LESSON PLAN

LP- CS 603
Date: 16-01-14
Sub Code : CS 403
Sub Name : Advanced Computer Archtecture
!ranch : CSE

"nt: # Seme$ter: #%
"nt $&''abu$:
Review of Pipelining, Examples of some pipeline in modern processors, pipeline hazards, data
hazards, control hazards. Techniques to handle hazards, performance improvement with
pipelines and effect of hazards on the performance.
Se$$on
No
Topics to be covered (me
E)pected
Comp'eton
*ee+
Actua'
Comp'eton
*ee+
1 Review of Pipelining 55m 1
st

, Examples of some pipeline in modern processors 55m 1
st
3 pipeline hazards 55m 1
st
4 data hazards 55m 1
st
- control hazards 55m 2
nd
6 Techniques to handle hazards 55m 2
nd
. performance improvement with pipelines 55m 2
nd
/
effect of hazards on the performance.
55m 2
nd
0 test 55m 2
nd
"nt $&''abu$:
Vector processors- Use and effectiveness, memory to memory vector architectures, vector
register architecture, vector length and stride issues, compiler effectiveness in vector
processors.
.
Se$$on
No (opc$ to be covered (me
E)pected
Comp'eto
n *ee+
Actua'
Comp'eton
*ee+
10 Vector processors 55m 2
nd
1111, Use and effectiveness 55m 3
rd
13 memory to memory vector architectures. 55m 3
rd
14 vector length and stride issues 55m 3
rd
1-
compiler effectiveness in vector processors 55m 3
rd
1611. test 55m
th
LESSON PLAN
LP- CS 403
Date: 16-01-14
Sub Code : CS 403
Sub Name : Advanced Computer Archtecture
!ranch : CSE

"nt: #! Seme$ter: #%
LESSON PLAN
LP- CS 403
Date: 16-01-14
Sub Code : "# $3
Sub Name : AD%ANCED CO2P"(E3 A3C4#(EC("3E
!ranch : CSE

"nt: ### Seme$ter: #%
"nt $&''abu$:
#!#%, &!#%, &!&%, #ingle instruction multiple data stream '#!&%( architectures.
)rray processors, comparison *ith vector processors, e+ample of array processors such
as &&, Technology.
Se$$on
No (opc$ to be covered (me
E)pected
Comp'eton
*ee+
Actua'
Comp'eton
*ee+
1/ #!#% 55m
th
10 &!#%, &!&%( 55m 5
th
,0
#ingle instruction multiple data stream '#!&%(
architectures
55m 5
th
,1 )rray processors 55m 5
th
,, comparison *ith vector processors 55m 5
th
,3 e+ample of array processors 55m 5
th
,4 test 55m -
th
LESSON PLAN
LP- CS 403
Date: 16-01-14
Sub Code : "# $3
Sub Name : AD%ANCED CO2P"(E3 A3C4#(EC("3E
!ranch : CSE

"nt: #% Seme$ter: #%
"nt $&''abu$:
&emory hierarchy, "ache !ntroduction, Techni.ues to reduce cache misses,
techni.ues to reduce cache penalties, techni.ue to reduce cache hit times. /ffect of
main memory band*idth, effect of bus-*idth, memory access time, virtual memory,
etc

Se$$on
No (opc$ to be covered (me
E)pected
Comp'eton
*ee+
Actua'
Comp'eton
*ee+
,- &emory hierarchy --m -
th
,6 "ache !ntroduction 55m -
th
,. Techni.ues to reduce cache misses
55m
-
th
,/ techni.ues to reduce cache penalties 55m -
th
,0 techni.ue to reduce cache hit times 55m -
th
30 /ffect of main memory band*idth 55m 0
th
31 effect of bus-*idth 55m 0
th
3, memory access time 55m 0
th
33 virtual memory 55m 0
th
LESSON PLAN
LP- CS 403
Date: 16-01-14
Sub Code : "# $3
Sub Name : AD%ANCED CO2P"(E3 A3C4#(EC("3E
!ranch : CSE

"nt: % Seme$ter: #%
"nt $&''abu$:
1!#" architectures, addressing modes, instructions formats, effect of simplification on
the performance, e+ample processors such as &!2#, 2)-1!#", #2)1", 2o*er 2", etc.
&!&!% &ultiprocessors, "entrali3ed shared architectures, distributed shared memory
architectures, synchroni3ation and memory consistency models, message passing
architectures, comelier issues. %ata flo* architectures, !nterconnection net*or4s.
Se$$on
No (opc$ to be covered (me
E)pected
Comp'eton
*ee+
Actua'
Comp'eton
*ee+
34 1!#" architectures --m 5
th
3- addressing modes 55m 5
th
36 instructions formats 55m 5
th
3. effect of simplification on the performance 55m 5
th
3/
e+ample processors such as &!2#, 2)-1!#",
#2)1", 2o*er 2", etc
55m 5
th

30 &!&!% &ultiprocessors 55m 5
th
40 "entrali3ed shared architectures 55m 6
th
41 distributed shared memory architectures 55m 6
th
4,
synchroni3ation and memory consistency
models
55m 6
th
43 message passing architectures 55m 6
th
44 comelier is$ue$ 55m 1$
th
4- !nterconnection net*or4s 55m 1$
th
46 test 55m 1$
th
LESSON PLAN
LP- CS 403
Date: 16-01-14
Sub Code : CS 403
#ub 7ame 8 )%V)7"/% "9&2UT/1 )1":!T/"TU1/
!ranch : CSE

Seme$ter: #%
Cour$e De'ver& P'an:
*ee+$ 1 , 3 4 - 6 . / 0 10 11 1, 13
"nt$
# ## ### #% %
CO"3SE (E5(
1. :;)7<, =. >)%V)7"/% "9&2UT/1 )1":!T/"TU1/ ;!T: 2)1)??/?
219<1)&&!7<@, &"<1); :!??, 1663
3E6E3ENCES
2. Hwang !riggs"#omputer $rchitecture Parallel Processing, T%H
3. "omputer 9rgani3ation A )rchitecture 'T&: ;BUT #eries(, <hosh A 2al,T&:
. 2atterson %.). and :ennessy , C.?. >"omputer architecture a .uantitative
approach@,
Prepared b& Approved b&
S7nature
Name Su+anta 8undu Prof.(Dr) Tapan Kumar Chattopadhyay
De$7naton A$$$tant Pro9e$$or Prncpa'1 :2#(
Date 16;01;,014 16;01;,014