International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)

Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com

Volume 3, Issue 3, May-June 2014 ISSN 2278-6856

Volume 3, Issue 3 May June 2014 Page 219


Abstract: Visual surveillance has attracted much attention
in the computer vision community due to its potential
applications. The making of real time video surveillance
systems requires fast and reliable algorithm for moving
object detection. This paper an algorithm to detect moving
objects in a scene acquired by a stationary camera. As
algorithm has low calculation complexity, it is suitable for
real time embedded system. Accuracy of this algorithm is
tested by implementing this algorithm in MATLAB tool.
Same algorithm is implemented by Micro blaze soft core
processor. The algorithm is written in system C Language
and tested in SPARTAN-3 XC3S200TQ-144 FPGA by
interfacing a test circuit with the PC using the RS232 cable.

Keywords: Video surveillance, morphological operation,
FPGA, Micro Blaze, EDK

1. INTRODUCTION
Real-time moving object detection is critical for a number
of embedded applications such as security surveillance
and visual tracking. Moving object detection often acts as
an initial step for further processing such as classification
of the detected moving object. In order to perform more
sophisticated operations such as classification, we need to
use an efficient as well as accurate algorithm for moving
object detection. For real time performance computational
complexity has to be minimum.
Computationally, real-time computer vision is an
expensive task due to the fact that even small images need
to be submitted to many processes. So that large
quantities of calculations are need to be avoided [2]. We
have used background subtraction based algorithm which
is not a computationally expensive algorithm and also
presents high performance in terms of accuracy. In this
work we propose the implementation of an efficient object
detecting system on FPGA that could be employed in a
wide range of embedded systems providing high-
performance and low-power [3]. Performance of
algorithm is tested by using MATLAB tool and
implemented by using Xilinx MicroBlaze soft-core
processor.
To monitor the scene reliably it is essential that the
processing time per frame be as low as possible. Hence it
is important that the techniques which are employed are
as simple and as efficient as possible. For that reason the
well known technique of background subtraction is
selected for this application. Background subtraction
allows moving objects to be detected by taking the point-
by-point absolute difference of the current image and a
background image which must be acquired when there
are no moving objects in the scene. . Its expression is as
follows [3]-[5]-[6]:
D(X, Y) = 1 if (|FK(X, Y) B(X, Y) |> T)
(1)
= 0 others
Where D(X, Y) is a binary image of differential results.
But only background subtraction method is very sensitive
to the changes in the external environment. The methods
with a background model cannot cope with multi-valued
background distributions. As such, they will be prone to
errors whenever those situations arise. However, if such
errors connect into relatively small blobs, they can be
removed from the classified image by a special filter.
After median filtering operations on difference image,
some accurate edge regions may be obtained [3]. Median
filtering is one kind of smoothing technique[8]. All
smoothing techniques are effective at removing noise in
smooth patches or smooth regions of a signal, but
adversely affect edges. Same time it is important to
preserve the edges. So that performance may not up to the
mark. To find the median value, it is necessary to sort all
the values in the neighborhood into numerical order that
leads process becomes relatively slower.
Morphological closing operation tends to fuse narrow
break and also eliminate small holes. After applying
morphological closing operation some accurate edge may
be obtained and moving object will be detected.
Processing time required to detect the object using this
technique is low but accuracy may not be good enough.
In background subtraction approach current frame (pixel
by pixel) is subtracted from a reference image called
background image. Afterward, the resulting image from
the subtraction is segmented in order to produce a binary
image that highlights the moving regions on the image
that belongs to the moving objects. Difference image
contains the motion region along with noise. Therefore,
noise needs to be removed.

2. Technique used
This paper adopts filter mask w(x, y) with the 3x3
window to filters out noise. All coefficients of this mask
are 1. Correlation of filter w(x, y) with image f(x, y)
denotes as w(x, y)*f(x, y).
w(x, y)*f(x, y) = 1 if
>4
=0 Otherwise (2)

Eq. (2) shows that proposed 3x3 mask counts number of
non-zero elements in original binary image. If count is
Moving Object Detection Using FPGA

Mr. Mahesh C. Pawaskar
1
, Mr. N. S.Narkhede
2
and Mr. Saurabh S. Athalye
2


1
Department of Electronics and Telecommunication Engineering,
Rajendra Mane College Of Engineering. Ambav.

2
Department Of Electronics Engineering,
Shah And Anchor Kutchhi Engineering College, Mumbai.

International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 3, Issue 3, May-June 2014 ISSN 2278-6856

Volume 3, Issue 3 May June 2014 Page 220


more than 4 then center value is replaced by 1 otherwise
center value is replaced by 0. As this mask is working on
binary numbers, it requires least calculation time, it also
fuse narrow break and eliminate small holes. It combines
advantages of median filter mask and morphological
closing operation. Flow of Technique can be explained as
follows:
1. Input a video
2. Extract the frame
3. Take absolute difference of the current image and a
background image
4. Select proper threshold level to convert subtracted
image into binary image
5. Convolve proposed 3x3 masks with binary image to
filter out noise.
6. B(x, y)=1 represent foreground and B(x, y)=0
represent background

3. EXPERIMENTAL RESULT
3.0 Sequence Hall monitor
Sequence Hall monitor is an indoor sequence consisting
of 287 frames of 320 x 240 spatial resolutions, acquired at
a frequency of 30 fps (frames per second). The scene
consist hall, where a man comes out, leaves a bag on the
floor, and then goes in the room. While the first man
passes, the another man comes into the hall and moves
towards the room. It represents an example of easy
sequence, in that lighting conditions are quite stable and
moving objects are well contrasted with the background
(there is no camouflage); however, strong shadows cast by
moving objects can be observed in the entire sequence [4].


(a) (b) (c)

(d) (e)
Figure 3.1 (a) Frame to be tested (Frame No. 185)
(b)Image after morphological closing operation (c)
Median filtered Image (d) Proposed method result
(d)Ground Truth Image

Table 1: Result of sequence Hall Monitor
Paramete
r
Technique
Recall 0.7273
Precision 0.9123
F1 0.8094
Similarity 0.6798

3.1 Sequence water surface
Sequence water surface consisting 60 frames of 160 x 120
spatial resolutions, captured at a frequency of 15 fps. The
outdoor scene includes (moving) waves of water in the
background and, finally, a man passing in front of the
camera; here we are not interested in the waving water,
but only in extraneous moving objects (the man) [4].
(a) (b) (c)

(d) (e)
Figure 3.2 (a) Frame to be tested (Frame No. 25)
(b)Image after morphological closing operation (c)
Median filtered Image (d) Proposed method result
(d)Ground Truth Image

Results for accuracy of sequence Water surface is given in
table no. 2.
Table No. 2 : Result of sequence Water Surface
Parameters Proposed
Method
Recall 0.7413
Precision 0.9009
F1 0.8133
Similarity 0.6854

4. PROPOSED BACKGROUND
MODELING
There are different ways to include processors inside
Xilinx FPGA for System-on-a-Chip (SoC): PowerPC hard
processor core, or Xilinx MicroBlaze soft processor core,
or user-defined soft processor core in VHDL/Verilog. In
this work, The 32-bit MicroBlaze processor is chosen
because of the flexibility. The user can modify the
processor with or without advance features, based on the
budget of hardware. The advance features include
memory management unit, floating processing unit,
hardware multiplier, hardware divider, instruction and
data cache links etc.
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 3, Issue 3, May-June 2014 ISSN 2278-6856

Volume 3, Issue 3 May June 2014 Page 221


In the first step we consider the video and extract frames.
We have selected one of the image in which object is to be
detected. Another image is Background. For these two
images we create a header file. And then we can write an
algorithm for back ground subtraction in the XPS tool by
using system C language. In the XPS we are giving two
inputs of headerfile.h and source file.c. XPS is a tool used
to link a program to hardware like FPGA. After
downloading the bit stream open the visual basics
application and click run button on the command window
of XPS .Finally with the help of UART port and RS232
cable we made a communication between hard ware and
our PC and we can see the output image in the PC with
the help of visual basis tool.

Figure 4.1 Block diagram of moving object detection
using FPGA

The software side follows the standard embedded software
flow to compile the source codes into an executable and
linkable file (ELF) format. Meanwhile, a microprocessor
software specification (MSS) file and a microprocessor
hardware specification (MHS) file are used to define
software structure and hardware connection of the system.
The EDK uses these files to control the design flow and
eventually merge the system into a single downloadable
file. The whole design runs on a real-time operating
system (RTOS).

Figure 4.2 Embedded Development Kit Design Flow

Downloading bitstream to FPGA
Select the Device Configuration and download Bitstream,
XPS downloads the bitstream (download.bit file) onto the
target board using iMPACT in batch mode. XPS uses the
file etc/download.cmd for downloading the bitstream.
Because XPS tools are make file based, the download
button calls on the make file and executes the steps
necessary to create the bitstream with the ELF file
populated within the bitstream.

5. EXPERIMENTAL RESULTS
SPARTAN-3 XC3S200TQ-144 FPGA is used to
implement this work. There are the object detection
images in the visual basics tool. Figure 5.1 is input
images without moving object and another one with
moving object. Finally in the output image we can
observe the object without background. Device utilization
of FPGA is shown in table number 3-

Figure 5.1 Background image


Figure 5.2 Image with object


Figure 5.3 Image without background (Binary image)
International Journal of Emerging Trends & Technology in Computer Science (IJETTCS)
Web Site: www.ijettcs.org Email: editor@ijettcs.org, editorijettcs@gmail.com
Volume 3, Issue 3, May-June 2014 ISSN 2278-6856

Volume 3, Issue 3 May June 2014 Page 222


Table 3 Device utilization summary [9]
Logic Utilization Used Available Utilization
Number of Slices 1,517 1,920 79%
Number of Flip Flops 1,572 3,840 40%
Number of bonded
IOBs
62 97 63%
4 input LUTs 2,417 3,840 62%
Number of RAMB16s 4 12 33%
MULT18X18s 3 12 25%
Number of DCMs 1 4 25%


Figure 5.4 graph of device utilization

6. CONCLUSION
In this work a moving object detection based on
background subtraction algorithm is used on a
reconfigurable hardware. Algorithm is efficiently
identifying a moving object with least complex
calculation. The system works on a real-time pipelined
flow. The system will be capable to detect an object by
extracting its shape. The image containing moving object
will be send to a PC or another platform via RS-232
interface. Implementation of this system on low-cost
FPGAs is possible, and it presents good results.

References
[1] C. Sanchez-Ferreira, J. Y. Mori, C. H. Llanos
Background Subtraction Algorithm for Moving
Object Detection in FPGA 2012 IEEE
[2] Su Liu, Alexandros Papakonstantinou, Hongjun
Wang, Deming Chen Real-Time Object Tracking
System on FPGAs 2011 Symposium on Application
Accelerators in High-Performance Computing pp 1-4
[3] M.Kalpana Chowdary , S.Suparshya Babu,
S.Susrutha Babu, Dr.Habibulla Khan FPGA
Implementation of Moving Object Detection in
Frames by Using Background Subtraction
Algorithm International conference on
Communication and Signal Processing, April 3-5,
2013, India 2013 IEEE pp 1032-1036.
[4] Lucia Maddalena and Alfredo Petrosino A Self-
Organizing Approach to Background Subtraction for
Visual Surveillance Applications IEEE transaction
on image processing, Vol. 17, No. 7, July 2008, pp
1168-1177
[5] Lijing Zhang, Yingli Liang Motion human detection
based on background Subtraction 2010 Second
International Workshop on Education Technology
and Computer Science, pp 284-287
[6] Massimo Piccardi Background subtraction
techniques: a review 2004 IEEE International
Conference on Systems, Man and Cybernetics, pp
3099-3104
[7] K.Kinoshita, M.Enokidani, M. Izumida and
K.Murakami, "Tracking of a Moving Object Using
One-Dimensional Optical Flow with a Rotating
Observer," Control, Automation, Robotics and
Vision, 2006. ICARCV '06. 9th International
Conference on 5-8 Dec. 2006 pp 1 6
[8] Rafael C. Gonzalez, Richard E. Woods Digital
Image Processing Pearson Education South Asia Ltd pp
630-639
[9] http://www.xilinx.com/support/documentation/data_s
heets/ds099.pdf