fsm

© All Rights Reserved

34 vues

fsm

© All Rights Reserved

- 3rd sem and 4th sem ece
- Std12-Voc-EE--EM
- Fsm
- VLSI FAQs
- MELJUN CORTES Shift Register and Counter
- Ecad Lab Manual
- Best Design Practices for DFT
- Bel 14 Sequential Logic
- Fsm
- Lab 8
- Flat
- Chapter 01 - Introduction
- IEEE Control Petri Nets and 61850
- SerDes_45nm
- Cryptography
- Dual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications
- DFT
- Lesson Plan De
- lab7-8
- Introduction to FLIP FLOPS

Vous êtes sur la page 1sur 85

com 1

Finite State Machines

Session Speaker :

Selva Kumar. R

Selvakumar @ vkmselva@gmail.com 2

Session Objectives

To understand a FSM

To understand pros and cons of Mealy Machines

To design sequential circuits using FSMs

Selvakumar @ vkmselva@gmail.com 3

Session Topics

FSMs

Moore

Mealy

Design of Sequence Detector

Case Study

Selvakumar @ vkmselva@gmail.com 4

Combinational circuits can be represented using truth

tables.

Truth table is not an adequate model for a sequential

circuit.

FSMs are important in sequential circuit design

Introduction

Selvakumar @ vkmselva@gmail.com 5

A state machine is an effective way to implement

control functions.

A state machine works in two phases.

The new state is calculated

The new state is sampled into a register

A basic form of state machine is a sequential circuit

in which the next state and the circuit outputs depend

on the current state and the inputs.

Finite State Machines

Selvakumar @ vkmselva@gmail.com 6

Finite State Machines

Any Circuit with Memory Is a Finite State Machine

Even computers can be viewed as huge FSMs

Design of FSMs Involves

Defining states

Defining transitions between states

Selvakumar @ vkmselva@gmail.com 7

State Machines: Definition of Terms

State Diagram

Illustrates the form and

function of a state machine.

Usually drawn as a bubble-

and-arrow diagram.

State

A uniquely identifiable set

of values measured at various

points in a digital system.

Next State

The state to which the state

machine makes the next

transition, determined by the

inputs present when the

device is clocked.

Branch

A change from present state

to next state.

Mealy Machine

A state machine that

determines its outputs from

the present state and from the

inputs.

Moore Machine

A state machine that

determines its outputs from

the present state only.

Selvakumar @ vkmselva@gmail.com 8

Present State and Next State

On a well-drawn state diagram, all possible transitions will be visible, including

loops back to the same state. From this diagram it can be deduced that if the

present state is State 5, then the previous state was either State 4 or 5 and the

next state must be either 5, 6, or 7.

State 6

State 7

State 5

State 4

For any given state, there is a finite

number of possible next states. On

each clock cycle, the state machine

branches to the next state. One of

the possible next states becomes the

new present state, depending on the

inputs present on the clock cycle.

Selvakumar @ vkmselva@gmail.com 9

Moore and Mealy Machines

Both these machine types follow the basic characteristics

of state machines, but differ in the way that outputs are

produced.

Moore Machine:

Outputs are independent of the inputs, ie outputs are

effectively produced from within the state of the state

machine.

Mealy Machine:

Outputs can be determined by the present state alone,

or by the present state and the present inputs, ie outputs

are produced as the machine makes a transition from

one state to another.

Selvakumar @ vkmselva@gmail.com 10

Machine Models

Inputs

Combinatorial

Logic to

Determine State

Present State

Register Bank

Combinatorial

Logic to

Determine

Output Based on:

Present State

Output

Moore Machine

Inputs

Combinatorial

Logic to

Determine State

Present State

Register Bank

Combinatorial

Logic to

Determine

Output Based on:

Present State

Present Inputs

Output

Mealy Machine

Inputs

Combinatorial

Logic to

Determine State

Present State

Register Bank

Combinatorial

Logic to

Determine

Output Based on:

Present State

Output

Moore Machine

Inputs

Combinatorial

Logic to

Determine State

Present State

Register Bank

Combinatorial

Logic to

Determine

Output Based on:

Present State

Present Inputs

Output

Mealy Machine

Selvakumar @ vkmselva@gmail.com 11

Properties of State Diagram

Mealy machines and moore machines can be

labelled differently

Mealy machine: since output depends on state and

inputs:

Label directed arcs with input/output for that state

transition

Moore machine: Since output depends only on state:

Label directed arcs with input for that state transition.

Label state circles with S

k

/output.

Selvakumar @ vkmselva@gmail.com 12

Moore Machine Diagrams

State 2

x,y

State 1

q,r

a,b

i,j

Input condition that

must exist in order

to execute these

transitions from

State 1

Output condition that

results from being in

a particular present

state

The Moore State Machine

output is shown inside the

state bubble, because the

output remains the same as

long as the state machine

remains in that state.

The output can be arbitrarily

complex but must be the

same every time the

machine enters that

state.

Selvakumar @ vkmselva@gmail.com 13

Mealy Machine Diagrams

State 2

State 1

a,b

q,r

i,j

x,y

Input condition that

must exist in order

to execute these

transitions from

State 1

Output condition that

results from being in

a particular present

state

The Mealy State Machine generates

outputs based on:

The Present State, and

The Inputs to the M/c.

So, it is capable of generating many

different patterns of output signals

for the same state, depending on the

inputs present on the clock cycle.

Outputs are shown on transitions

since they are determined in the

same way as is the next state.

Selvakumar @ vkmselva@gmail.com 14

Moore Machine

Describe Outputs as Concurrent Statements Depending on

State Only

state 1 /

output 1

state 2 /

output 2

transition

condition 1

transition

condition 2

Selvakumar @ vkmselva@gmail.com 15

Mealy Machine

Describe Outputs as Concurrent Statements Depending on

State and Inputs

state 1

state 2

transition condition 1 /

output 1

transition condition 2 /

output 2

Selvakumar @ vkmselva@gmail.com 16

Moore vs. Mealy FSM (1)

Moore and Mealy FSMs Can Be Functionally Equivalent

Mealy FSM Has Richer Description and Usually Requires

Smaller Number of States

Smaller circuit area

Selvakumar @ vkmselva@gmail.com 17

Moore vs. Mealy FSM (2)

Mealy FSM Computes Outputs as soon as Inputs Change

Mealy FSM responds one clock cycle sooner than equivalent

Moore FSM

Moore FSM Has No Combinational Path Between Inputs

and Outputs

Selvakumar @ vkmselva@gmail.com 18

Next State

Moore FSM

Output Is a Function of Present State Only

Describe Outputs as Concurrent Statements Depending on State

Only

Outputs

Inputs

Memory

(register)

Transition

function

Output

function

Present State

transition

condition 1

transition

condition 2

state 1/

output 1

state 2/

output 2

Selvakumar @ vkmselva@gmail.com 19

Mealy FSM

Output Is a Function of a Present State and Inputs

Describe Outputs as Concurrent Statements Depending on State and

Inputs

Inputs

Outputs

Memory

(register)

Transition

function

Output

function

Present State

Next State

transition

condition 1/

output 1

state 1

state 2

transition

condition 2/

output 2

Selvakumar @ vkmselva@gmail.com 20

Elements of a Diagram

A state diagram represents a finite state machine(FSM)

and contains

Circles: represent the machine states

Labeled with a binary encoded number or S

k

reflecting state

Directed arcs: represent the transitions between states

Labeled with input/output for that state transition

Selvakumar @ vkmselva@gmail.com 21

Properties of State Diagram

Some restrictions that are placed on the state

diagrams

FSM can only be in one state at a time!

Therefore only in one state, or one circle, at a time.

State transitions are followed only on clock cycles

(synchronous!)

Selvakumar @ vkmselva@gmail.com 22

0

0

1

1

1

Moore FSM - Example 1

Moore FSM that Recognizes Sequence 10

S2 / 1

0

reset

Meaning

of states:

S0: No

elements

of the

sequence

observed

S1: 1

observed

S2: 10

observed

S1 / 0 S0 / 0

Selvakumar @ vkmselva@gmail.com 23

Mealy FSM - Example 1

Mealy FSM that Recognizes Sequence 10

S0 S1

0 / 0

1 / 0 1 / 0

0 / 1

reset

Meaning

of states:

S0: No

elements

of the

sequence

observed

S1: 1

observed

Selvakumar @ vkmselva@gmail.com 24

Moore & Mealy FSMs Example 1

clock

input

Moore

Mealy

0 1 0 0 0

S0 S1 S2 S0 S0

S0 S1 S0 S0 S0

Selvakumar @ vkmselva@gmail.com 25

Sequence detector

To detect two consecutive 1s in an input sequence.

Output will indicate if there are two immediate 1s.

Sequence

detector

sequence

clock

output

Clockcycle : t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

w : 0 1 0 1 1 0 1 1 1 0 1

z : 0 0 0 0 0 1 0 0 1 1 0

To read a serial bit stream of data

Example of sequential circuit

Selvakumar @ vkmselva@gmail.com 26

Realized using combinational logic and flip-flops

Primary inputs: w

Outputs: z

State: Q

Moore FSMs: outputs depend only on the state

Mealy FSMs: outputs depend on both state and primary inputs

Combinational

circuit

Flip-flops

Clock

Q

W

Z

Combinational

circuit

General form of a sequential circuit

Selvakumar @ vkmselva@gmail.com 27

Specifications:

The circuit has one input, w, and one output, z.

All changes in the circuit occur on the positive edge of

a clock signal.

The output z is equal to 1 if during two immediately

preceding clock cycles the input w was equal to 1.

otherwise, the value of z is equal to 0.

Clockcycle : t

0

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

w : 0 1 0 1 1 0 1 1 1 0 1

z : 0 0 0 0 0 1 0 0 1 1 0

Manual design steps (1): specifications

Selvakumar @ vkmselva@gmail.com 28

starting state A: when power is on or reset signal

is applied.

As long as w is 0, it remains in A.

After w 1, it moves to state B.

Then,

If w 0, it moves back to state A.

If w 1, it moves to state C, and z=1.

When in state C,

If w 0, back to state A, and z=0;

If w 1, remain in state C.

Manual design steps (2): specifications

Selvakumar @ vkmselva@gmail.com 29

State diagram of a simple sequential circuit.

C z 1 =

Reset

B z 0 = A z 0 = w 0 =

w 1 =

w 1 =

w 0 =

w 0 = w 1 =

Manual design steps (3): specifications

Selvakumar @ vkmselva@gmail.com 30

From the state diagram, we have the state table

Present

Next state

Output

state

w = 0 w = 1

z

A A B 0

B A C 0

C A C 1

Combinational circuit

Combinational

circuit

Flip-flops

Manual design steps (4): specifications

Selvakumar @ vkmselva@gmail.com 31

Present

Next state

state

w = 0 w = 1

Output

y

2

y

1

Y

2

Y

1

Y

2

Y

1

z

A 00 00 01 0

B 01 00 10 0

C 10 00 10 1

11 dd dd d

A: 00

B: 01

C: 10

Manual design steps (5): specifications

Selvakumar @ vkmselva@gmail.com 32

Combinational

circuit

Combinational

circuit

Clock

y

2

z

w

y

1

Y

1

Y

2

Generate next state

Generate output

Next state

current state

Circuit diagram

Selvakumar @ vkmselva@gmail.com 33

Specifications

Derive the states, and create a state diagram

Create a state table

State assignment

Chose flip-flops

Derive logic expressions for state and outputs

Implementation

Summary of design steps

Selvakumar @ vkmselva@gmail.com 34

Trigger alternatives

For flip flops, the clock event can either be a positive or

negative edge

Both have same next-state table

clk

Positive edge triggered

Flip Flop

Q D

C

Negative edge triggered Flip

Flop (bubble indicates negative

edge)

clk

Q D

C

D

0

0

1

1

Q

0

1

0

1

Q+

0

0

1

1

Current

state, now

Next state, after

clock event

Clock Events on Other Planets

Selvakumar @ vkmselva@gmail.com 35

Note how the reset is connected

Reset will make both of the FFs zero, thus putting them into state A.

Most FFs have both reset and preset inputs (preset sets the FF to one).

The reset connections (to FF reset and preset) are determined by the state

assignment of the reset state.

Reset

Clock

x

Q1

Q2

Q2

z

D1 Q1

reset

D2 Q2

reset

Moore Machine 111 Detector

Selvakumar @ vkmselva@gmail.com 36

Pattern Detection Example

Suppose we want a sequential system that has the

following behaviour.

Effectively, the system should output a 1 when the last set of

four inputs have been 1101.

For instance, the following output z(t) is obtained for the

output input x(t).

Selvakumar @ vkmselva@gmail.com 37

Pattern Detection Example

The following state diagram gives the behaviour of the desired

1101 pattern detector.

Consider s

0

to be the initial state, s1 when first symbol detected

(1), s

2

when sub pattern 11 detected, and s3 when sub pattern 110

detected.

Selvakumar @ vkmselva@gmail.com 38

State Tables

State tables also express a systems behaviour and consists of

Present state

The present state of the system, typically given in the binary

encoded form or with s

k

. So, a state of s

5

in our state diagram

with 10 states would be represented as 0101 since we require

4 bits.

Inputs

Whatever external inputs used to cause the state transitions.

Next state

The next state, generally in binary encoded form.

Outputs

Whatever outputs, other than the state, for the system. Note

that there would be no outputs in a moore machine.

Selvakumar @ vkmselva@gmail.com 39

Pattern Detect Example

If we consider the pattern detection example

previously discussed, the following would be the

state table.

Selvakumar @ vkmselva@gmail.com 40

Translate to Diagram

If given a state table, the state diagram can be developed as

follows.

Determine the number of states in the table and draw a state

circle corresponding to each one.

Label the circle with the state name for a mealy machine.

Label the circle with the state name/output for a moore

machine

For each row in the table, identify the present state circle and

draw a directed arc to the next circle.

Label the arc with the input/output pair for a mealy machine.

Label the arc with the input for a moore machine.

Selvakumar @ vkmselva@gmail.com 41

Sequential circuits

With the descriptions of a FSM as a state diagram and a state

table, the next question is how to develop a sequential circuit,

or logic diagram from the FSM.

Effectively, we wish to form a circuit as follows.

Selvakumar @ vkmselva@gmail.com 42

Sequential circuits

The procedure for developing a logic circuit from a state table is the

same as with a regular truth table.

Generate Boolean functions for

Each external outputs using external inputs and present state bits

Each next state bit using external inputs and present state bits.

Use Boolean algebra, Karnaugh maps, etc. as normal to simplify.

Draw a register for each state bit.

Draw logic diagram components connecting external outputs to

external inputs and outputs of state bit registers(which have the

present state.)

Draw logic diagram components connecting inputs of state bits (for

next state) to the external inputs and outputs of state bit

registers(which have the present state).

Selvakumar @ vkmselva@gmail.com 43

Pattern Detect Example

Following the procedure outlined, Boolean functions

for the pattern detector state table can be formed using

Karnaugh maps as follows.

Selvakumar @ vkmselva@gmail.com 44

Pattern Detect Example

Notice that the previous Boolean functions can also

be expressed with time as follows.

An important thing to note in these equations is the

relation between the present states P and the next

states N.

Selvakumar @ vkmselva@gmail.com 45

Pattern Detect Example

The following logic circuit implements the pattern

detect example

Selvakumar @ vkmselva@gmail.com 46

FSM Examples

Consider the following system description

A sequential system has

One bit inputs = { a,b,c }

One bit outputs = { p,q }

Output is

q when input sequence has even # of as and

odd # of bs

p otherwise

Selvakumar @ vkmselva@gmail.com 47

FSM Example

We begin forming a state machine for the system

description by reviewing the possible states. In

addition, assign each state name.

S

EE

: even # of as and even # of bs/output is p

S

EO

: even # of as and odd # of bs/output is q

S

OO

: odd # of as and odd # of bs/output is p

S

OE

: odd # of as and even # of bs/output is p

Note that this machine can be a moore machine. So,

we can associate the output with each state.

Selvakumar @ vkmselva@gmail.com 48

FSM Example

Now draw a circle with each state

Selvakumar @ vkmselva@gmail.com 49

FSM Example

Finally, for each state, consider the effect for each

possible input.

For instance, starting with state SEE, the next state for the

three input a, b, and c are determined as follows.

Selvakumar @ vkmselva@gmail.com 50

FSM Example

Finishing the state diagram, the following is obtained.

Selvakumar @ vkmselva@gmail.com 51

FSM Example

A state table can also be formed for this state diagram as

follows.

First, assign a binary number to each state

SEE = 00, SEO = 01, SOO = 10, SOE = 11

Assign a binary number to each input

a = 00, b = 01, c = 10

Assign a binary number to each output

p = 0, q = 1

Then for each state, find the next state for each input. In this

case there are three possible input values, so, three possible state

transitions from each state.

The state table on the following slide shows the results for

this example.

Selvakumar @ vkmselva@gmail.com 52

FSM Example

Selvakumar @ vkmselva@gmail.com 53

FSM Example

The Boolean function for the output can be determined

from a Karnaugh map as follows.

Note that an input 11 is not possible since we only have three

inputs that we have assigned to 00, o1 and 10. We can

therefore use dont cares for this possible input.

Selvakumar @ vkmselva@gmail.com 54

FSM Example

The Boolean function for the next state bit can also be

determined from Karnaugh maps as follows

Selvakumar @ vkmselva@gmail.com 55

FSM Example

The following logic circuit can be made with these

Boolean functions

Selvakumar @ vkmselva@gmail.com 56

FSM Example

A sequential circuit is defined by the following Boolean

functions with input X, present states P0, P1 and P2 and next

states N0, N1 and N2

Derive the state table

Derive the state Diagram

Selvakumar @ vkmselva@gmail.com 57

FSM Example

The state table is formed as follows.

Selvakumar @ vkmselva@gmail.com 58

FSM Example

The state Diagram can be drawn as follows

Selvakumar @ vkmselva@gmail.com 59

Moore Machine Example

The following table describes a Moore state machine.

The machine has a single input signal x and a single

output signal z. Using the encoding for each state shown

in column one, derive next state equations for each state

bit of the state machine, and also an equation for the

output bit z.

Selvakumar @ vkmselva@gmail.com 60

Moore Machine - Example

Taking the state code as bits D2D1D0 then gives

K-maps for each state bit as:

Selvakumar @ vkmselva@gmail.com 61

Moore Machine - Example

For D1

For D2

Selvakumar @ vkmselva@gmail.com 62

Moore Machine - Example

For output Z

Selvakumar @ vkmselva@gmail.com 63

Counter Design

Design a counter to produce an

output count in gray code, i.e.

0000010110101

10111101100000

Produce an FSM chart for the

design. From the FSM chart

produce a state tables using the

following state assignments:

i. binary coded

decimal

ii. gray code

Implement both designs the

counter using D-type flip-flops,

NAND gates and inverters.

Selvakumar @ vkmselva@gmail.com 64

Counter Design

i) binary coded decimal

8 states, therefore 3

flip-flops required, state

vector (code) ABC.

State vectors are

S0=000, S1=001,

S2=010, S3=011,

S4=100, S5=101,

S6=110, S7=111.

Selvakumar @ vkmselva@gmail.com 65

Counter Design

Selvakumar @ vkmselva@gmail.com 66

Counter Design - Implementation

Selvakumar @ vkmselva@gmail.com 67

Counter Design

ii) gray code

8 states,

therefore 3 flip-

flops required, state

vector (code) ABC.

State vectors are

S0=000,

S1=001, S2=011,

S3=010, S4=110,

S5=111, S6=101,

S7=100.

Selvakumar @ vkmselva@gmail.com 68

Counter Design

Selvakumar @ vkmselva@gmail.com 69

Counter Design - Implementation

Selvakumar @ vkmselva@gmail.com 70

Finite string pattern recognizer (step 1)

Finite string pattern recognizer

one input (X) and one output (Z)

output is asserted whenever the input sequence 010has

been observed, as long as the sequence 100has never been

seen

Step 1: understanding the problem statement

sample input/output behavior:

X: 0 0 1 0 1 0 1 0 0 1 0

Z: 0 0 0 1 0 1 0 1 0 0 0

X: 1 1 0 1 1 0 1 0 0 1 0

Z: 0 0 0 0 0 0 0 1 0 0 0

Selvakumar @ vkmselva@gmail.com 71

Finite string pattern recognizer (step 2)

Step 2: draw state diagram

for the strings that must be recognized, i.e., 010

and 100

a Moore implementation

S1

[0]

S2

[0]

0

1

S3

[1]

0

S4

[0]

1

0 or 1

S5

[0]

0

0

S6

[0]

S0

[0]

reset

Selvakumar @ vkmselva@gmail.com 72

Finite string pattern recognizer

Exit conditions from state S3: have

recognized 010

if next input is 0 then have 0100

= ...100 (state S6)

if next input is 1 then have 0101

= 01 (state S2)

Exit conditions from S1: recognizes

strings of form 0 (no 1 seen)

loop back to S1 if input is 0

Exit conditions from S4: recognizes

strings of form 1 (no 0 seen)

loop back to S4 if input is 1

1

...01

...010 ...100

S4

[0]

S1

[0]

S0

[0]

S2

[0]

1 0

1

reset

0 or 1

S3

[1]

0

S5

[0]

0

0

S6

[0]

...1 ...0

1 0

Selvakumar @ vkmselva@gmail.com 73

Finite string pattern recognizer

S2 and S5 still have incomplete

transitions

S2 = 01; If next input is 1,

then string could be prefix of

(01)1(00)

S4 handles just this case

S5 = 10; If next input is 1,

then string could be prefix of (10)1(0)

S2 handles just this case

Reuse states as much as possible

look for same meaning

state minimization leads to

smaller number of bits to

represent states

Once all states have a complete

set of transitions we have a

final state diagram

1

...01

...010 ...100

S4

[0]

S1

[0]

S0

[0]

S2

[0]

1 0

1

reset

0 or 1

S3

[1]

0

S5

[0]

0

0

S6

[0]

...1 ...0

1 0

...10

1

1

Selvakumar @ vkmselva@gmail.com 74

Implementation

Implementation

NS0 = CS0Q2 + CS2X + CS1CS2X + CS0X

NS1 = CS1X + CS0CS2 + CS0CS1 + CS2X

NS2 = CS0CS2X + CS1CS2X + CS0CS1X

Z = CS0CS1CS2

X X X 1 1 1 1

X X X 0 1 1 1

0 1 1 1 0 1 1

0 1 1 0 0 1 1

0 1 0 1 1 0 1

0 1 1 0 1 0 1

0 0 1 1 0 0 1

1 0 1 0 0 0 1

0 1 0 1 1 1 0

0 1 1 0 1 1 0

0 0 1 1 0 1 0

1 1 0 0 0 1 0

0 1 0 1 1 0 0

1 0 0 0 1 0 0

0 0 1 1 0 0 0

1 0 0 0 0 0 0

NS2 NS1 NS0 X CS2 CS1 CS0

R

D Q

R

D Q

P010

P100

Reset

X

Clk

Selvakumar @ vkmselva@gmail.com 75

Complex counter

Mode Input M

0

0

1

1

1

0

0

Current State

000

001

010

110

111

101

110

Next State

001

010

110

111

101

110

111

A synchronous 3-bit counter has a mode control M

when M = 0, the counter counts up in the binary sequence

when M = 1, the counter advances through the Gray code sequence

binary: 000, 001, 010, 011, 100, 101, 110, 111

Gray: 000, 001, 011, 010, 110, 111, 101, 100

Valid I/O behavior (partial)

Selvakumar @ vkmselva@gmail.com 76

Complex counter (state diagram)

Deriving state diagram

one state for each output combination

add appropriate arcs for the mode control

S0

[000]

S1

[001]

S2

[010]

S3

[011]

S4

[100]

S5

[101]

S6

[110]

S7

[111]

reset

0

0 0 0 0 0 0 0

1

1

1

1

1 1

1

1

Selvakumar @ vkmselva@gmail.com 77

Selvakumar @ vkmselva@gmail.com 78

Selvakumar @ vkmselva@gmail.com 79

Selvakumar @ vkmselva@gmail.com 80

Selvakumar @ vkmselva@gmail.com 81

Selvakumar @ vkmselva@gmail.com 82

Selvakumar @ vkmselva@gmail.com 83

Gray encoded state machines

Similar to binary encoded state machines.

State sequence has the property that only one

output changes when sequencing between states.

Can have lower power

Can be asynchronously sampled in some systems.

There may be unused states.

State Encoding

Selvakumar @ vkmselva@gmail.com 84

State Encoding

One-Hot Finite State Machines

One flip-flop for each state in the machine

Normal operation has exactly one flip-flop set; all other

flip-flops reset.

Next state logic equations for each flip-flop depend

solely on a single state (flip-flop) and external inputs.

Natural for FPGAs

There will be unused states

Selvakumar @ vkmselva@gmail.com 85

Summary

Any Circuit with Memory Is a Finite State Machine

Moore FSMs have been found advantageous for stability

Mealy machines are used for speed

State Encoding Can Have a Big Influence on Optimality

of the FSM Implementation

- 3rd sem and 4th sem eceTransféré parVenkatesh Venu
- Std12-Voc-EE--EMTransféré parkalaikalai360
- FsmTransféré partechdocs2
- VLSI FAQsTransféré parapi-27099960
- MELJUN CORTES Shift Register and CounterTransféré parMELJUN CORTES, MBA,MPA
- Ecad Lab ManualTransféré parKiran Vudugu
- Best Design Practices for DFTTransféré parnirajthakkar
- Bel 14 Sequential LogicTransféré parBharavi K S
- FsmTransféré parBunna Kal
- Lab 8Transféré parbulkSoft
- FlatTransféré parGanesh Singh
- Chapter 01 - IntroductionTransféré parprinceji
- IEEE Control Petri Nets and 61850Transféré parJose de Sa
- SerDes_45nmTransféré parNitin Patel
- CryptographyTransféré parkpsamy1983
- Dual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power ApplicationsTransféré parIJSRP ORG
- DFTTransféré parMuhsin Nk
- Lesson Plan DeTransféré parPrasanna Bandaru
- lab7-8Transféré parBoon Kheng
- Introduction to FLIP FLOPSTransféré parOliver Barrina Jaguines
- QMUL.griffin.03232005 (1)Transféré parRahil Shah
- 04Transféré parmmlabjp
- Interfacing DevicesTransféré parProf. Yashavant p. Jadhav
- Multivibrator BonTransféré partchoudacy
- STA1Transféré parNayan Pastagiya
- Soc Seminar Ppt - CopyTransféré parLakshmisree Sajit
- 74HC4017Transféré parikatsiris
- ascasfsdfTransféré parSathees Mathi
- 41991872-VHDL-RecordTransféré parDivya Chanduri
- 6_1Transféré parsaikumarchintu

- Discrete MathematicsTransféré parPraneeth Akula Sona
- Flexlm_enduserTransféré parIram Chavira
- pytutTransféré parmaikkeli
- ZK 7.0.0 Style Customization GuideTransféré parfcosys
- Raisin in the SunTransféré parDwdaqa
- Indian National Anthem by DevegowdabhimanyuTransféré parDevegowdabhimanyu
- What is the meaning of 'al masjid al haram' according to The Quran?Transféré parTruthResearcher
- RDBMSTransféré parfcmitc
- Octave ReviewTransféré parbaruaeee
- Design of a Python-subset Compiler in Rust targeting ZPAQLTransféré paryo
- programming in c theory and lab syllabus 17gex03Transféré parapi-229849561
- IELTS General Training ReadingTransféré parAbdul Hameed
- Cambridge exams Preparation Materials listTransféré parsweetface_f2900
- Vocabulary & Grammar Test Unit 4 Test ATransféré parsara
- Cognitive LinguisticsTransféré parDoris Tănase
- Cross-language Effects in Bilingual Production and Comprehension Some Novel FindingsTransféré parPaula Manalo
- Chapter 1 - constructivist learning approach to ESPTransféré parchicanaliza
- Using Structured References With Excel TablesTransféré parintolscrib
- 101 Ways to Improve Your EnglishTransféré parsharu4291
- MacbethTransféré paruj1995
- Discourse analysisTransféré parOlga DabŠtrb
- Effective Classroom Learning -VocationalTransféré parobsrvr
- Francisco Aboitiz (Auth.)-A Brain for Speech_ a View From Evolutionary Neuroanatomy-Palgrave Macmillan UK (2017)Transféré parLeón Zamora Z
- Trabajo FinalTransféré parJorge Erasmo Alberto
- ABAP XML - Mapping SimplifiedTransféré parEmilS
- Debate Score SheetTransféré parCassandra Jane Ong
- Academic Writing StyleTransféré parclaudia1920
- Imperialism Primary Source Group ActivityTransféré parr
- Ilovepdf MergedTransféré parSantiago Escobar
- Lesson Plan Maria MakilingTransféré parFrancis Lloyd Beruan