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IR Drop Analysis ~ VLSI Basics And Interview Questions

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IR Drop Analysis
What i s I R Dr op Anal ysi s? How i t ef f ec t s t he t i mi ng?
The power supply in the chip is distributed uniformly through metal layers (Vdd and
Vss) across the design. These metal layers have finite amount of resistance. When
voltage is applied to this metal wires current start flowing through the metal layers
and some voltage is dropped due to that resistance of metal wires and current. This
Drop is called as IR Drop. For example, a design needs to operate at 2 volts and has
a tolerance of 0.4 volts on either side, we need to ensure that the voltage across its
power pin (Vdd) and ground pin (Vss) in that design does not fall short of 1.6
Volts.The acceptable IR drop in this context is 0.4 volts. That means the design in this
context can allow upto 0.4 volts drop which does not effect the timing and
functionality of design.
How i t ef f ec t s t he t i mi ng?
IR Drop is Signal Integrity(SI) effect caused by wire resistance and current drawn off

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IR Drop Analysis ~ VLSI Basics And Interview Questions
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from Power (Vdd) and Ground (Vss) grids. According to Ohms law, V = IR. If wire
resistance is too high or the current passing through the metal layers is larger than
the predicted, an unacceptable Voltage drop may occur. Due to this un acceptable
voltage drop, The power supply voltage decreases. That means the required power
across the design is not reaching to the cells. This results in increased noise
susceptibility and poor performance.
The design may have different types of gates with different voltage levels. As the
voltage at gates decreased due to unacceptable voltage drop in the supply voltage,
the gate delays are increased non-linearly. This may lead to setup time and hold time
violations depending on which path these gates are residing in the design. As
technology node shrinking, there is decrease in the geometries of the metal layers
and the resistance of this wires increased which lead to decrease in power supply
voltage. During Clock Tree Synthesis, the buffers and inverters are added along the
clock path to balance the skew. The voltage drop on the buffers and inverters of clock
path will cause the delay in arrival of clock signal, resulting hold violation.
What ar e t he t ool s used f or I R Dr op Anal ysi s? I n w hi c h st age I R Dr op
Anal ysi s per f or med ?
Various tools are available for IR Drop Analysis. Voltagestorm from Cadence,
Redhawk from Apache are mainly used to show IR Drop on chip. Here we are going
to discuss about IR Drop using Redhawk. IR Drop Analysis using Redhawk is
possible at different stages of the design flow. When changes are in expensive and
they don't effect project's schedule, It is better to use Redhawk for IR drop analysis
from start of the design cycle. It can identify and fix power grid problems in the
design. This also reduces changes required in sign-off stage where final static and
dynamic voltage (IR) drops performed. So Redhawk can be used anywhere in the
design starting from the floorplanning stage through initial and final cell placement
stages.

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