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Switching Theory And Logic Design Sobha Devi

IMPORTANT QUESTIONS
*** UNIT 1 ***
1. Types of number systems
2. Conversions
( )
2
(?)
8
( )
2
(?)
16
( )
8
(?)
16

( )
8
(?)
2
( )
16
(?)
2
( )
16
(?)
8

( )
2/8/16/5
(?)
10

( )
10
(?)
2/8/16/5

3. rs and r-1 s complement ( 1s and 2s complement forms)- PROBLEMS
4. Signed and unsigned magnitude number representation.
5. SUBTRACTION
1s complement and 2s complement subtraction
BCD subtraction using 9s & 10s complement
EXCESS 3 subtraction
- PROBLEMS

6. ADDITION
BCD addition
EXCESS 3 addition
- PROBLEMS

7. BCD , EXCESS 3 , 2421 , 8421 codes
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EXAMPLES:
1. Convert the following to Decimal and then to Octal.






(a) 1234
16
(d)10001111
2

(b) 12EF
16
(e) 352
10

(c) 10110011
2
(f) 999
10

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Switching Theory And Logic Design Sobha Devi
Refer material for problems
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*** UINT 2 ***
1. Boolean theorems
2. Logic gates AND , OR , NAND , NOR ,EX-OR , EX-NOR (logic symbol &
truth table)
3. What is SOP & Standard SOP(canonical form) ? (similarly POS & standard
POS)
4. Complement and dual of a give Boolean function - problems
5. Minimization of logical expression using Boolean theorems
6. Error detecting and error correcting codes PARITY (even parity and
odd parity) Hamming code - problems
7. AND-OR , OR AND , NAND-NAND, NOR-NOR realizations
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EXAMPLES:
1. Simplify the following Boolean functions to minimum number of literals:
i. ( a + b ) ( a + b )
ii. y(wz + wz) + xy
2. Prove that AND-OR network is equivalent to NAND-NAND network.
3. State Duality theorem. List Boolean laws and their Duals.
4. (a) Express the following functions in sum of minterms and product of maxterms.
i. F(A,B,C,D)=BD+D+BD
ii. F(x,y,z)=(xy+z)(xz+y)
(b) Obtain the complement of the following Boolean expressions. [8]
i. (AB+AC)(BC+BC)(ABC)
ii. ABC+ABC+ABC
iii. (ABC)(A+B+C)

5. Obtain the Dual of the following Boolean expressions.
i. AB+A(B+C)+B(B+D) ii. A+B+ABC
iii. AB+ABC+ABCD+ABCDE iv. ABEF+ABEF+ABEF
6. With the help of the generalized form of the Hamming code, explain how the number of
parity bits required to transmit a given number of data bits.
7. What is a parity bit? Define even and odd parity. What is the limitation of the parity code
when it comes to detection and correction of bit errors?


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Switching Theory And Logic Design Sobha Devi
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*** UNIT 3 ***
1. What is k - map? What is meant by pair, a quad, and an octet of a
map and how many variables are eliminate ? Name its advantages and
disadvantages
2. What is Quine McCluskey method? What are the advantages over k-
map?
3. PROBLEMS > 3 variable k-map, 4- variable k-map , 5- variable k-map,
6variable k-map

EXAMPLES:
1. a) Write a simplified max-term Boolean expression for F= m(0, 4, 5, 6, 7, 10, 14 ) using the
Karnaugh mapping method.
b) Minimize the following function using the Quine-McCluskey method.
Y = (1, 2, 5, 8, 9, 10, 12, 13, 16, 18, 24, 25, 26, 28, 29, 31)
2. (a) What are the advantages of Tabulation method over K-map?
(b) Simplify the following Boolean function using Tabulation method.
Y(A,B,C,D) = (2,3,5,7,8,10,12,13)
3. Simplify the following Boolean expressions using K-map and implement them using
NOR gates:
a) F (A, B, C, D) = ABC + AC + ACD
(b) F (W, X, Y, Z) = WXYZ + WXYZ + WXYZ + WXYZ.

*** UNIT 4 ***
1. Half Adder , Full Adder , Implementation of Full adder using 2 Full
Adders and 1 OR gate.
2. Half Subtractor , Full Subtractor , Implementation of Full Subtractor
using 2 Full Subtractors and 1 OR gate.
3. Full adder applications 4 bit adder ,4 bit subtractor
4. BCD adder
5. Look a head adder circuit
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Switching Theory And Logic Design Sobha Devi
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EXAMPLES:
1. Discuss the functional principle of 4-bit ripple carry adder what is its major disadvantages?
2. Draw the logic diagram of a three-digit Excess-3 adder and briefly describe its functional
principle?
3. Design a combinational logic circuit whose output is a 4-bit number and out put is
the 1s complement of the input number.
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** UINT 5 **
1. What is combinational logic circuit ?
2. Differentiate between combinational logic circuit and sequential circuit?
3. Decoders Definition , Truth Table , Logic symbol , Logic circuit
4. Encoders Definition , Truth Table , Logic symbol , Logic circuit
5. Multiplexer Definition , Truth Table , Logic symbol , Logic circuit
6. Demultiplexer Definition , Truth Table , Logic symbol , Logic circuit
7. PROBLEMS
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1. Implement the multiple output combinational logic circuit using a 4line to 16
line decoder.
f1 = m(1, 2, 4, 7, 8, 11, 12, 13, 14, 15)
f2 = m(0, 1, 3, 5, 8, 9, 15)
f3 = m(2, 3, 4, 7)
f4 = m(0, 1, 3, 4, 7, 9)
2. Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexer.
3. What is decoder? Construct 3*8 decoder using logic gates and truth table.
4. What is Encoder? Design Octal to Binary Encoder.
5. Draw the logic diagram of 2bit comparator?
6. Implement the give Boolean function using Decoder , Multiplexer and Demultiplexer.
f1 = m(1, 2,5, 7, 8, 11, 13, 14, 15)



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Switching Theory And Logic Design Sobha Devi
* UNIT 6
1. PROM, PLA, PAL implementation for the given Boolean function.
2. Comparison of PROM, PLA & PAL.
Examples:
1. Derive the PLA programming table for the combinational circuit that squares a 3
bit number.
2. For the given 3-input, 4-output truth table of a combinations circuit, tabulate the
PAL programming table for the circuit. [8+8]
Inputs

Output

x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

3. (a) Implement the following boolean functions using PLA.
f1(w,x,y,z) = P(0,1,3,5,9,13)
f2 (w,x,y,z) = P(0,2,4,5,7,9,11,15). [16]
(b) Write short notes on PLDS .
4. (a) The following memory units are specified by the no of words times the number
of bits per word. How many address lines and input-output data lines are
needed in each case?
i. 4K 16
ii. 2G 8
iii. 16M 32
iv. 256K 64.
(b) Give the number of bytes stored in the memories listed above.



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Switching Theory And Logic Design Sobha Devi
UINT 7
1. What is sequential circuit?
2. Differentiate between latch and flip flop.
3. Differentiate synchronous and asynchronous sequential circuit.
4. Flip flops SR , D , JK ,T
5. Conversions of one flip flop to another flip flops
6. Design of asynchronous counters
7. Design of synchronous counters
8. Ring counter and Johnson counters
9. What is registers and their types and design patterns.
10. What is race around condition. How can we overcome this problem
(using Mater Slave flipflop)

EXAMPLES:
1. Compare synchronous & Asynchronous circuits
2. Design a Mod-6 synchronous counter using J-K flip flops.

3. Explain the following
i. Race-around condition in flip flop
ii. J-K Master slave flip flop
iii. Excitation table for flip flops
4. Design a synchronous counter that counts as 000, 010, 101, 110, 000, 010 Ensure that the un
used states of 001, 011, 100 and 111 go to 000 on the next clock pulse. Use J-K flip-flops.