High-to-Low Propagation Delay tPHL

VIN switches instantly from low to high. Driver transistor (n-channel)

immediately switches from cutoff to saturation; the p-channel pull-up switches
from triode to cutoff.

Circuit during high-to-low transition:

(p-channel MOSFET is cutoff)
IDn
vOUT (t)
+
CL = CG + CP

VIN (t > 0) = VOH

_

The voltage on the load capacitor at t = 0- was VOH; since n-channel MOSFET is
saturated initially and the input voltage is a constant, the drain current is initially
IDn(sat) for VGS = V+.
The high-to-low propagation delay tPHL is (by denition) the time required for
VOUT to reach VOH / 2:
I Dn ( sat )
dv OUT
d QL
----------------- = ----- --------------------- = ----------------------dt C G + C P
dt
CG + C P

EE 105 Spring 1997

Lecture 16

Hand Calculation of tPHL

The output voltage decreases linearly over 0 < t < tPHL if we assume that the
MOSFET remains saturated:
vOUT (t)

VOH
slope = dvOUT / dt
VOH / 2

tPHL

The high-to-low propagation delay is given by:

dv OUT
( V OH 2 ) V OH
I Dn ( sat )
----------------- = ----------------------------------------- = ----------------------dt
t PHL
CG + C P
Solving for the delay:
( C G + C P ) ( V OH 2 )
t PHL = ---------------------------------------------------------------------------2
n C ox ( W 2L ) n ( V OH V Tn )

EE 105 Spring 1997

Lecture 16

Graphical Interpretation

The n-channel driver remains saturated throughout the rst half of the transition
from high-to-low...
ID

VOUT
t = 0+
VIN = VOH

t = tPHL

VOH
t = 0
VIN = 0V

VOH
2

0
0

VOH
2

VOH
(a)

VOUT

0
0

tPHL
(b)

note that the characteristics above are not for a square-law MOSFET, which
would enter the triode region for VOUT < VOH - VTn; the error is not large enough
to matter for hand calculations in any case

EE 105 Spring 1997

Lecture 16

Low-to-High Propagation Delay tPLH

For the low-to-high transition, the n-channel device is cutoff and the p-channel
MOSFET is initially saturated and supplying - IDp(sat) to charge up the gate and
parasitic capacitances.
VDD
VSGp +
_

VIN = 0 V

- IDp

Therefore,
( C G + C P ) ( V OH 2 )
t PLH = ----------------------------------------------------------------------------2
p C ox ( W 2L ) p ( V OH + V Tp )

In order to have identical propagation delays, the width-to-length ratio of the pchannel pull-up must be twice that of the n-channel driver, in order to compensate
for the lower hole mobility in the channel.

EE 105 Spring 1997

Lecture 16

Power Dissipation

Energy from power supply needed to charge up the capacitor:

E charge =

+ 2

V i(t)dt = V Q = ( V ) ( C G + C P )

Energy stored in the capacitor:

+ 2
1
E store = --- ( C G + C P ) ( V )
2

Energy lost in p-channel MOSFET during charging:

+ 2
1
E diss = E charge + E store = --- ( C G + C P ) ( V )
2

During discharge, the n-channel MOSFET driver dissipates an identical amount

of energy. If the charge/discharge cycle is repeated f times/second, where f is the
clock frequency, the dynamic power dissipation is:

+ 2

P = ( 2E diss ) f = ( C G + C P ) ( V ) f
In practice, many gates dont change state every clock cycle, which lowers the
power dissipation

Additional source of dissipation: power ow from V+ to ground when both

transistors are saturated. Can be significant, but hard to estimate by hand.
Typical number: 25% of dynamic power dissipation.

EE 105 Spring 1997

Lecture 16

Power (cont.)

Practical numbers: CL = 50 fF, f = 200 MHz, V+ = 3 V, Ngates = 5 x 105

P = 45 W ! (note that the real average depends on the average number switching
per clock cycle)

Comparing Technologies -- the power-delay product

* Logic families are often compared by considering the product of the dynamic
power dissipation and the propagation delay:

+ 2 ( C L + C p ) ( V 2 )
PDP = Pt P ( C L + C p ) ( V ) f ---------------------------------------------

1--- k ( V + V ) 2
Tn
2 N

where V+ has been substituted for VOH to achieve a more universal result.
* For V+ >> VTn,

2 +

(CL + C p) V f
PDP --------------------------------------kN

EE 105 Spring 1997

Lecture 16

CMOS Static Logic Gates

Static -- logic levels remain valid so long as power is supplied

NOR and NAND gates

VDD

M4
A
M3

+
M2 VOUT
_

M1 B

(a)
VDD

M3

M4

A
B

+
B

M2

VOUT
_

M1

(b)

EE 105 Spring 1997

Lecture 16

CMOS NAND Gate

Qualitative description
Find transfer curve for case where VA = VB and both transition from 0 to 5 V

Transistors M1 and M2 are in series and have the same current; however, they do
not have the same gate-source bias

VDD

VM

M3

M4

ID
VM

VM

VGS1 = VM

M2
+
M1 VDS1

VGS2 = VM VDS1

ID1 = ID2

VDS
(a)

(b)

EE 105 Spring 1997

Lecture 16

MOSFETs in Series

Transistors M1 and M2 are in series with the same gate voltage, for the case
where the inputs are tied together (A = B)
VOUT

M1

VA = VB

M2

ground

drain current is the same through each device ... what is the effective value of kP?

EE 105 Spring 1997

Lecture 16

MOSFETs in Series (Cont.)

At VA = VB = VM, the cross section through M1 - M2 is:





,,
,,



VM

,,
,,

source

VM

gate

gate

M1

M2

n+

L1

L2

(a)

,,
,,

drain

VM

,,

source

VM

gate

gate

M1

M2

L1

L2

,,
drain

(b)

Transistor M1 is in triode and M2 is saturated. From the cross section, the drain
of M1/ source of M2 can be eliminated without affecting anything --> the two
MOSFETs can be merged into a composite transistor with L1 + L2 = 2 Ln

Solving for VM for the case where VA = VB (note that the two p-channel devices
are in parallel and have an effective width of W3 + W4 = 2 Wp
2k p
kp
V Tn + 2 ----- ( V DD + V Tp )
V Tn + ------------ ( V DD + V Tp )
kn 2
kn
V M = ------------------------------------------------------------------ = --------------------------------------------------------------2k p
kp
1 + -----------1 + 2 ----kn 2
kn

where kn = nCox (Wn/Ln) and kp = pCox (Wp/Lp)

We could optimize VM = VDD/2, but there is another switching condition to consider

EE 105 Spring 1997

Lecture 16