I2c Protocol

J.N.L.Shashank
Granite River Labs
What is i2c?
I2c means Inter Integrated Circuit, also
known as I-square C or IIC
It is a bi-directional open-drain data
transfer protocol
Developed by Philips i.e., now NXP Semi
Conductors
Shown existence since the mid 1990s.
Texas Instruments, Freescale, ST Micro
electronics etc.. also implemented this
Why i2c?
I2c protocol is basically used to interface
low speed peripherals that can work on a
serial interface.
Easy to interface compared to other serial
communications like SPI, UART.
Multi-master and multi-slave concepts.

Transfer Rates
Low Speed: 10 kbpS
Standard Speed: 100 kbpS
Fast Speed: 400 kbpS
Fast Speed+ :1 MbpS
High Speed: 3.4 MbpS
The signals and Bus Nodes
SDA: Used to transmit and receive data.
SCL: Used for clock synchronization.

Master Node: Generates clock and
performs communications. Controls
slaves.
Slave Node: Responds to the
communication by master receiving clock
from master
Address
Can be 7 bit or 10 Bit address Space.
Limits the total number of slaves that can
be connected to a master based on the
address.
Also implements 16 bit address space in
the high speed data transfer applications.
Master
Controls the slaves and their address
space.
Generates Clock
Performs the data transfer initiation
Multi slave connection.
Bus Arbitration
MASTER RECEIVE
MASTER TRANSMIT


Slave
Receives clock
Responds to master message
May/ may not send ACK
SLAVE RECEIVE
SLAVE TRANSMIT

The Protocol
Contains Start bit (1 bit), the address (7/10
bits), the data (8/16 bit) and the stop bit
(1 Bit) (SDA).
May / May not contain acknowledge.
Clock is on a separate channel (SCL).
Acknowledge is done after every 8 data
bits.
Edge trigger signalling.
Start bit
The start bit is indicated by a high-to-low
transition of SDA with SCL high.
Stop bit
The stop bit is indicated by a low-to-high
transition of SDA with SCL high
Clock
Data
Acknowledge (ACK)
ACK bit is optional.
It can also be implemented as NACK
(Negative Acknowledge)
If the slave exists on the bus then it will
respond with an ACK bit (active low for
acknowledged) for that address.
PHY layer
Open-drain connections.
Pull down implements logic 0.
Floating output implements logic 1.
+5V or +3.3 Volts
Clock minimum wait time to get response
is 4S
Bus Arbitration
Used when multiple slaves are connected
Priority slave select.
Prevents from obtaining data from wrong/
unaddressed slave.
Also exists on multi master mode.
Clock Stretching
Used to synchronize the clock between
master and slave.
Used when the master / slave is still busy
processing previous request.
SCL is held low until processing is over.
Master also can drive the SCL low.
Data is transferred after making SCL high.
Timing Diagram
Other Implementations
SMBus architecture. System Management
PMBus architecture. Power Management