41

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 1, JANUARYIFEBRUARY 1989

ESD Protection: Design and Layout Issues for
VLSI Circuits
Abstract-The electrostatic-discharge design issues for input, output,
and power bus protection of metal-oxide semiconductor very-large-scale
integration devices are reviewed. For input pins, the critical layout
techniques that determine primary and secondary protection circuits are
reported; for output pins, the effective use of the output buffer itself as a
protection circuit is discussed. Finally, some of the recent advanced
process features for enhancement of very-large-scale integration circuit
reliability are presented, as well as their impact on the protection circuit
design and layout.
I . INTRODUCTION
HE sensitivity of metal-oxide semiconductor (MOS)
T integrated circuits to electrostatic discharge phenomena
has assumed a more critical role in recent years. In the past,
simple protection circuits involving diffused areas as diodes
have been effective at the input pins of integrated circuit
devices. However, in the evolution of higher-density and
faster-speed memory chips, the requirements for the electro-
static discharge (ESD) protection circuits have become more
stringent. This is coupled by the fact that with increased
awareness of ESD damage and yield loss in microelectronic
circuits, higher protection levels are in demand. Furthermore,
ESD protection requirements have increased from human
body stress to other types of stress, such as machine model
stress and charge device stress. In this paper the newer
protection-circuit design issues and considerations for n-
channel metal-oxide semiconductor (NMOS) and complemen-
tary MOS (CMOS) process technologies will be discussed.
The rapid advances in process technologies leading to
critical requirements for the protection circuits include thinner
gate oxides, shallower junctions, lightly doped drain (LDD) or
graded drain junctions, clad diffusions with silicides, and
multilayer metal systems. The influence of very-large-scale
integration (VLSI) scaling, as well as enhanced process
features on ESD, has placed a need to understand and design
more effective protection networks. Since no significant
modeling programs are available to attain this, the protection
circuit design can be performed only by empirical studies of
test structures which comprehend the design parameters and
failure analysis to improve the layout. With these two
Paper IUSD 87-97, approved by the Electrostatic Processes Committee of
the IEEE Industry Applications Society for presentation at the 1987 Industry
Applications Society Annual Meeting, Atlanta, GA, October 19-23. Manu-
script released for publication May 31, 1988.
C. Duvvury is with the VLSI Design Laboratory, Texas Instruments
Incorporated, MS 369, P.O. Box 655621, Dallas, TX 75265.
R. N. Rountree is with Texas Instruments Incorporated, MS 657, P.O. Box
1443, Houston, TX 77001.
R. A. McPhee is with the Electronics Imaging Systems Group, DuPont
Electronics Corporation, Philadelphia, PA 19061.
IEEE Log Number 8823811.
approaches good protection circuits can be achieved for both
inputs and outputs.
In Section 11the protection design for inputs will be
discussed. This will include considerations for both primary
protection design and secondary protection design, the latter of
which is essential in preventing the gate oxide rupture in
internal circuitry. The design techniques for output protection
using output buffers will be considered in Section I11 for
NMOS as well as for CMOS. The protection between the
power bus lines in semiconductor chips is often overlooked.
The input protection design is also influenced by the use of a
multibus system fer power lines. These considerations will be
discussed in Section IV. Finally, highly advanced process
features for 1-pm CMOS technology have a strong impact on
the ESD protection network performance, design, and layout.
In Section V these issues will beexamined.
11.INPUT PROTECTION
For inputs, diffusion diodes have conventionally served as
effective protection circuits. With positive ESD stress pulses
an input n+ diode will offer protection with breakdown into
the avalanche region; for negative stress it will operate as a
forward-biased diode. To obtain the maximumperformance of
the diode it must be laid out in an optimal manner that will
maintain a uniform avalanche conduction along its perimeter.
Therefore alternate approaches that occupy minimal area on
the chip are more desirable.
The main protection circuit for the inputs must not only be
small in area but also must turn on quickly to conduct a large
amount of current in a very short duration of time. For this to
function optimally it is often necessary to have a secondary
protection network whose main purpose is to protect the first
gate oxide in the internal circuitry. In this section the layout
and design of both primary and secondary protection networks
for inputs will be discussed.
A. Primary Protection
In recent years a thick-oxide or field-oxide device with
grounded source diffusion has been found to offer a high level
of input protection [1]-[3]. A typical layout of this device,
along with the critical design parameters, is shown in Fig. 1.
Basically the effectiveness of this device for positive stress is
derived by the operation of the parasitic bipolar n-p-n (formed
with the drain as the n-type collector, the substrate as the base,
and the source as the n-type emitter) in the second breakdown
mode. Previous work [3] has shown that for positive stress
pulses this device turns on at around 35 V, followed rapidly by
the operation of the lateral n-p-n. With negative-polarity stress
OO93-9994/89/0100-01$01 .OO O 1989 IEEE
42
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 1, JANUARYIFEBRUARY 1989
DRAIN
CHANNEL
SOURCE
v s s BUS
L A -
Fig. 1. Layout of thick-oxide device with critical design parameters.
~ P-TYPE SUBSTRATE
Fig. 2. Cross section of thick-oxide device.
pulses the device would operate as an area-dependent diode
and thus offer substantially good protection.
To obtain the maximum performance of this device as a
primary protection circuit, the layout is very crucial. A cross
section of the thick-oxide device in Fig. 1 is shown in Fig. 2.
Since for reverse-bias the maximum J. E product will occur at
the cylindrical junction, the generated heat could spread to the
contact and cause melting of the contact metalization. There-
fore the contact-to-drain-edge spacing, indicated as B in
Fig. 1 and as drain spacing in Fig. 2, is critical for the ESD
performance and should be kept sufficiently large (typically 6-
8 pm) [4]. Referring to Fig. 1, another critical design
parameter is the device width denoted as A. This parameter
should also be maximized since increasing it would reduce the
local heat generation and improve the failure threshold. Note
that the actual value of A is defined from one end contact to
another since this is the effective region for current distribu-
tion. Although it is desirable to have the maximum width, the
available area near the bond pad of the chip, or the tolerable
capacitance at the input pin limit, is typically to about 150 pm.
With these dimensions, for thick-oxide devices built with an
abrupt junction process, >6 kV of protection can be obtained
when tested with the human body model (HBM) stress
according to the military standard. The circuit schematic for
this test is shown in Fig. 3.
Other than the two critical parameters discussed in the
preceding, parameter C is also indicated in Fig. 1. Since it
is the lateral n-p-n that is critical to the operation under ESD
stress, the channel length C would not be very critical, but
should be kept about the minimum for the process technology.
I This model of stress is defined as charging up a 100-PF capacitor and
discharging it onto the pin under stress through a 1.5-kQ resistor.
10 M i l 1.5 k 0
REGULATED
HV SUPPLY
Fig. 3. Schematic diagramof human body model.
THICK D E F J OXIDE DIFFUSION RES;jTOR FIELD & PLATE
TO INTERNAL CIRCUIT
Fig. 4. Circuit schematic of secondary protection circuit.
With minimum channel length the threshold for bipolar
conduction would be lower, thus ensuring a quick turn-on.
The drain contact overlap away from the source side has not
been found to have any impact on the ESD performance of the
device, but could be designed to bethe same as B. Finally, for
optimum performance of the thick-oxide device the diffusion
areas should not have sharp edges and should be contacted
with uniformly spaced contacts. A good review of the thick-
oxide layout techniques are given in [ 5] .
B. Secondary Protection
As discussed in the previous section, an effective design for
the primary protection device is crucial in obtaining high-
performance levels of 6 kV or greater. However, the
secondary protection scheme is very critical to the successful
operation of the overall input protection. This is because the
secondary protection network can potentially prevent the
internal gate-oxide rupture during the initial stages of the ESD
pulse, before the primary protection network turns on. The
circuit schematic of the overall input protection circuit is
shown in Fig. 4. The secondary protection consists of a
diffusion resistor and a field plate diode, which are in parallel
with the thick-oxide device. With the application of a positive
pulse, the lateral n-p-n action begins first at the field plate
diode due to its rapid response time; the voltage to the internal
circuitry will be clamped to below that of the gate oxide
breakdown. Once this occurs, a large amount of current flows
through the diffusion resistor, causing a voltage drop across its
length. This will subsequently result in a voltage buildup at the
drain of the thick-oxide device, eventually causing it to go into
a snapback mode of conduction also. The larger thick-oxide
device will then discharge the majority of the transient pulse to
ground.
Since the purpose of the diffusion resistor is to limit the
current to the field plate diode, it is often selected to be about
100 Q. The width of this resistor is critical, since a very
narrow diffusion (< 2 pm) could be damaged due to avalanche
heating. However, this is balanced by the available area and
the number of squares required to obtain the desired resistor
value. The field plate device design is as important as the
thick-oxide device, since this is the device that will receive the
first portion of the stress pulse. The channel length should be
DUVVURY et al. : ESD PROTECTION
43
TU CIRCUIT
THICK
OXIDE
DEVICE FP ni na
VSS
Fig. 5. Layout of overall input protection
H16H VOLTAGE
R L A V
I
Fig. 6. Schematic diagramof machine model stress.
POLYSKICON MELT FKAMENT
DRAI N [ 1 - 1 SOURCE
POL Y GA T E
L M E T A L MELT FILAMENT
P- TYPE SUB STRA TE
Fig. 7. Failure modes for NMOS devices.
kept close to the minimum of the process technology to
achieve the fastest transit times from drain to source. The
device width should be large enough to handle the initial
current, with width-to-length ratios of >10. A typical
isolation stage design can protect up to 2 kV before allowing
the primary protection to turn on. An example of effective
layout for the overall input protection is shown in Fig. 5.
Most of the preceding protection design considerations deal
with human body model stress. Recently there has been an
increasing interest in stress testing VLSI devices to the so-
called machine model2 stress as well. The circuit schematic for
this model is shown in Fig. 6. As can be seen, this
incorporates a high-voltage high-current stress, where the
current is essentially determined by the dynamic impedance of
the protection circuit due to the absence of any limiting
resistance. Therefore the protection levels for this model
approximately translate down one order of magnitude from the
human body model. For improved performance with the
This type of stress is defined as charging up a 200-PF capacitor and
discharging it directly onto the pin under stress.
machine model, an on-chip series resistor, placed between the
pad and the protection circuit, can also beused. However, this
resistor should not be too large, since the pad voltage buildup
could cause a dielectric rupture of the pad oxide during the
HBM testing.
III. OUTPUT PROTECTION
In a VLSI chip, the large output buffer device itself can be
used to obtain good ESD protection. As mentioned in Section
11,the heat generated at the reverse-biased junction during the
ESD pulse can cause damage. This is especially crucial for the
thin-oxide output device. Consider Fig. 7, where the thin-
oxide cross section is shown. The generated heat could either
cause a metal melt filament from source to drain by elevating
the temperature near the contact metalization, or result in a
polysilicon melt filaments by spreading to the gate situated
directly above the thin oxide. To minimize this and improve
the failure threshold, the diffusion contacts for both drain and
source must be kept far (> 5 pm) from the polysilicon gate [4].
This critical design parameter and the output layout to achieve
44
n n n
8 8 8
8 0
8 0 k f
8 8 8
8 8 8
8 8 8
8 8
8 8
8 m
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. I , JANUARYfFEBRUARY 1989
8
8
8
8
8
8
A 8
8
8
8
Fig. 8. Layout of output device with critical design parameters.
8
8 8 8
8 8
N-CHANNEL P-CHANNEL
ss
DD
P-EPI
P+-SUBSTRATE
Fig. 9. Cross section of CMOS output buffer.
uniform current density are shown in Fig. 8. As is obvious,
increasing the device width for maximum performance is
necessary, but this is dictated by the particular circuit design
considerations.
Similar to the thick-oxide input device, the n-channel output
device offers protection for positive stress by operating as a
parasitic bipolar n-p-n in the second breakdown mode, and for
negative stress as a forward-biased diode. Therefore, for
NMOS output buffers, good ESD protection is inherently
designable. Since CMOS is rapidly becoming popular for
memory circuits, CMOS output buffers are naturally an
attractive option due to their speed performance. The ESD
design of this type of buffer therefore must also be considered.
The output protection for CMOS buffers, shown in Fig. 9,
will be more straightforward since the p-channel device would
provide protection as a forward-biased diode for positive
stress, and likewise the n-channel for negative stress. How-
ever, this may not necessarily be the case due to the nature of
process, which does not allow for a low diode impedance path
to ground for p-channel devices [6]. For example, this is
commonly the case for CMOS processes with the p-channel
devices in an n-well, as shown in Fig. 9. This means that for
positive stress the reverse bias stress will still be on the n-
channel device. Therefore the pull-down n-channel device
must still be carefully designed, as described in the preceding,
to obtain good protection. On the other hand, for negative
polarity stress, the p-channel device does not tend to go into
second breakdown and hence cannot be depended upon to
provide the necessary protection [7]. This would also lead to
the pull-down n-channel device for protection with negative
stress. It must be noted here that the p-channel device does
play some role in taking a portion of the stress current away
from the n-channel device, and that, in general, for the abrupt
Fig. 10. Equivalent component schematic of input protection.
Fig. 11. Damage site observed for Voo-Vss stress.
junction process the positive stress performance of CMOS
output buffers is better than for NMOS buffers. This becomes
more complicated for advanced processes, as will be pointed
out in Section V.
IV. POWER Bus PROTECTION
The military-standard testing method requires stressing
between all inputs, outputs, and power pins with respect to the
ground pin or Vss pin. When stressing between VDD (or Vcc)
and Vss pins, the stressing current could turn on many
parasitic devices internal to the chip. As shown in Fig. 10,
consider the equivalent component schematic of the input
protection network of Fig. 3. Here Ru and Rc represent the
parasitic resistance and capacitance between VDD and Vss.
Usually these are large, and good protection is built into the
chip for VDD-to-Vss stress. But at a certain level of stress some
failures are likely to be induced in the internal locations. For
example, if in the internal layout the VDD diffusion to Vss
diffusion is very close, this could act as a parasitic thick-oxide
device. Since this is not an intended protection circuit, it could
easily be damaged for a lower stress voltage. An illustration of
one such damage is shown in Fig. 11. Even if a large thick-
oxide device is placed between VDD and Vss, the failure site
will still most likely be at the weak parasitic devices. To
overcome this, the minimum VDD diffusion to Vss diffusion
spacing in the internal layout of the chip must be kept larger
than that of the thick-oxide protection device. Referring back
to Fig. 10, it is also interesting to note that when the input is
stressed with respect to VDD, the stress current would
eventually flow between Vss and VDD. Therefore careful
internal layout would also provide good protection for this
type of stress. Similarly, when a CMOS output buffer is
stressed with respect to VDD, damage could occur in the
internal parasitic devices. The current path for this is shown in
Fig. 12, where both VDD and Vss diffusions are shown.
Therefore a careful consideration is also required in this case.
In general, VDD-to-Vss stress current paths are very complex
and require thorough analysis to determine if the chip is fully
DUVVURY et al.: ESD PROTECTION
45
VDD (COMMON) VSS (OPEN)
N-CHAN DEVICE
P- CHI N
J+ ,~ I p & L & F + T O DEVICE
Nt
6
VDD DIFFUSION VSS DIFFUSION
P- TYPE EPITAXIAL LAVER
Pt TYPE SUBSTRATE
Fig. 12. Current through output device during positive ESD stress to VDD.
INPUT CIRCUIT 1/0 CIRCUIT V / V NETWORK
plate (FP) diode.
DD ss
Fig. 13. Overall CMOS protection scheme of typical CMOS circuit, showing basic circuit elements such as thick field (TF) and field
functional after the power bus stress. The overall CMOS
protection scheme is shown in Fig. 13. Note the complicated
current paths due to the parasitic elements between VDD and
Vss. The layout must comprehend these to obtain good ESD
protection for stress between different pin combinations, as
discussed earlier.
Large microcomputer chips tend to use multi-Vss and multi-
VDD power bus systems in order to reduce local noise levels in
the circuits. In such cases the protection circuit performance
may depend upon the Vss pin to which it is tied and the Vss pin
to which it is stressed. If the input pin is tied to Vssl and the
stress is with respect to Vssz, the performance will be
determined by how hard the Vssl is held at the substrate
potential. This is because if a resistive path exists between Vssl
and Vss2, the local substrate potential at the pin could become
slightly negative due to the voltage drop between VSs2 and
Vssl, and hence cause a relatively higher stress at the input
pin. Therefore careful layout of all ground networks with
regard to ESD protection circuits is also necessary.
V . ADVANCED PROCESS CONSIDERATIONS
To increase the speed and reliability of VLSI circuits,
advanced process features such as LDD and silicided diffu-
sions are becoming popular. These features are compared in
the cross sections shown in Fig. 14. For the LDD structures the
grading of source/drain is achieved by either single or double
species of implants. This would reduce the peak electric fields
near the drain regions of the transistors and make themless
susceptible to hot-electron reliability problems. The silicida-
tion of the diffused regions, as shown in Fig. 14, reduces the
sheet resistivity and increases the circuit speed. However,
these two novel features, especially the latter, have recently
been found to have a large negative impact on the ESD
performance of protection circuits [8], [9]. The implication of
this on the protection circuit design and layout are considered
in this section.
The failure threshold voltages versus device width for thick-
oxide input devices are shown in Fig. 15 for different process
options. These results are for positive stress, according to the
HBM method. Note that while for abrupt junction process the
failure threshold can be improved with increasing device
width, this is somewhat limited for the LDD process and is
futile with the silicided diffusion process. With the silicide
process, not only does increasing the device width have very
little or no impact, increasing the drain spacing (see Fig. 1)
does not help either. This is because with the silicided
diffusions, as shown in Fig. 14, the drain spacing is essentially
reduced to zero, and hence the drastic reduction in the failure
thresholds.
As a result, the alternatives for improving the failure
thresholds are either to investigate other design parameters,
block the silicidation at the protection circuits, or invent newer
protection schemes. Recent work [lo] has shown that by
varying the channel length of silicided thick-oxide devices,
optimumperformance can possibly be realized. Since such
an improvement may not be significant, a better approach is to
block the silicide formation and optimize the sourceldrain
IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 25, NO. 1, J ANUARYIFEBRUARY 1989
46
DRAIN CONTACT ABRUPT SOURCE CONTACT
I N+ DRAIN {N+ SOURCE I
DOUBLE
DiFFUSED LDD
DRAIN CONTACT LDD/SILICIDE SOURCE CONTACT
SINGLE
DIFFUSED LDD
Fig. 14. Cross section of NMOS transistor for conventional and advanced process options
0 0 Bo 100 160
DEVICE WIDTH I d)
Fig. 15. Failure threshold voltage versus device width for thick-oxide input
devices.
process, as reported in [8]. In most circuits the LDD process is
now very common. For these, good ESD performance can be
obtained from the thick-oxide devices by making them
sufficiently large in size. However, the impact of LDD on the
secondary protection must not be overlooked. The LDD
process will degrade theESD performance of the field plate
diode of Fig. 4 and cause the damage to be shifted to this
device. This requires a careful balancing of the resistor and the
field plate diode size in Fig. 5. Also, with LDD process the
diffusion junctions are shallower and require the diffusion
resistor to bewider. All of these considerations are necesary to
obtain the maximumperformance from the thick-oxide protec-
tion scheme.
Similar to the input protection, the output protection has
also been found to degrade in ESD performance with the use
of advanced process features. Again, with the silicided
diffusions the performance is at its worst. Even with the use of
CMOS output buffers the stress still occurs in the silicided n-
channel devices for positive pulses and easily causes damage
to the silicide. With an understanding of the ESD phenomena,
good ESD protection can be obtained for CMOS buffers with
advanced process options, as reported in [6]. This would
require lowering thep-channel diode impedance to the guard
ring and thus relieve the stress on the n-channel device. In
summary, whether it is the LDD or silicided process, good
output ESD protection can be obtained, provided that an
effective ladder structure, as shown in Fig. 8, is utilized.
VI. CONCLUSION
The ESD protection design and layout techniques were
reviewed in this paper for both inputs and outputs. The input
protection requires consideration for primary and secondary
protection circuit design. An effective primary circuit to
rapidly discharge large amounts of stress current is a thick-
oxide device with optimized layout. This device with a
grounded source diffusion can provide up to 6 kV of ESD
protection for the human body stress model. The secondary
protection involves a diffusion resistor and a field plate diode
to discharge theinitial transient pulse and protect the internal
gate oxide.
For outputs, the output buffer can be designed to offer good
ESD protection. The effective layout involves a ladder-type
structure to achieve uniform current density, and maximum
contact-to-gate spacing to improve the failure threshold
before the eventual thermal failures. In the case of CMOS
output buffers, higher-level ESD protection can be achieved as
long as the pull-down n-channel device is effectively designed.
Power bus protection between VDDand Vss is also important
for VLSI circuits. Since the ESD stress could potentially cause
damage in the internal circuitry, a protection circuit must also
be employed between VDD and Vss. The layout of the chip
must be designed with the consideration that weak parasitic
devices in the internal circuitry make the VDD-VSS protection
DUVVURY et al. : ESD PROTECTION 47
circuit ineffective. In addition, good VDD-VSS protection also
ensures good protection between the input-output (UO) pin
and DD. For large microcomputer chips with power
bus systems, careful layout of all ground networks with regard
to ESD performance must be considered.
[9] C. ~uvvury, R. A. McPhee, D. A. Baglee, and R. N. Rountree, ESD
protection reliability in I-pm CMOS technologies, in Proc. 24th
Ann. Reliability Phys., Apr. 1986, pp. 199-205.
0. Wilson, H. Domingos, and M. Hassan, Electrical overstress in
NMOS silicided devices, in EOS/ESD Symp. Proc., vol. EOS-9,
Sept. 1987, pp. 265-273.
[lo]
Advanced process features, such as LDD junctions and
silicided diffusions, have a strong negative impact on ESD
protection circuits, and hence they need to be modified to
partially overcome this. The design modifications must con-
sider both the primary and secondary protection circuits of the
inputs. Since CMOS technology is accompanied by advanced
process features, the output protection design can take
advantage of this to achieve good ESD performance. This calls
for an effective layout of the p-channel device to lower its
base-emitter diode impedance.
Finally, sufficiently high ESD protection levels can be built dynamic random-access
Charvaka Duvvury (S67-M68-M81) received
the B.S.E.E. degree from the University of Hous-
ton, Houston, TX, and the M.S.E.E. and Ph.D.
degrees (materials science) from the University of
Toledo, Toledo, OH.
From 1972 to 1977 he worked as a postdoctoral
Fellow in the physics department of the University
of Alberta, Edmonton, AB, Canada. He joined
Texas Instruments (TI) Incorporated at Houston in
1977 as an MOS Design Engineer, where he was
involved in various design and reliability issues of
memories and the reliability issues of the Roadrunner
into VLSI chips, provided effective design and layout employ
&crocomputer chips. Currently he is a member of the Technical Staff in the
results from empirircal studies, extensive stress testing of all
vLsl Design Laboratory Of
working On ESD and
transistor modeling. He has published over 20 papers in technical journals,
which include topics of transistor modeling, ESD, and hot-electron effects.
Dr. Duvvury is a member of the IEEE, Sigma XI, Eta Kappa Nu. and the
pin combinations, and routine failure analysis. This type of
approach must be repeated for each new generation of process
technology or circuit architecture to ensure continued ESD
protection.
Association.
REFERENCES
J . K. Keller, Protection of MOS integrated circuits from destruction
by electrostatic discharge, in Proc. EOS/ESD Symp., vol. EOS-3,
Sept. 1981, pp. 73-79.
T. V. Hulett, On chip protection of NMOS devices, in Proc. EOS/
ESD Symp., vol. EOS-3, Sept. 1981, pp. 90-96.
C. Duvvury, R. N. Rountree, and L. S. White, A summary of most
effective electrostatic protection circuits for MOS memories and their
observed failure modes, in Proc. EOS/ESD Symp., vol. EOS-5,
Sept. 1983, pp. 181-184.
R. N. Rountree and C. L. Hutchins, NMOS protection circuitry,
IEEE Trans. Electron Devices, vol. ED-32, no. 5, pp. 910-917, May
1985.
A. Palella and H. Domingos, A design methodology for ESD
protection networks, in EOSIESD Symp. Proc., vol. EOS-7, Sept.
C. Duvvury, R. N. Rountree, Y. Fong, and R. A. McPhee, ESD
phenomena and protection issues in CMOS output buffers, in Proc.
25th Ann. Reliability Phys., Apr. 1987.
N. Khurana, T. Maloney, and W. Yeh, ESD on CHMOS devices-
Equivalent circuits, physical models and failure mechanisms, in Proc.
23rd Ann. Reliability Phys., Mar. 1985, pp. 212-223.
R. A. Mcphee, C. Duvvury, R. N. Rountree, and H. Domingos,
Thick oxide device ESD performance under process variations, in
Proc. EOS/ESD Symp., vol. EOS-8, Sept. 1986, p. 173.
1985, pp. 169-174.
Association, with acti\
Robert Rountree (M87) received the B.S.E.E.
degree from the University of Houston in 1976.
He was employed at Texas Instruments (TI) as a
MOS Design Engineer until 1977, when he entered
active duty in the U.S. Army. He rejoined TI in
1982 as an MOS Design Engineer in advanced
development in Houston, TX. He is currently a
senior member of the technical staff, working on
various aspects of reliability and design of 1-4 Mbit
dynamic random-access memories.
Mr. Rountree is a member of the EOS/ESD
re participation in the Technical Program Committee.
Robert McPhee (S82-M85) received the B.S.
and M.S. degrees in electrical engineering from
Clarkson University in 1Y84 and 1986, respec-
tively.
In May of 1985 he joined Texas Instruments in
Houston, TX, as an MOS Design Engineer, work-
ing on the reliability aspects of advanced memories.
At present he is employed by DuPont Electronics in
Philadelphia, PA, working with the Electronics
Imaging Systems Group.