Small Signal Modeling of a Novel Single-Phase

Photovoltaic Inverter

Pan Geng, Weimin Wu, Yinzhong Ye, and Yijian Liu
Department of Electrical Engineering, Shanghai Maritime University, Shanghai, 200135, China


Abstract-The dual mode time-sharing photovoltaic (PV)
inverter is generally of higher efficiency compared to other types
because only one power stage operates in the high switching
frequency state at any time. In this paper, small-signal-model
comparison was made between the conventional dual mode
time-sharing inverter and the proposed dual mode time-sharing
cascaded inverter. It has been revealed with modeling that the
control-to-output voltage transfer function of the conventional
inverter has right half plane zero, and the system is difficult to be
controlled well, additionally, a simple compensator could hardly
meet the requirement on systems phase margin and amplitude
margin when the input voltage is lower than a half peak value of
the output voltage. However, it becomes much easier to design a
desired compensator for the proposed buck-type inverter. The
experiments in a 1kW prototype of proposed inverter verified the
theoretical analysis.
Index Terms: small-signal-model, dual mode, time-sharing,
photovoltaic inverter
I. INTRODUCTION
Photovoltaic (PV) generation system is one of attractive
renewable energy sources. The electrical characteristics of PV
panels vary with their types, manufacturing processes, and
temperature levels
[1]
. Many topologies and control methods
have been presented to reach a high performance
[1-9]
. Fig.1
shows a good solution of conventional dual mode time-sharing
inverter with a chemical DC-link capacitor for high efficiency
[6]
. However, the system is difficult to be controlled well. Few
papers investigated how to design a suitable control system for
this type inverter in detail
[6~9]
. In this paper, models of the
conventional dual mode time-sharing inverter and the proposed
one (as shown Fig.2)
[3]
will be derived. And the experiments in
a 1kW prototype of proposed inverter verified the theoretical
analysis.

Fig.1 Conventional dual mode time-sharing inverter

Fig.2 Proposed dual mode time-sharing cascaded inverter
II. MODELING OF THE DUAL MODE TIME-SHARING
INVERTER
A. Systems basic Operating Principle
Fig.3 shows the basic operating principle for the dual mode
time-sharing inverter. When the absolute instantaneous value of
the output AC voltage is lower than that of the input DC voltage
(named as Buck operating stage), the output power stage of
this type inverter (Full-bridge inverter) works in high frequency
state only.

Fig.3. Operating principle for dual mode time-sharing inverter
When the absolute instantaneous value of the output AC
voltage is higher than that of the input DC voltage (named as
Boost operating stage), the output power stage is in an
economical operating mode because the boost stage of the
conventional inverter operates in sine wave modulation, while
the current-fed circuit of the proposed one chops to shape the
head part of the sine wave.
B. Modeling for Buck operating stage
During Buck operating stage, the conventional inverter and
the proposed one can be simplified as Fig.4. Both could be
treated as buck converters.
TllMC?009 98!+?++3909$?.00 ?009 Tlll 2188

(a). Of conventional inverter

(b). Of proposed inverter
Fig.4 Equivalent circuits during Buck operating stage
The small signal models of these two inverters could be
derived as follows.
For the proposed topology, during a switching period T
s
, the
voltage of inductor L
2
could be described as:

=
=
) ( ) (
) ( ) ( ) (
22
1 21
t V t V
t V t V t V
o L
o C L
(1)
where V
L21
is the voltage of L
2
when the switch V
t2
is on, and
V
L22
is the voltage of L
2
when the switch V
t2
is off.
Using the state-space averaging method, Eq.1 could be
simplified as:
Ts
o
Ts
C
Ts
L
Ts
L
t V t V t d
dt
t i d
L t V ) ( ) ( ) (
) (
) (
1 1
2
2 2
= = (2)
where d
1
(t) is the duty-cycle of buck chopper converter, and
<x(t)>
Ts
is the average value in the switching period T
s
.
The currents of capacitors C
1
, C
2
and the voltage balance
equation could be described as:
Ts
L
Ts
in
Ts
C
Ts
C
t i t d t i
dt
t V d
C t i ) ( ) ( ) (
) (
) (
2 1
1
1 1
= = (3)
R
t V
t i
dt
t V d
C t i
Ts
o
Ts
L
Ts
C
Ts
C
) (
) (
) (
) (
2
2
2 2
= = (4)
Ts
C
Ts
in
t V t V ) ( ) (
1
= (5)
Unlike DC/DC converters, this circuit does not have a steady
state during the line frequency period, but it could be treated as a
quasi-steady-state in a switching period while analyzing a
steady state working point. The quasi-steady-state equation
could be expressed as:

=
=
=
=
1
1
2
2
C in
o C
o
L
L in
V V
V DV
R
V
I
DI I
(6)
where these variables are the quasi-steady-state values of the
circuit.
Using perturbation approach to the average model of Eq.2~5
with being ignored the high-order terms and being the variables
substituted by Eq.6 will lead to:

=
=
=
+ =

) ( ) (
) (
) (
) (
) ( ) ( ) (
) (
) ( ) ( ) (
) (
1
2 2
1 2 2
1
1
1 1 1
2
2
t V t V
R
t V
t i
dt
t V d
C
t d I t i D t i
dt
t V d
C
t V t d V t V D
dt
t i d
L
C in
o
L
C
L L in
C
o C C
L
(7)
where R, L
1
, L
2
, C
1
, C
2
are load resister, filter inductors and
capacitors of the proposed one respectively, and a variable with
a cap of ^ is the small-signal disturbance variable.
A similar process for the small signal model of conventional
topology will result in:

=
=
+ =
=

) ) ( ) (
) (
) (
) (
) ( ) ( ) (
) (
) ( ) ( ) (
) (
) ( ) (
) (
1
2
2
2
'
1 2 2 1
1
1
1
'
1 1
2
2
1
1
1
t i t i
R
t V
t i
dt
t V d
C
t d I t i D t i
dt
t V d
C
t V t V D t d V
dt
t i d
L
t V t V
dt
t i d
L
L in
o
L
C
L L L
C
o C C
L
C in
L
(8)
where R, L
1
, L
2
, C
1
, C
2
are load resister, filter inductors and
capacitors of the conventional inverter respectively.
Fig.5 shows the small-signal equivalent circuit models during
Buck operating stage.

) (t V
in

) ( ` t V
o

) (
2 `
t d I
L

) ( `
1
t d V
C

(a). Of conventional inverter
2189

) (t V
in

) (t V
o

) (
2
t d I
L

) (t d V
in

(b). Of proposed inverter
Fig.5 Small-signal equivalent circuit models during the Buck operating stage
The control-to-output voltage transfer functions of these two
inverters can be deduced as Eq.9 and Eq.10 respectively:
( ) R s L D L s R D C L C L C L s C L L s C C L L R
V R s L V D s C L V R
s G
in o in
vd
+ + + + + + +
+
=
) (
) (
2
2
1
2 2
2 1 2 2 1 1
3
1 2 1
4
2 1 2 1
1
2
1 1
1
'

(9)
R s L s C RL
R V
s G
in
vd
+ +
=
2
2
2 2
) (
1
(10)
It can be seen that the transfer function of conventional
inverter is a fourth-order system with two right half plane zeros,
while the transfer function of the proposed one is much simple.
C. Modeling for Boost operating stage
During Boost operating stage, the conventional dual mode
time-sharing inverter and the proposed one can be simplified as
that shown in Fig.6. The conventional inverter now works as a
boost chopper, while the proposed one is still a buck chopper.

(a). Of conventional inverter

(b). Of proposed inverter
Fig.6 Equivalent circuit during Boost operating stage
Based on the similar processed, the small signal models and
the small signal equivalent circuit models are shown in Equ.11,
Equ.12 and Fig.7, respectively. And the control-to-output
voltage transfer functions are deduced as Equ.13 and Equ.14
respectively.

=
=
=
=
+ =

) ( ) (
) (
) (
) (
) ( ) ( ) (
) (
) ( ) (
) (
) ( ) ( ) (
) (
1
'
'
'
2
2
2
'
2
2
1 1
1
1
'
'
1
2
2
'
2
1 1
' 1
1
'
'
'
'
' ' '
'
'
'
' '
'
t i t i
R
t V
t i
dt
t V d
C
t i t d I t i D
dt
t V d
C
t V t V
dt
t i d
L
t d V t V D t V
dt
t i d
L
L
in
o
L
C
L L L
C
o
C
L
C C
in
L
(11)

+ =
=
=
+ =
+ =

1 2 1
2
2
2
2
1 1
1
1
2
2
1 2
1
1
) ( ) ( ) (
) (
) (
) (
) (
) ( ) (
) ( ) ( ) (
) (
) ( ) ( ) (
) (
L L in
o
L
C
L
L C
o in C
L
C in in
L
I t d t Di t i
R
t V
t i
dt
t V d
C
t i
N
t i
dt
t V d
C
t V t V t V
dt
t i d
L
t V N t V D V t d
dt
t i d
L
(12)

) ( ` t V
in

) ( ` t V
o

) (
1 `
t d I
L

) ( `
1
t d V
C
1 : D

(a). Of conventional inverter

) (t V
in

) (
1
t d I
L

) (t d V
in

) (t V
o

) (t V
in

(b). Of proposed inverter
Fig.7 Small-signal equivalent circuit models during the Boost operating stage
( ) ( ) R D s D L L s R D C L C L C L s C L L s C C L L R
s
R D
L
D R V
s G
O
vd
+ + + + + + +

=
2 2
2 1
2 2
2 2 1 1 2 1
3
1 2 1
4
2 1 2 1
1
) (
) (
2
'
(13)
( ) ( ) R N s N L L Rs N C L C L C L s C L L s C C L RL
NRV
G
in
vd
2 2
2 1
2 2
2 2 1 1 2 1
3
1 2 1
4
2 1 2 1
2
+ + + + + + +
=
(14)
2190
III. DESIGN OF THE CONTROL COMPENSATOR FOR THE PROPOSED
INVERTER
Below are the main parameters of the conventional inverter
and the proposed one,
For the conventional inverter: V
in
=80V, V
o
=110V
rms
, the
switching frequency of boost and full-bridge inverter are 45kHz
and 30kHz respectively, L
1
=400uH, C
1
=30uF, L
2
=500uH,
C
2
=10uF, R=15ohm.
For the proposed one: V
in
=80V, V
o
=110Vrms, the switching
frequency of V
m1
, V
th1~4
, and V
t1~4
are 108kHz, 54kHz and
30kHz respectively, L
1
=160uH, C
1
=30uF, L
2
=500uH, C
2
=10uF,
R=15ohm.

Fig.8 Frame of control system

The frame of control system is shown in Fig.8, where G
c
(s) is
the transfer function of compensation network, G
m
(s) is the
transfer function of PWM modulator and H(s) is transfer
function of feedback network. Therefore, the original open-loop
transfer function is G
m
(s)G
vd
(s)H(s).
Unlike DC/DC converters, the duty-cycle of steady state for
DC/AC converters is not a fixed value. But it is known that the
output voltage waveform of an inverter distorts easiest when it
reaches its peak value. And the circuit could be regarded as
working at the worst condition under this duty-cycle. If the
circuit could be controlled well under this duty-cycle, the circuit
could work well in the whole line frequency period. So in this
paper, only the worst condition is analyzed either during the
Buck operating stage or the Boost operating stage. The
original open-loop bode plots of both stages are described in
Fig.9 and Fig.10 respectively.



(a). Of conventional inverter

(b). Of proposed inverter
Fig.9 Bode plots of the original open-loop control-to-output voltage transfer
functions during Buck operating stage

(a). Of conventional inverter

(b). Of proposed inverter
Fig.10 Bode plots of the original open-loop control-to-output voltage transfer
functions during Boost operating stage
Owing to the right half plane zeros, the conventional inverter
has a poor characteristic. It is difficult to design a simple
compensator to make the system work well. However, the
proposed topology is a buck type inverter in essence. Without
any right half plane zeros, it is much easier to design a desired
compensator.
2191
For example, during the Boost operating stage, the
cross-over frequency is designed at 20kHz, and the
compensators zeros are set to compensate the poles of the
original transfer function respectively, and the compensators
poles are designed at 108kHz to eliminate the ripple at the
switching frequency. It is easy to get a desired compensator as
following,
2 5
2 3 2 4 4
) 10 78 . 6 (
) 10 5 ( ) 10 ( 10 46 . 3
) (
+
+ +
=
s s
s s
s G
c
(15)
The root locus and bode plot of the compensated system is
shown in Fig.11. It can be seen that it is a stable system and has
a phase margin of about 54.2 degrees and an amplitude margin
of about 20.5 dB with enough low frequency gain.

Fig.11 Root locus and bode plot of the Compensated control-to-output voltage
transfer functions during Boost operating stage
IV. EXPERIMENTAL RESULTS
A 1kW 80/110V dc/ac inverter prototype shown in Fig.12 is
accomplished to demonstrate the proposed control strategy.
The experimental waveform is shown in Fig.13, where channel
1 is the output voltage and channel 2 is the load current. It can
be seen that the waveforms of output voltage and load current
are very sinusoidal, and these two waveforms have the same
phase.

Fig.12 Experimental prototype

Fig.13 Experimental waveform
V. CONCLUSIONS
This paper shows how to design a desirable compensator
based on the small-signal-model, and shows that the proposed
buck type converter without right half plane zero in its
control-to-output voltage transfer function is easier to be
compensated and has a better stability. The experimental
results on a 1kW prototype show the feasibility of this inverter.
ACKNOWLEDGMENT
The authors thank the supports from the National Natural
Science Foundation of China (NSFC) (No: 50707017), the
Leading Academic Discipline Project of Shanghai Municipal
Education Commission (No: J50602) and Innovative Project of
Shanghai Municipal Education Commission (No: 09YZ249)
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