An FPGA Implementation of a Feed-Back

Chaotic Synchronization for Secure

Communications
M. S. AZZAZ

,C. TANOUGAST

, S. SADOUDI

, A. BOURIDANE

and A. DANDACHE

Laboratoire Syst` emes de Communications,

Ecole Militaire Polytechnique, Alger, Alg erie

Laboratoire LICM, Universit e Paul Verlaine de Metz, Metz Technop ole, France

Northumbria University, Newcastle, United Kingdom

mohamed.azzaz@umail.univ-metz.fr, Camel.Tanougast@univ-metz.fr
AbstractIn this paper, we propose a hardware imple-
mentation of a Feed-Back Chaotic Synchronization (FCS)
for designing a real-time secure symmetric encryption
scheme. This proposed scheme allows for the design and im-
plementation of real time synchronization between two em-
bedded chaotic generators for secure communications. The
implementation and experimental results mapped on two
Xilinx FPGA Virtex technology platforms using two Lorenz
three-dimensional continuous chaotic systems demonstrate
the feasibility and the usefulness of this synchronization
approach in terms of performance and hardware resources
for embedded encryption systems.
I. INTRODUCTION
Chaos has been introduced to cryptography as its ergod-
icity, unpredictability, and sensitivity to parameter and ini-
tial condition meet the analogous requirements of a good
cryptosystem [1], [2]. One of the recent developments
of nonlinear dynamics and chaos was the realization of
the chaos synchronization between two identical chaotic
systems introduced by Pecora and Carroll [3] which can
be used in cryptography. This synchronization becomes
vital for accurate recovery of the transmitted signal in
encrypted communications based on chaotic generators.
Generally, the strategy of the secure communication based
on chaos approach consists of implementing a cipher
key chaotic generator used for the encryption of the
plaintext. A digital implementation of chaotic generators
presents some advantages and provides accuracy and
large possibility of integration in embedded applications
especially for data encryption and secures communica-
tions between embedded systems. Unlike, in an analogue
implementations which exhibit some practical difculties
to ensure information recovery and to deal with the
problem of the chaotic synchronization since the com-
ponent values vary with age, temperature, etc. [6], [7],
a digital implementation avoids the parameter mismatch
between the transmitter and the receiver. In this context,
advances in VLSI technology have been employed to the
manufacturing of recongurable logic including FPGA
chips and have helped their rapid growth in logic capacity,
performance and popularity. Recently, several structures
of chaotic systems have been implemented using FPGA
technology. For example, Lorenz, Chua or Chen systems,
which can be used for designing chaotic hardware key
generation for data encryption systems, have been pro-
posed [3], [4], [5], [6], [20]. However, digital hardware
implementations have not been proposed to implement the
synchronization between embedded chaotic generators.
In addition, some researchers in the area have been
then interested to investigate chaos synchronization in
various elds including secure communications, optics,
chemical and biological systems, etc. This paper pro-
poses a real-time hardware implementation of the Feed-
Back chaotic synchronization (FCS) between two chaotic
signal generators using FPGA technology. Our proposed
architecture can be used for synchronizing any three-
dimensional continuous chaotic systems (Chuas system,
L us system, Colpitts system, etc.) used as hardware key
cipher generator for encrypted communications [3], [4],
[5], [6]. The feasibility and efciency of our implementa-
tion approach are demonstrated from the synchronization
of two Lorenzs chaotic systems where one correspond to
a Master chaotic system embedded in one FPGA circuit
(Transmitter side) and the second is the Slave chaotic
system also embedded in an FPGA (Receiver side). This
paper is organized as follows. Section II reviews briey
the Lorenzs chaotic system. Section III details the chaotic
synchronization of two Lorenzs chaotic generators using
a Feed-Back Synchronization approach. Section IV gives
the modeling and RTL architecture of the master and slave
systems for use to map FCS synchronization. The syn-
thesis and hardware implementation results on Virtex-II
Xilinx FPGA technology and the performances evaluation
are also detailed in this Section. Section V shows the
hardware platform experimental and the real time results
of our implementation. Finally, a conclusion is given in
the Section VI.
II. LORENZS CHAOTIC MODEL
The system of Lorenz is a well known example of
a chaotic system. The Lorenzs three-variable model
provides a practical test case with qualitatively realistic
properties. It is represented by the following nonlinear
equation system [13]:

dx
m
dt
= (y
m
x
m
)
dy
m
dt
= x
m
z
m
+ rx
m
y
m
dz
m
dt
= x
m
y
m
bz
m
(1)
978-1-86135-369-6/10/$25.00 2010 IEEE
CCS-8 239 CSNDSP 2010
The solution of this nonlinear equation system depends
mainly on the Lorenzs parameters and the initial condi-
tions specied by the initial values of x = x
0
, y = y
0
and z = z
0
. The standard parameter values and initial
conditions for the Lorenzs chaotic attractor are: = 10,
r = 8/3 , b = 28 and x
0
= 0, y
0
= 5, z
0
=
20, respectively [12]. This model was integrated with
a fourth-order Runge-Kuttas numerical resolution (RK-
4 method) scheme with the following value for the time
step h = 0.01 [9], [20]. This means a higher precision
is adopted and is especially applicable to engineering
problems and will result in better and attractive random
numerical sequences x(n), n is cycle times of numerical
integral algorithm.
III. FEED-BACK CHAOTIC SYNCHRONIZATION
Figure 1 illustrates the principle of Feed Back chaotic
synchronization (FCS) adopted in our synchronization of
chaotic generators to evaluate the error rate.
Fig. 1. Illustration of the Feed-Back Chaotic Synchronization imple-
mentation.
In this implementation, the master Lorenz model of
the set of equations (1), and the slave system are nudged
toward values obtained from the master run as shown in
the set of equations (1):

dx
s
dt
= (y
s
x
s
)
dy
s
dt
= x
m
z
s
+ rx
m
y
s
dz
s
dt
= x
m
y
s
bz
s
(2)
Where the subscript m represents the master sys-
tem (x
m
, y
m
, z
m
) and s represents the slave system
(x
s
, y
s
, z
s
). We consider that the two trajectories of the
x
m
(t) and x
s
(t) chaotic signals are synchronized if :
lim
t
|x
m
(t) x
s
(t)| = 0 (3)
Unlike in an analogue implementation, our digital im-
plementation based on FPGA technology allows us to
synchronize two chaotic systems given the sensitivity of
the mismatch parameters . The structure of a Feed-Back
Chaotic Synchronization implementation is depicted in
Figure 2 which is based on Dynamic Feedback Modu-
lation (DFM) [13]. The role of the FCS is to transmit
the chaotic drive signal x
m
(t), which is then injected
into the two subsystems (y
m
, z
m
) and (y
s
, z
s
) (as il-
lustrated in Figure 2). At the receiver side, the slave
system regenerates the chaotic signal x
s
(t) and produces
a synchronization error rate between the received drive
and the regenerated drive signals. This technique can
be applied to chaotic modulation [13]. However, in this
case study it is used for generating chaotic keys for
Fig. 2. Functional architecture of the Feed-Back Chaotic Synchroniza-
tion.
stream cipher communications where the synchronization
between the Encrypter and the Decrypter is required.
Next section discusses our proposed implementation [13].
IV. PROPOSED ARCHITECTURE AND
MODELING
In this section, we present an optimized hardware
description of the master chaotic system dened by the
set of equations (1) of the transmitting side and the slave
chaotic system dened by the set of equations (2) of
the receiver side. Each system is implemented on Xilinx
FPGA technology Virtex-II pro [16].
A. RTL Architecture of the master and-slave chaotic
systems
Our proposed architecture consists of the implementa-
tion of the RK-4 method to resolve Lorenzs differential
equations system rst. An overview of the proposed
Register Transfer Level (RTL) architecture for the master
chaotic system is given in Figure 3. More precisely, this
gure depicts our data-path processing architecture which
is based on xed parameters , r and b as specied
in the previous Section. The architecture consists of the
structural feedback of the three main blocks: F
1
, F
2
and
F
3
. These three functional units implement the set of
equations (1) at the transmitter. where:

F
1
=
dx
m
dt
F
2
=
dy
m
dt
F
3
=
dz
m
dt
(4)
Similarly, RTL architecture of the slave chaotic system is
depicted in Figure 4. The parameters of the slave chaotic
system are similar to those of the master one but the three
main blocks implementing equations (1), is given by:

G
1
=
dx
s
dt
G
2
=
dy
s
dt
G
3
=
dz
s
dt
(5)
The RTL description of the proposed architecture
has been implemented on Xilinx Virtex-II FPGA
(XC2V1000) [16] using VHDL structural description.
ISE 10.1i of Xilinx tools [17] have been used for this
implementation allowing to obtain the logic resource
requirements and the associated real time constraints. The
synthesis results after place and route and performance
analysis of our implementation are shown in Table I
(master side) and Table II (slave side). These tables
specify the hardware resources in terms of the logic Slice
or the Slice Flip-Flops numbers and the performances.
CCS-8 240 CSNDSP 2010
Fig. 3. RTL architecture of the master chaotic system.
Fig. 4. RTL architecture of the Slave chaotic system.
TABLE I
IMPLEMENTATION RESULTS OF THE MASTER CRYPTOSYSTEM WITH
VIRTEX-II-PRO FPGA (2VP30FF896-7)
Transmitter device utilization summary FPGA: 2vp30ff896-7
Number of Slices 2038 out of 13696
Number of BRAMs 813 out of 136
Number of MULT 18X18s 40 out of 136
Maximum Frequency 29.837 MHz
TABLE II
IMPLEMENTATION RESULTS OF THE SLAVE SYNCHRONIZED
CRYPTOSYSTEM WITH VIRTEX-II-PRO FPGA (2VP30FF896-7)
Receiver device utilization summary FPGA: 2vp30ff896-7
Number of Slices 2038 out of 13696
Number of BRAMs 813 out of 136
Number of MULT 18X18s 40 out of 136
Maximum Frequency 29.837 MHz
The results and their analysis have demonstrated that
both the master and slave chaotic systems have similar
synthesis results when implemented independently on
FPGA (Transmitter and Receiver). This proves that a
real-time FCS can be efciency implemented with FPGA
technology. It can be stated that an attractive trade-off
between high speed and low logic resources has been
achieved. Indeed, our implementation on a Xilinx Virtex-
II device uses only 2038 CLB-Slices corresponding to
14 % of FPGA area, 40 multipliers and no block RAMs
for the master and the slave chaotic system because it
the transmitter is clearly symmetrical to the receiver. To
evaluate the behavior of the proposed system, it is neces-
sary to use some evaluation metrics. As adopted by the
research community, the metrics used for the evaluation
results for this system are the throughput rate and the
time latency. The throughput rate is dened as the number
of bits by unit of time. In our implementation, this rate
corresponds to 32 bit word-length during one operating
clock frequency. From the performance results (Table I or
Table II) it can be observed that a maximal throughput of
0.95 Gbps has been achieved. It is worth noting that this
CCS-8 241 CSNDSP 2010
Fig. 5. ModelSim simulation results of the proposed Chaotic Synchro-
nization and its error rate.
throughput rate is computed after the initialization phase.
Latency is dened as the time necessary to generate one
single word-length signal after the start of the generator.
Our optimized implementation of the master or the slave
chaotic systems requires 6 clock cycles to generate one
word-length chaotic signal. In our architecture, a time
latency of 200 ns has been obtained. Thus, the hardware
implementation clearly show attractive performances in
terms of the throughput and resource costs required.
B. Structural Description and Functional Simulation Re-
sults
The two proposed architectures (Master and Salve with
parameters: = 10, r = 8/3 and b = 28) are simulated
to ascertain their correct functional operation with test
vectors returned by a software implementation using
ModelSim simulator tool [18]. This validation consists to
model and describe in VHDL directly the RK-4 method
using the followings RK-4 value coefcients (h = 0.01,
coef = 1/6) [8]. Since the continuous chaotic signals
are real, our proposed architectures treat nite resolution
numbers using a binary representation. More precisely,
our data-path architectures have adopted hardware imple-
mentations based on nite solution numbers with a xed
point representation of the real data on 32 bits (16Q16).
i.e. all data are xed point format with 16 bits integer and
16 bits fraction. This xed-point arithmetic format allows
a very useful and attractive trade off between high speed
and low area cost because the presentation on 32 bits
(16Q16) gives more precision in the representation of the
real data while preserving the dynamic of the generated
chaotic signals. The ModelSim simulation results of the
Feed-Back chaotic synchronization between the Lorenzs
Master chaotic system of and the Lorenzs Slave chaotic
system; is shown in Figure 5.
The synchronization error is depicted in Figure 6. The
synchronization between the Master and Slave chaotic
systems is achieved after 470 samples. The time of
the simulation corresponding of the maximum frequency
allowed by the hardware synthesis is 0.033 s. This means
that the synchronization is completely realized between
the master and slave chaotic systems after 18 s running
as shown in Figure 7.
Fig. 6. Functional simulation of the synchronization error rate.
Fig. 7. Feed-Back Chaotic Synchronization after 18 s.
V. EXPERIMENTAL MEASUREMENTS
RESULTS
A real-time experimentation for our implementation of
the Feed-Back Synchronization between two XUP Virtex-
II-Pro FPGA platforms is shown in Figure 8. The rst
FPGA platform is congured as a transmitter which is em-
bedded by the Master chaotic signal characterized by the
set of equations (1) and modeled by the RTL architecture
depicted in Figure 3. At the other side the second FPGA
platform is congured as a receiver which is mapped
by the Slave chaotic signal characterized by the set of
equations (2) and modeled by the RTL architecture shown
in Figure 4. The transmitter and the receiver real-time
attractors measurements of our proposed architecture,
obtained by a direct implementation after optimization,
are depicted in Figures (9.a) and (9.c), respectively. These
Snapshots are given by a digital oscilloscope [19]. The
measured real-time signals of the drive signal X
m
and
the regenerated X
s
are presented in Figure (10.a). Based
on the Feed-Back Chaotic Synchronization principle, we
synchronize the response system to the drive system. By
using the Lorenz system, the chaotic synchronization is
achieved exactly, which is clearly shown in the Figure
(10.b). However, this synchronization is lost when an
error of 10
15
is introduced at one parameter of the slave
Fig. 8. Real time experimentation on FPGA platforms of the Feed-Back
Chaotic synchronization after 18 s running.
CCS-8 242 CSNDSP 2010
(a) (b)
Fig. 9. Real-time (x y) chaotic attractor of the Lorenz model: (a)
Transmitter attractor, (b) Receiver attractor.
(a)
(b) (c)
Fig. 10. Real-Time Feed-Back Chaotic Synchronization: (a) X
m
and X
s
chaotic signals, (b) Achieved synchronization, (c) de-
synchronization.
chaotic system (the receiver side) for example , this de-
synchronization is shown in Figure (10.c). These results
clearly conrm that the implemented chaotic synchroniza-
tion works well and veries the simulation results thereby
demonstrating its feasibility when using our proposed
architecture.
VI. CONCLUSION AND FUTURE WORK
This paper proposes a hardware implementation of a
Feed-Back Chaotic Synchronization for designing a real-
time secure symmetric encryption scheme. The proposed
implementation allows for the design of a real time
synchronization system between two embedded chaotic
generators for secure communications. Through a hard-
ware implementation using FPGA technology, we have
demonstrated that by considering two Lorenzs chaotic
generators as master and slave transmission systems, the
feasibility and efciency of our synchronization approach
is obtained. This has been achieved and veried by real-
time experimentation and simulation of the proposed
architectures. In addition, our experimental results show
the robustness of the synchronization technique (syn-
chronization achieved after 18 s running). Moreover,
our experimental results using Xilinx Virtex technology
have demonstrated that our approach can lead to designs
with small logic area, satisfactory throughput rates and
low latency for embedded applications. For example, an
implementation on a Xilinx Virtex-II technology requires
only 2038 CLB-Slices, 40 multipliers and no block RAMs
for each side (Transmitter, Receiver). Our FPGA imple-
mentation achieves a throughput rate of 0.95 Gbps at a
clock frequency of 29.837 MHz with a low latency time
of 200 ns. Once can clearly conclude the feasibility of
deploying a chaotic synchronization between two three-
dimensional continuous chaotic systems. Finally, our new
approach is very simple, exhibits attractive performances
and is useful in the eld of secure communications Ongo-
ing work is underway to further improve the performance
of the architecture targeting a full implementation in a
pipelined fashion although coming at the expense of an
increase the latency.
REFERENCES
[1] K. M. Cuomo, A.V. Oppenheim, and S.H. Strogatz, Synchroniza-
tion of Lorenz-based chaotic circuits with applications to communi-
cations, IEEE Trans. Cir. and Syst.-II, vol. 40, pp. 626633, 1993.
[2] U. Parlitz, L. O. Chua, L. Kocarev et al., Transmission of digital
signals by chaotic synchronization, Int. J. Bifurcations Chaos 2,
973977, 1992.
[3] L. M. Pecora and T. L. Carroll, Synchronization in chaotic sys-
tems, Physical Review Letters, 64(8), pp. 821824, 1990.
[4] T. Matsumoto, Chaos in electronic circuits, IEEE Inst. of Elec.
and Elecs Eng., vol.75, N.8, pp. 10331046, Aug.1987.
[5] C.Y. Cha and S.G. Lee, Complementary Colpitts Oscillator in
CMOS Technology, IEEE Transaction on microwave theory and
techniques, Vol. 53, N 3, March 2005.
[6] M. I. Sobhy, M. A. Aseeri and A. E. R. Shehata, Real Time Im-
plementation Of Continuous (Chua And Lorenz) Chaotic Generator
Models Using Digital Hardware, Proc. of the Third International
Symposium on Communication Systems Networks and Digital Pro-
cessing, pp.3841 , 1999.
[7] M.A. Aseeri, M.I. Sobhi and P. Lee, Lorenz Chaotic Model Using
Field Programmable Gate Array (FPGA), Midwest Symposium on
Circuit and Systems, pp. 686699, 2002.
[8] H. William Press, Brian P. Flannery, Saul A. Teukolsky and William
T. Vetterling, Numerical Recipes in C, The Art of Scientic
Computing, Cambridge University Press, 1992.
[9] C. Tanougast, S. Weber, G. Millerioux, A. Bouridane and J.
Daafouz, VLSI architecture and FPGA implementation of a hybrid
message embedded self-synchronizing stream cipher, 4th IEEE In-
ternational Symposium on Electronic Design, Test and Applications,
pp. 386389, 2008.
[10] M. S. Azzaz, C. Tanougast, S. Sadoudi, A. Bouridane, A. Dan-
dache, FPGA implementation of new Real-time Image Encryption
based switching chaotic systems, IET 20th Irish Signals and
Systems Conference, June 2009.
[11] Miller, R., M. Ghil, and F. Gauthiez, Advanced data assimilation
in strongly nonlinear dynamical systems, J. Atmos. Sci., vol. 51,
10371056, 1994.
[12] T. E. N. Lorenz, Deterministic nonperiodic ot, Journal of the
Atmospheric Sciences, Vol.20, N 2, pp.130141, March 1963.
[13] V. Milanovic and M.E. Zaghloul, Improved masking algorithm
for chaotic communications systems, IEE Electronics Letters, vol.
32, 1996.
[14] L. Kocarev, K. Halle, K. Eckert, and L. Chua, Experimental
demonstration of secure communication via chaotic synchroniza-
tion, Int. J. Bifur. Chaos, vol. 2, pp. 709713, Sept. 1992.
[15] Chi-Chung Chen and Kung Yao, Stochastic-calculus-based nu-
merical evaluation and performance analysis of chaotic communi-
cation systems, IEEE Transactions Circuits and Systems I: Funda-
mental Theory and Applications, Vol. 47, pp 16631672, 2002.
[16] Xilinx, Xilinx University Program Virtex-II Pro Development
System, Xilinx, UG069 (v1.1) April 9, 2008.
[17] Xilinx, Integrated Software Environment (ISE), Version 10.1,
Xilinx, 2008.
[18] Mentor Graphics, Modelsim SE Users Manuel, Sofware, Version
6.4, Mentor Graphics, 2008.
[19] Agilent, Digital Storage Oscilloscope DSO3202A, Agilent Tech-
nologies, Inc. 2008, June 25, 2008.
[20] M. S. Azzaz, C. Tanougast, S. Sadoudi and A. Dandache, Real-
time FPGA implementation of Lorenzs chaotic generator for ci-
phering telecommunications, IEEE Internation Circuits and Sys-
tems and TAISA Conference, pp. 14, 2009.
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