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DIGITAL ADC: VCO BASED ADC USING

DECIMATION FILTER

Synopsis Submitted in partial fulfillment of the Requirements for the degree of



Master of Technology (M. Tech)

In

Microelectronics & VLSI Design

Under the guidance of

Dr. Swapna Banerjee

By

Ramesh Prasad
(Roll no: 12EC62R20)






Department of Electronics & Electrical Communication Engineering

Indian Institute of Technology, Kharagpur

Kharagpur - 721302, West Bengal, India

April 2014

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ABSTRACT


The main objective of this work is to design an ADC which is suitable for high speed
applications with medium resolution, high bandwidth and low power. Since, ADC acts as a
connecting link between the Analog domain and digital domain. In deep sub-micrometer
process technologies, it is very difficult to design efficient ADC due to low voltage headroom
available for analog circuits and it also makes the analog circuits more complex whereas
digital circuits are faster and smaller with the advances in CMOS technology. Therefore ,
VCO based ADC is one of the best alternative with respect to other ADC architecture
because it makes extensive use of digital circuits and do not need accuracy in analog design.
Due to miniaturization of CMOS transistors in the integrated circuits results for faster
switching performance and reduced value of transconductance. In the design of data
converters higher gain bandwidth product is required in order to reduce the settling error of
op-amp. Digital circuits are basically known for faster switching response, while the lower
value of transconductance deteriorates the analog design. VCO based ADC provides the
advantages of Digital circuits and consumes lesser power with respect to other ADC
architecture. In this ADC, A sigma delta modulator using VCO is designed and digital
calibration is used in order to enhance the performance of VCO. The design is implemented
in 180nm UMC technology and the ADC achieves 56dB peak SNR and 54 peak SNDR at
600MHz sampling frequency for 20MHz input bandwidth and 11.2 mW.

Index Terms - Calibration, VCO based ADC, Sigma delta modulator, Voltage Controlled
Oscillator.









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1. Introduction
As we are living in analog world. There is need of circuits in order to fill the gap between the
analog domain and digital domain. The signals are converted into digital domain using digital
systems because it is easier to process the signals for various kind of operation in digital
domain rather than in analog domain.
As the technology is growing, there has been a continuous demand for higher bandwidth and
faster circuits. In earlier days, in order to develop faster circuit designers used the bipolar
transistor technology but it consumes a large amount of power [1]. But the use of BJT
technology was not suitable for mobile applications.
In order to achieve high speed and lower power consumption circuit designers moved to
CMOS technology [2]. Initially, with respect to speed CMOS technology always lagged
behind BJT technology but with the scaling in CMOS technology it became capable of
achieving high speed.

Figure 1(a) Performance Vs Power (Analog-Digital Converter)
Impact of Technology Scaling: In modern technology process it is very difficult to design
converters with low voltage headroom. The supply voltage is also reduced as per the
technology scaling, in order to maintain the signal to noise ratio it is also very important to
minimize the noise of converters. In most advanced processes, this limitation is handled by
utilizing thicker gate oxides but at the same time it affects the speed of operation.
Minimalistic Design: The primary motive of minimalistic design is to enhance the speed and
power efficiency by simplifying the analog circuits, because Power dissipation of ADC is
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directly dependent on the complexity of analog circuits. The simplification of analog circuits
can affect the precision of ADC and remedy of the problem is to move towards digital design.
Digitally Assisted Architectures: The digital logic can assist any converter for the purpose
of calibration and error correction. Technology scaling has significantly reduced the energy
per operation in CMOS logic circuits. For 0.5m technology the 2 input NAND gate
dissipates 1.23 pJ per operation whereas same gate dissipates 4.4fJ per logic operation in 90
nm Technology.

Table 1.1 E
NAND
Vs E
ADC
As shown in table, for 50 dB signal fidelity and E
NAND
=4.39fJ per logic operation, A single
conversion of ADC would consume as much as energy of approximately 38000 gates.
Generally, Converters basically depends upon three performance parameters i.e (a) Power
Consumption (B) Sampling Speed and (C) Resolution. Power consumption is one of the key
parameter to be taken into consideration for designing low power converters. The sampling
speed is defined as Samples per second. Basically it defines the measurement of number of
samples of analog signal for a given time frame. Resolution can be defined through Signal to
Noise Distortion Ratio (SNDR). Higher the values of SNDR, higher will be the resolution.
All these three performance parameter can be combined to define a term called Figure of
Merit (FOM). This term is used to define the performance of ADC .According to following
equation,
F0H = 2
-LN0B

P

Figure 1(b) shows the different kind of ADC architectures having different sampling speeds,
resolution and the applications demanding them. For very high bandwidth ADC the sampling
speed of the ADC must be in several of MHz.
2. Motivation
As we know analog to digital converter are very important block electronics systems in
modern time. Modern integrated technology can provide very high sampling rates but at the
cost of high power consumption. For e.g. [3,4] This ADC provides a sampling rate of
20G/sec at power dissipation of 10W at 1.2 W. In most cases, the performance and efficiency
are mainly affected by the rate at which analog signal is converted into digital.
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Figure 1(b) Different architecture of ADC
Analog to digital converter is easier to design in digital domain rather than in analog domain
because of reduced threshold voltage problem and low power supply voltage. The signal
process capability is also enhanced and improved in digital as compared to analog
counterparts - better repeatability, automatic synthesis and testing, very low sensitivity in
noise. Fig.1(c) & (d). Shows a scatter plot of results published at these venues over the past
eleven years [4].

Figure 1(c) Power efficiency versus SNDR Figure 1(d) Conversion b/w versus SNDR.
Due to several advantages, design of ADC digitally has gained so much popularity as
compared to analog ADC. There are several ways to design converters digitally but one way
is to convert the analog information into the time domain and convert the pulse widths (time
domain intervals) into digital codes. Reduction in supply voltage and shrinkage in transistor
size, ADC are designed in time domain instead of analog domain.

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3. VCO based Analog-Digital Converter
VCO based ADC is one of the best option for designing analog to digital converter in
advanced technology. A VCO based ADC is oversampling converts which uses sampling
frequency much higher than the Nyquist frequency and it uses time based architecture which
consists of VCO and digital circuits [7]. Analog input signal controls the frequency of the
VCO frequency and VCO converts the signal from voltage domain to phase domain. The
digital part consists of Counter along with other digital circuitry and counter counts the
number of edges of multiphase oscillator outputs for a clock period and generates the
required digital output. The resolution of the ADC can be improved with the increase in the
number of phases generated from the VCO [10]. The quantization error of previous sampling
period becomes the initial phase for the next sampling period. ADC output is given by the
expression,

y[n] =
N
mp
(
x
[n] +
xq
[n 1]
q
[n])
2n

Where
x
[n] is the VCO phase change due to analog input signal and N
mp
is the number of
VCO phases.

y[n] =
N
mp
(
x
[Z] +(Z
-1
1)
q
[Z])
2n

VCO plays the role of integrator in time domain and convert the signal into time variation
from amplitude variation. But apart from several advantages it has some demerits also [7].
VCO tuning curve for control voltage is non linear in nature which is a matter of concern.
While a voltage controlled oscillator has a variety of unusual and interesting properties, it has
two major advantages that are very much attractive and relevant in the design of ADCs.
First, the VCO acts as a voltage-to-phase integrator. The instantaneous VCO output
frequency F
out
is proportional to the applied input voltage V
tune
(t) according to the voltage-
to-frequency gain K
v
[Hz/V]. The resulting voltage controlled oscillator output phase
out
(t)
is proportional to the time integral of the applied input voltage.
Note that as long as the VCO oscillates, the VCO output phase will accumulate endlessly,
even for a DC input. This implies that the VCO behaves as a CT integrator with infinite DC
gain. A second property of interest is the digital nature of a ring-VCOs outputs [8]. Note that
while the VCO output phase and frequency are continuously varying, the VCO output itself
toggles between two discrete levels V
DD
and Gnd , much like a CMOS digital gate .Multi-
phase (or equivalently, multi-bit) quantization can be accomplished by sampling the output
phases of a ring oscillator with an array of D-flip-flops [9]. Note that since the VCO phases
are full-swing logic signals, the quantizer is robust to voltage offsets in the flip-flops. At the
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same time, only one VCO edge transitions at a given sampling instant, while the rest of the
VCO phases saturate to either V
DD
or Gnd. Consequently, the quantizer not only is less prone
to generate meta-stable outputs, but also has guaranteed monotonicity without requiring any
calibration.
A new methodology is proposed in which the non linearity of VCO is taken care by look up
table based calibration and the limited time resolution is taken care by the phase interpolator
which results in the improvement in SFDR, thus enhancing the efficiency of the conversion.
This architecture of VCO based is in open loop nature because the problem of non linearity
and low resolution can be resolved by employing the voltage controlled oscillator in closed
loop manner but at the same time it occupies large area. So, off chip digital calibration
technique is one of the methods which can be used to enhance the performance of ADC
The primary target of this work is to design ADC with 8 bit resolution, high bandwidth (upto
20MHz) and low power. Thus, a new design technique is defined in which digital signal edge
transition is superior to the analog voltage resolution.

Fig 1(e) Implemented analog digital converter

Fig 1(f) Implemented delay cell for VCO
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Fig 1(g) Phase interpolator

Fig 1(h) Differential ring VCO with phase interpolator

Fig 1(i) Phase Quantizer
4. Organization of Thesis
The thesis is divided into 6 chapters. The first chapter consists of the introduction, motivation
and objective of the project. The second chapter consists of literature survey on various kinds
of ADC architectures and their advantages and disadvantages. The third chapter provides the
detailed theoretical information on various kind of circuits used at block level like differential
VCO, Quantizer, filter etc. The fourth chapter provides the detailed information on the
implementation of VCO based ADC in UMC 180nm technology. The fifth chapter gives the
information regarding the schematic simulation results and post layout simulation results.
And the last chapter gives the conclusion and future work.

5. Conclusion
Digital analog to digital converters have potential applications in very low voltage, low
power circuits. Moreover, the implementation of such converters is fully compatible with the
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standard digital CMOS technology. Actually one important feature of Digital ADC is that,
advances in process technology allow the same architecture to achieve a high sampling
frequency and better resolution as well as lower power consumption.
The design is implemented in UMC 180nm CMOS process with a supply voltage and it can
be used for lower supply voltage and sub micron technologies. The VCO ADC is designed
with approx 20 MHz bandwidth and SNR/SFDR of value 47.2 dB/ 57 dB.
The Dynamic performance of VCO based ADC can be improved in open loop configuration
with digital calibration and decimation filter techniques.

6. References
[1] R. Hagelauer, F. Oehler, G. Rohmer, J. Sauerer, and D. Seitzer, A gigasample/second 5-
b ADC with on-chip track and hold based on an industrial GaAs MESFET E/D process,
IEEE Journal of Solid-State Circuits, vol. 27, no. 10, pp. 13131320,1992.
[2] M. Choi and A. Abidi, A 6 b 1.3 GSample/s A/D converter in 0.35 mu;m CMOS, in
International Solid-State Circuits Conference, pp. 126127, 438, 2001.
[3] B. Murmann, "Digitally Assisted Analog Circuits A Motivational Overview," ISSCC
Special-Topic Evening Session(SE1.1), Feb. 2007.
[4] P. Schvan, et al, A 24GS/s 6b ADC in 90nm CMOS,ISSCC Dig. Techn. Papers, pp.
544-545, Feb. 2008.
[5] K. Poulton, et al., A 20-GSample/s 8b ADC with a 1-MByte Memory in 0.18-um
CMOS, ISSCC Dig. Techn. Papers, pp. 318-319, Feb. 2003.
[6] B. Murmann, "ADC Performance Survey 1997-2008," [Online]. Available:
http://www.stanford.edu/~murmann/adcsurvey.html.
[7] Jaewook kim, Tae-Kwang jang, Young-Gyu Yoon and Seong Hwan Cho, Analysis and
Design of VCO based ADCs, IEEE transactions on circuits and systems, Vol.57, No.1, Jan
2010.
[8] Sachin Rao, Brian Young, Amr Elshazly, Wenjing Yin, Naga Sasidhar, and Pavan Kumar
Hanumolu, A 71dB SFDR Open Loop VCO-Based ADC Using 2-Level PWM Modulation,
2011, Symposium on VLSI Circuits.
[9] Engel Roza, Analog-to-Digital Conversion with duty cycle modulation, IEEE
transactions on circuits and systems, Analog and Digital Signal processing, Vol.44, No.11,
November 1997.
[10] C.H.Park and B.Kim , A Low noise , 900MHz VCO in 0.6m CMOS, IEEE J. Solid
State Circuits , vol. 34 , no. 5 ,pp. 179-194, May 1999.