Vous êtes sur la page 1sur 11

What do you mean by HDLs ?

Hardware description language or HDL is any language from a class of

computer languages and/or programming languages for formal description of
electronic circuits, and more specifically, digital logic. It can describe the
circuit's operation, its design and organization, and tests to verify its operation
by means of simulation. HDLs are standard textbased expressions of the spatial
and temporal structure and behaviour of electronic systems. Li!e concurrent
programming languages, HDL syntax and semantics includes explicit notations for
expressing concurrency. Ho"ever, in contrast to most soft"are programming
languages,HDLs also include an explicit notion of time, "hich is a primary attribute
of hard"are Languages "hose only characteristic is to express circuit connectivity
bet"een a hierarchy of bloc!s are properly classified as netlist languages used on
electric computeraided design .#HDL and #$%IL&' are the t"o most "idely
used Hard"are description languages .
What is VLSI Design ?
#L(I Design stands for #ery Large scale Integrated circuit design.
Very-large-scale integration )VLSI* is the process of creating integrated circuits
by combining thousands of transistorbased circuits into a single chip
#L(I "hich involves the pac!ing of more and more logic devices into smaller
and smaller areas.
What is VHDL ? What are capabilities of VHDL ?
#HDL is a programming language, much li!e +,,, it has its o"n syntax and
semantics. -he big difference from traditional programing languages is that
instead of describing instructions "hich a processor "ill execute, it describes
ho" circuits should be organized.#HDL is basically a programming language
used to model digital (ystems. .s it is emulating real hard"are it is inherently
parallel and also treats timing as important. -his language is a commonly used
in the design of fieldprogrammable gate arrays)/0'.*and application specific
integrated circuits).(I+*. #HDL stands for #ery High (peed Integrated +ircuit
Hard"are Description language.#HDL is composed of language building bloc!s
that consist of more than 75 reserved words and about 200 descriptive
words or word combinations.
What can be the various uses of VHDL ?
-he #HDL language can be used for several goals li!e
i* -o synthesize digital circuits
ii* -o verify and validate digital designs
iii* -o generate test vectors to test circuits
iv* -o simulate circuits
What are the Various levels of abstractions in VLSI design?
.bstraction is defined as the hiding of information that is too detailed.
It is therefore necessary to diffrentiate bet"een essential and
nonessential information. Information that is not important for the
current vie" of the problem "ill be left out from the description
-he #arious levels of abstraction in #L(I design are 1
2. 3ehaviour level
4. %-L )%egister -ransfer level*
5. Logic level
6. Layout )-ransistor level*
In the behaviour level, complete systems can be modelled. 3us
systems or complex algorithms are described "ithout considering
synthesizability. -he stimuli for simulation of %-L models are described
in the behaviour level, for example. (timuli are signal values of the
input ports of the model and are described in the testbench,
sometimes called validation bench.
-he designer has to ta!e great care to find a consistent set of input
stimuli that do not contradict the specification. -he responses of the
model have to be compared "ith the expected values "hich, in the
simplest case, can be done "ith the help of a "aveform diagram that
sho"s the simulated signal values.
&n the %- level, the system is described in terms of registers and logic
that calculates the next value of the storage elements. It is possible to
split the code into t"o bloc!s )cf. process statement* that contain
either purely combinational logic or registers. -he registers are connected
to the cloc! signal and provide for synchronous behaviour. In practice,
the strict separation of /lip /lops from combinational logic is often
annulated and cloc!ed processes describe the registers and the
corresponding update functions.
-he gate netlist is generated from the %- description "ith the help of a
synthesis tool. /or this tas!, a cell library for the target technology "hich
holds the information about all available gates and their parameters
)fanin, fanout, delay* is needed.
3ased upon this gate netlist the circuit layout is generated. -he resulting
"ire lengths can be converted into propagation delays "hich can be fed
bac! into the gate level model )bac! annotation*. -his allo"s for thorough
timing simulations "ithout the need for additional simulator soft"are.
What is Synthesis?
(ynthesis represents the transformation of an abstract description into a
more detailed descrition. In general, the term 7synthesis7 is used for the
automated transformation of %- level descriptions into gate level representations.
-his transformation is mainly influenced by the set of basic cells that is available
in the target technology. 8hile simple operations li!e comparisons and either/or
decisions are easily mapped to boolean functions, more complex constructs li!e
mathematical operators are mapped to a tool specific macro cell library first.
-his means that a number of adder, multiplier, etc. architectures are !no"n
to the synthesis tool and these designs are treated as if they "ere designed
by the user.
What is the difference between Entity and rchitecture ?
-he interface bet"een a module and its environment is described "ithin
the entity declaration "hich is initiated by the !ey"ord ' entity '. It is
follo"ed by a userdefined descriptive name. -he interface description
is placed bet"een the !ey"ord ' is ' and the termination of the entity
statement "hich consists of the !ey"ord ' end ' and the name of the entity.
-he input, output and bidirectional ports are defined in the entity.
In the ne" #HDL'95 standard the !ey"ord ' entity ' may be repeated after
the !ey"ord ' end ' for consistency reasons.
-he architecture contains the implementation for an entity "hich may be
either a behavioural description )behavioural level or, if synthesizable,
%- level* or a structural netlist or a mixture of those alternatives..
.n architecture is strictly lin!ed to a certain entity. .n entity, ho"ever,
may have several architectures underneath, e.g. different
implementations of the same algorithm or different abstraction levels.
.rchitectures of the same entity have to be named differently in order
to be distinguishable. -he name is placed after the !ey"ord ' architecture '
"hich initiates an architecture statement. '%-L' "as chosen in this case.
It is follo"ed by the !ey"ord ' of ' and the name of entity that is used as
interface )'H.L/.DD$%'*. -he architecture header is terminated by the
!ey"ord ' is ', li!e in entity statements. In this case, ho"ever, the !ey"ord
' begin ' must be placed some"here before the statement is terminated.
-his is done the same "ay as in entity statements1 -he !ey"ord ' end ',
follo"ed by the architecture name. &nce again, the !ey"ord ' architecture '
may be repeated after the !ey"ord ' end ' in #HDL'95.
E!plain Various types of "odelling styles ?
-he #arious modelling styles are 1
(tructural, behavioural, dataflo" and mixed style.
Structural Description Method# It expresses the design as an
arrangement of interconnected components. It is basically the
representation of the schematic in #HDL Language form.
Behavioral Description Method1 describes the functional behavior of a
hard"are design in terms of circuits and signal responses to various stimuli.
. 3ehavioral Description uses a small number of processes "here each process
performs a number of se:uential signal assignments to multiple signals.
-he hard"are behavior is described algorithmically and this modelling style
is the most fre:uently used and the best "ay to model any algorithm.
-he advantage of models at this level is that models for simulation can be
built :uic!ly.
Data-Flow Description Method1 is similar to a registertransfer language
-his method describes the function of a design by defining the flo" of
information from one input or register to another register or output.
Data/lo" Description uses a large number of concurrent signal assignment
statements. . concurrent statement executes asynchronously "ith respect
to other concurrent statements.
-he concurrent statements used in data flo" description include1
bloc! statement )used to group one or more concurrent statements*
concurrent procedure call concurrent assertion statement
concurrent signal assignment statement
E!plain various types of delays in VHDL ?
-he #arious types of delays in #HDL are 1
2. Delta delay In #HDL simulations, all signal assignments occur "ith some
infinitesimal delay, !no"n as delta delay. #HDL uses the concept of delta
delay to !eep trac! of processes that should occur at a given time step,
but are actually evaluated in different machine cycles .. delta delay is a
unit of time as far as the simulator hard"are is concerned, but in the
simulation itself time has no advance. -echnically, delta delay is of no
measurable unit, but from a hard"are design perspective one should thin!
of delta delay as being the smallest time unit one could measure, such as
a femtosecond)fs*.
4. Inertial delay -he inertial delay causes the pulses less than specified delay
to get suppressed ; "ill not propogate these pulses to change the output.
-he inertial delay model is specified by adding an after clause to the
signal assignment statement. Inertial delay is basically a default delay,
i.e it's a component delay.
5. Transport delay - -ranport delay adds the propogation delay to the signal.
-he transport delay model <ust delays the change in the
output by the time specified in the after clause.
-ransport delay basically represents a "ire delay.
e.g. q <=transport a nor b after 1ns ;
What are $enerics ?
'enerics are a "ay to provide static information to the #HDL program.
Immediately after "riting entity name, "e "ill mention the generics,
this generics "ill provide the data for entire program.
'enerics basically allo" a design entity to be described so that,for each use
of that component,its structure and behavior can be changed by
generic values.In general they are used to construct parameterized
hard"are components.'enerics can be of any type%but mostly "e "ill give the timing
details there.
$.g. 1 generic ) "idth 1 integer 1= > *?
'eneric is a great asset "hen you use your design at many places "ith
slight change in the register sizes,input sizes etc. 3ut if the design is very
uni:ue then,you need not have generic parameters. .lso, 'eneric's are
What is the difference between S&D'L($I) and *I& types?
3I- has 4 values1 '@' and '2'.
(-DAL&'I+ is defined in the library stdAlogicA22B6.-his is a nine valued logic system.
It has 9 values1 'C', 'D', '@', '2', 'E', '8', 'L' ,'H' and ''.
-he meaning of each of these characters are1
C = uninitialized
D = un!no"n a multisource line is driven '@' and '2' simultaneously )F*
@ = logic @
2 = logic 2
E = high impedance )tri state*
8 = "ea! un!no"n
L = "ea! 7@7
H = "ea! 727
= dont care
-ype stdAlogic is unresolved type because of 'C','E' etc. It is illegal to
have a multisource signal in #HDL. (o use 'bit' logic only "hen the signals
in the design doesn't have multi sources. If you are unsure about this then
declare the signals as stdAlogic or stdAlogicAvector,because then you "ill
be able to get errors in the compilation stage itself. 3ut many of the operators
such as shift operators cannot be used on 'stdAlogicAvector' type.(o you may
need to convert them to bitAvector before using shift operations.
&ne example is given belo"1
example of ho" to shift a stdAlogic signal 1 right shifting logically by 4 bits.
Here, count is stdAlogicAvector.
output G= -oA(tdLogic#ector)toAbitvector)count* srl 4*? toAbitvector converts
(tdALogicA#ector to bitAvector. -oA(tdLogic#ector converts bitAvector to (tdALogicA#ec
What is the difference between )oncurrent + Se,uential Statements ?
+oncurrent statements define interconnected processes and bloc!s that
together describe a designHs overall behavior or structure. -hey can be grouped
using bloc! statement. 'roups of bloc!s can also be partitioned into other bloc!s.
.t the same level, a #HDL component can be connected to define signals "ithin the bloc!s
It is a reference to an entity
. process can be a single signal assignment statement or a series of se:uential statements )((*
8ithin a process, procedures and functions can partition the se:uential statements
Discuss process and wait statements? )an they be used simultaneously
in the program ?
II+&J0L$-$ .I(8$%
-he #arious features of the process statement are 1
It contains se:uentially executed statements
It can exist "ithin an architecture only
(everal processes run concurrently
$xecution is controlled either via
sensitivity list )contains trigger signals*, or
-he process label is optional
3ecause the statements "ithin an architecture operate concurrently, therefore another
#HDL construct is necessary to achieve se:uential behaviour. . process, as a "hole, is
treated concurrently li!e any other statement in an architecture and contains statements
that are executed one after another li!e in conventional programming languages. In fact
it is possible to use the process statement as the only concurrent #HDL statement.
-he execution of a process is triggered by events. $ither the possible event sources are
listed in the sensitivity list or explicit "ait statements are used to control the flo" of
-hese t"o options are mutually exclussive, i.e. no "ait statements are allo"ed in a
"ith sensitivity list. 8hile the sensitivity list is usually ignored by synthesis tools, a #HDL
simulator "ill invo!e the process code "henever the value of at least one of the listed
changes. +onse:uently, all signals that are read in a purely combinational process, i.e.
influence the behaviour, have to be mentioned in the sensitivity list if the simulation is to
produce the same results as the synthesized hard"are. &f course the same is true for
cloc!ed processes, yet ne" register values are to be calculated "ith every active cloc!
only. -herefore the sensitivity list contains the cloc! signal and asynchronous control
)e.g. reset*.
. process statement starts "ith an optional label and a '1' symbol, follo"ed by the
' process '
!ey"ord. -he sensitivity list is also optional and is enclosed in a ')' '*' pair. (imilar to the
architecture statement, a declarative part exists bet"een the header code and the
' begin '. -he se:uential statements are enclosed bet"een ' begin ' and ' end
process '.
-he !ey"ord ' process ' has to be repeatedK If a label "as chosen for the process, it has
be repeated in the end statement, as "ell.
What is the difference between Signal and the Variable ?
(ignals are interpreted as "ires or "ires "ith memory )i.e., //s, latches etc.*
Signal are declared as :-
signal signal_nae! signal_nae! """ : data_type
Signal assignent :-
signal_nae #$ pro%ected_wa&e'or(
-he +oncept of variables is found in traditional programming languages, in
"hich a name represents a symbolic memory location "here a value can be
stored and modified. -here is I& direct mapping bet"een a variable and a
hard"are component. #ariables can be declared and used only inside a process.
Variable declaration:
&ariable &ariable_nae! """ : data_type
Variable assignent:
&ariable_nae :$ &alue_e)pression(
#ariables contains no timing information )immediate assignment* i.e. no
"aveform is possible for variables.
3oth signals and variables can be assigned initial values.
.lthough useful in simulations, synthesis canI&- deal "ith them
What are VHDL Subtypes ?
#HDL subtypes are used to constrain defined types. +onstraints ta!e the
form of range constraints or index constraints. Ho"ever, a subtype may
include the entire range of the base type. .ssignments made to ob<ects
that are out of the subtype range generate an error at run time. -he syntax
and an example of a subtype declaration is sho"n belo" 1
(C3-L0$ /irstAten I( II-$'$% %.I'$ @ to 9?
E!plain -esolution .unction ?
. resolution function defines ho" values from multiple sources, multiple drivers,
are resolved into a single value. -he signals in #HDL can have multiple drivers.
-he value of the signal is a function of all the drivers of that signal. -he
follo"ing figure sho"s an example of a bus signal "hich is driven by four
independent signals. -he value bus is computed by a bus resolution
function )brf in this example*.
. resolution function must be a pure function that has a single input
parameter of class constant that is a one dimensional unconstrained
array of the type of the resolved signal.
-he drivers are labeled s*!s2!s+! and s,. -he value of the signal dbus is
computed by a bus resolution function )br' in our example*. 3us resolution
functions are userdefined and are evaluated "hen one of the drivers of the
signal receives a ne" value )event*. -he 'resolved' value is then generated
by the bus resolution function
Write short notes on )ase statements ?
.ll branches are e:ual in priority "hen using a +.($ statement.
-herefore it is obvious that there must not be any overlaps
among cases or choices and all possible values of the +.($ $D0%$((I&I
must be covered. /or covering all remaining, i.e. not yet covered,
cases, the !ey"ord ' others ' may be used.
-he type of the $D0%$((I&I in the head of the +.($ statement
has to match the type of the :uery values. (ingle values of $D0%$((I&I
can be grouped together "ith the 'M' symbol, if the consecutive action
is the same. #alue ranges allo" to cover even more choice options
"ith relatively simple #HDL code.
when VALUE_1 =>
-- sequential statements
when VALUE_2 | VALUE_3 =>
-- sequential statements
when VALUE_4 to VALUE_N =>
-- sequential statements
when others =>
-- sequential statements
end case ;
Write short note on Loop statement and /e!t statement ?
Three kinds of iteration statements.
[ label: ] loop
sequence-of-statements -- use eit statement to get out
end loop [ label ] ;
[ label: ] for !ariable in range loop
end loop [ label ] ;
[ label: ] "hile condition loop
end loop [ label ] ;
eit "hen end#file;
end loop;
for $ in 1 to 1% loop
&&'$( := %;
end loop;
"hile not end#file loop
end loop;
all kinds of the loops ma) contain the *net* and *eit* statements.
& statement that ma) be used in a loop to cause the net iteration.
[ label: ] net [ label+ ] [ "hen condition ] ;
net outer#loop;
net "hen &,-;
net this#loop "hen .=/ or done; -- done is a -oolean !ariable
Discuss the Difference between array and records types ?
--1S #0#HDL composite types consists of arrays and records. $ach ob<ect of
this data type can hold more than one value% .rrays consist of many
similar elements of any data type, including arrays. -he array is declared
in a -L0$ statement. -here are numerous items in an array declaration.
-he first item is the name of the array. (econd, the range of the array is
declared. -he !ey"ords -& and D&8I-& designate ascending or descending
indices, respectively, "ithin the specified range. -he third item in the array
declaration is the specification of the data type in each element of the array.
$.g 1 -L0$ dataAbus I( .%%.L )@ to 52* &/ 3I- ?
-L0$ regAtype I( .%%.L )2N do"nto @* of 3I- ?
-E)(-DS #0
-he second #HDL composite type is the record. %ecords are used to group
elements of different types into a single #HDL ob<ect. .n ob<ect of type record may
contain elements of different types. .gain, a record element may be of any data
type, including another record. . -L0$ declaration is used to define a record.
Iote that the types of a record's elements must be defined before the record
is defined. .lso notice that there is no semicolon after the "ord %$+&%D. -he
%$+&%D and $ID %$+&%D !ey"ords brac!et the field names. .fter the %$+&%D
!ey"ord, the record's field names are assigned and their data types are specified.
$.g 1 -L0$ ("itchAinfo I(
status 1 binary ?
Idnumber 1 integer ?
$ID %ecord?
s"itch.status = &I?
s"itch.IDnumber = 5@?
In the above example, a record type, s"itchAinfo, is declared. -his example ma!es
use of the binary enumerated type declared previously. Iote that values are
assigned to record elements by use of the field name.