Lecture 160A Bipolar Technology (6/22/04)

Page 160-1

LECTURE 160 BIPOLAR TECHNOLOGY

(READING: Text-Sec. 2.4, 2.5)
INTRODUCTION
Objective
The objective of this presentation is:
1.) Illustrate the fabrication sequence for a typical bipolar junction transistor
2.) Show the physical aspects of the BJT
Outline
npn BJT technology
Compatible pnp BJTs
Modifications to the standard npn BJT technology
Advanced BJT technology
Summary

ECE 4430 - Analog Integrated Circuits and Systems

Lecture 160A Bipolar Technology (6/22/04)

P.E. Allen - 2004

Page 160-2

npn BIPOLAR JUNCTION TRANSISTOR TECHNOLOGY

Major Processing Steps for a Junction Isolated BJT Technology
Start with a p substrate.
1. Implantation of the buried n+ layer
2. Growth of the epitaxial layer
3. p+ isolation diffusion
4. Base p-type diffusion
5. Emitter n+ diffusion
6. p+ ohmic contact
7. Contact etching
8. Metal deposition and etching
9. Passivation and bond pad opening

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Lecture 160A Bipolar Technology (6/22/04)

Page 160-3

Implantation of the Buried Layer (Mask Step 1)

Objective of the buried layer is to reduce the collector resistance.

TOP
VIEW

n++ implantation for buried layer

SIDE
VIEW

p substrate

p-

p+

n-

ni

n+

Metal

Fig.160-01

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P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-4

Epitaxial Layer (No Mask Required)

The objective is to provide the proper n-type doping in which to build the npn BJT.
Assume the n+ buried layer can be seen underneath the epitaxial collector

TOP
VIEW

n collector

Epitaxial
Region

SIDE
VIEW
n+ buried layer
p substrate

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

ni

n-

n+

Metal

Fig.160-02

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-5

p+ isolation diffusion (Mask Step 2)

The objective of this step is to surround (isolate) the npn BJT by a p+ diffusion. These
regions also permit contact to the substrate from the surface.
Assume that the n+ buried region can be seen

TOP
VIEW

n collector

p+
isolation

p+
isolation

p+
isolation
n collector

SIDE
VIEW

n+ buried layer
p substrate

p-

p+

n-

ni

n+

Metal

ECE 4430 - Analog Integrated Circuits and Systems

Fig.160-03

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-6

Base p-type diffusion (Mask Step 3)

The step provides the p-type base for the npn BJT.

TOP
VIEW
n collector

p base

p+
isolation

pisolation

p base
n collector

SIDE
VIEW

n+ buried layer
p substrate

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

ni

n-

n+

Metal

Fig.160-04

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-7

Emitter n+ diffusion (Mask Step 4)

This step implements the n+ emitter of the npn BJT and the collector ohmic contact.

TOP
VIEW

p+
isolation

n+

p+
isolation

n+ emitter
p base

n collector

SIDE
VIEW

n+ buried layer
p substrate

p+

p-

n-

ni

n+

Metal

ECE 4430 - Analog Integrated Circuits and Systems

Fig.160-05

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-8

p+ ohmic contact (Mask Step 5)

This step permits ohmic contact to the base region if it is not doped sufficiently high.

TOP
VIEW

p+
isolation

n+

p+

p+
isolation

n+ emitter
p base

n collector

SIDE
VIEW

n+ buried layer
p substrate

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

ni

n-

n+

Metal

Fig.160-06

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-9

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Contact etching (Mask Step 6)

This step opens up the areas in the dielectric area which metal will contact.

TOP
VIEW

Dielectric Layer

p+
isolation

SIDE
VIEW

n+

p+

p+
isolation

n+ emitter

p base

n collector

n+ buried layer
p substrate

p+

p-

n-

ni

n+

Metal

Fig.160-07

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P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-10

Metal deposition and etching (Mask Step 7)

In this step, the metal is deposited over the entire wafer and removed where it is not
wanted.

TOP
VIEW

;;;;;;;;; ;;;;
p+
isolation

SIDE
VIEW

n+

p+

n+ emitter

p base

p+
isolation

n collector

n+ buried layer
p substrate
Fig.160-08

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-11

Passivation (Mask Step 8)

Covering the entire wafer with glass and opening the area over bond pads (which requires
another mask).

TOP
VIEW

;;;;;;;; ;;;;
;;;;;;;;;;;;
;;;;;;;; ;;;;

Passivation

p+
isolation

SIDE
VIEW

p+

n+

p+
isolation

n+ emitter

p base

n collector

n+ buried layer
p substrate
Fig.160-09

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P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-12

Typical Impurity Concentration Profile for the npn BJT

Taken along the line from the surface indicated in the last slide.
p

n+

1020
Substrate Doping Level

1019
1018
Epitaxial
collector
doping level

1017
1016
1015
1014
1013
1012

Emitter

Impurity Concentration (cm-3)

1021 n+

Base Collector

ECE 4430 - Analog Integrated Circuits and Systems

Buried Layer

10

11

Substrate

12

x, Depth from the

surface (microns)
Fig. 160-10

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-13

COMPATIBLE pnp BJTS

Substrate pnp BJT
Collector is always connected to the substrate potential which is the most negative DC
potential.

TOP
VIEW

;;;;;;;;;;;;;;
p+
isolation/
collector

p+
isolation/
collector

p+

n+

p emitter

n base
SIDE
VIEW
p collector/substrate

p
pp+
ECE 4430 - Analog Integrated Circuits and Systems

n-

ni

n+

Metal

Fig.160-11

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-14

Lateral pnp BJT

Collector is not constrained to a fixed dc potential.

TOP
VIEW

;;;;
;;;;;;;;;
p+
isolation

SIDE
VIEW

p+

p+

p collector

p emitter

n+

p+
isolation

n base

n+ buried layer
p substrate

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

ni

n-

n+

Metal

Fig.160-12

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-15

MODIFICATIONS TO THE STANDARD npn TECHNOLOGY

Types of Modifications
1.) Dielectric isolation - Isolation of the transistor from the substrate using an oxide
layer.
2.) Double diffusion - A second, deeper n+ emitter diffusion is used to create JFETs.
3.) Ion implanted JFETs - Use of an ion implantation to create the upper gate of a pchannel JFET
4.) Superbeta transistors - Use of a very thin base width to achieve higher values of F.
5.) Double diffused pnp BJT - Double diffusion is used to build a vertical pnp transistor
whose performance more closely approaches that of the npn BJT.

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-16

ADVANCED BIPOLAR IC TECHNOLOGY

Objective
Newer BJT technologies use polysilicon to form a self-aligned emitter resulting in
higher frequency response capability. These technologies attempt to keep the surface of
the integrated circuit as flat as possible.
Process
1.) Buried layer and epitaxial growth.
SiO2
n--type expitaxial layer

1m

n+

p--type substrate

yy
;;
Gate Ox

Oxide

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

n-

n+

Poly

Salicide Polycide

Metal
040622-03

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-17

Process Continued
2.) Etching of epitaxial layer.
SiO2
n--type expitaxial layer
n+

p--type substrate

yy
;;
Gate Ox

Oxide

p+

p-

n-

n+

Salicide Polycide

Poly

Metal

040622-04

3.) Growth of thick SiO2.

SiO2

n-

SiO2

SiO2

n+

p--type substrate

yy
;;
Gate Ox

Oxide

p+

p-

n-

n+

Salicide Polycide

Poly

Metal

ECE 4430 - Analog Integrated Circuits and Systems

040622-09

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-18

Process Continued
4.) Base diffusion and collector sinker (n+ diffusion)
p- base layer
SiO2

n-

SiO2

n+
SiO2

n+

p--type substrate

yy
;;
Gate Ox

5.)

n+

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal
040622-05

polysilicon emitter
n+ polysilicon emitter
p- base layer
SiO2

n-

SiO2

n+
SiO2

n+

p--type substrate

yy
;;
Gate Ox

Oxide

p+

ECE 4430 - Analog Integrated Circuits and Systems

p-

n-

n+

Poly

Salicide Polycide

Metal

040622-06

P.E. Allen - 2004

Lecture 160A Bipolar Technology (6/22/04)

Page 160-19

Process Continued
6.) p+ base diffusion
n+ polysilicon emitter
p+ base

Diffused n+ emitter
p+ base

SiO2

n-

SiO2

n+
SiO2

n+

p-type substrate

yy
;;
Gate Ox

Oxide

p+

p-

n-

n+

Poly

Salicide Polycide

Metal

040622-07

7.) Metal contacts

Base

Base

Emitter

p+

p+

n-

SiO2

Collector
SiO2

n+
SiO2

n+

p-type substrate

yy
;;
Gate Ox

Oxide

p+

ECE 4430 - Analog Integrated Circuits and Systems

Lecture 160A Bipolar Technology (6/22/04)

p-

n-

n+

Poly

Salicide Polycide

Metal

040622-08

P.E. Allen - 2004

Page 160-20

SUMMARY
The objective has been to give a physical understanding of how the npn BJT is fabricated.
The fabrication sequence for a typical npn BJT has been illustrated
Methods of implementing other active devices in the npn BJT technology were shown.
Simple npn BJT technology chooses to emphasize the npn over the pnp because the npn
BJT performance is always superior to the pnp BJT performance. Thus, the philosophy
in design is to use the npn where ever possible and incorporate the pnp only where it
has to be used.
An advanced BJT technology has been illustrated.
We will examine the passive components that can be implemented in a typical npn BJT
process later.

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2004