HDL LAB MANUAL Electronics & Communication Dept

HDL LAB-10ECL48
VIVA VOCE QUESTIONS
1. Expand VHDL.
2. What is the difference between VHDL and Verilo!
". What is the difference between #i$ sinal and %ariable #ii$ eneric &
&arameter #iii$ function & procedure #i%$ tas' & function #%$ alwa(s &
initial #%i$ reister & %ariable #%ii$ sinal & wire
). What are the different st(les of models in VHDL and Verilo!
*. What are the operators in VHDL & Verilo!
+. Which is an operator is ha%in most priorit(!
,. What is meant b( sensiti%it( list!
-. .i%e the /ollowin s(ntax in HDL #i$ if0 for0 function0 procedure #ii$
while0 case.
1. What is the operatin fre2uenc( of (our /&.3!
14. Expand /&.3 & 356C
11. What are the data t(pes in VHDL!
12. What are the data t(pes in Verilo!
1". What is delta time!
1). What is the difference between # 4 to "$ & # " downto 4$!
1*. Write the truth table & Excitation table for D filp flop0 57 0 80 9:
1+. What are the file operations in Verilo!
1,. What is meant b( s(nthesis!
1-. Write the flow chart for s(nthesis process!
11. What is the difference between combination circuit & se2uential circuit!
24. What is the difference between latch & /lip flop!
21. Write a Verilo code to swap contents of two reisters with and without a
temporar( reister!
22. 6n a pure combinational circuit is it necessar( to mention all the inputs in
sensiti%it( list! 6f (es0 wh(!
2". What is the difference between wire and re!
2). .i%e onl( two xor ates one must function as buffer and another as not
ate!
2*. ;uild a )<1 mux usin onl( 2<1 mux!
2+. What are shift operators in HDL!
2,. What are the loical operators in VHDL & Verilo!
2-. What is the ate densit( of (our /&.3!
21. What is data flow model0 structural model0 beha%ioral model!
"4. How (ou in%o'e from VHDL to Verilo and %ice %ersa!
"1. What is the difference between 57 flip flop & 9: flip flop!
"2. What is the difference between s(nchronous reset & 3s(nchronous reset!
"". What is the difference between stepper motor & DC motor!
"). What is the step si=e of stepper motor!
"*. What is mux and demux!
"+. What is encoder and decoder!
",. What is the difference between encoder & priorit( encoder!
HDL >3?@3L 5a68 1
HDL LAB MANUAL Electronics & Communication Dept
"-. What is bindin!
"1. What is the difference between AbitB and AstdCloicB!
)4. What are the stdCloic %alues!
)1. What are the different t(pes of buffers are in Verilo HDL!
)2. What is the difference between dc motor and stepper motor!
)". What are the applications of dc motor and stepper motor!
)). Write the s(ntax for casex and case=.
)*. What is screen time!
)+. Draw the simulation wa%eform for DDlatch usin sinal assinment and
%ariable assinment statements inside the process.
),. What is 573>!
)-. What is meal( model and >oore model!
)1. What are user defined t(pes!
*4. What are the pac'aes are a%ailable in VHDL! 3nd also i%e the s(ntax
for pac'ae
*1. How to call procedure and function within the process!
*2. .i%e the s(ntax for arra(s in VHDL and Verilo.
*". What are the VHDL file processin!
HDL >3?@3L 5a68 2