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IPASJ International Journal of Computer Science(IIJCS)

Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm


A Publisher for Research Motivation ........ Email: editoriijcs@ipasj.org
Volume 2, Issue 7, July 2014 ISSN 2321-5992



Volume 2 Issue 7 July 2014 Page 12


ABSTRACT
This paper describes the design and implementation of scalable 8-Tap FIR filter on Spartan-3 FPGA. Distributed Arithmetic
approach is used to design low pass FIR filter. Real time implementation was verified using the Xilinx SPARTAN -3
Development Board MXS3FK-5M, which uses XC3S4000/5000 FG900. The results are compared with implementation results
on MATLAB.
Keywords: Distributed Arithmetic, FPGA, FIR Filter, 8-tap LPF
1.INTRODUCTION
VLSI technology advent, gave a fast pace rise to number of applications of integrated circuits in high-performance
computing, tele-communications, and consumer electronics. FIR filters are used in applications that require exact
linear phase response. Typical applications for a FIR filter include: image processing, digital audio, digital
communication, and biomedical signal processing. The paper discusses basic FIR filter theory and the advantage of
implementation using Distribute Arithmetic. Further results of FPGA implementation
2. FILTER DESIGN
The conventional single-rate FIR version of the developed core computes the convolution sum defined as:
y(k) = where k=0,1,2.

where N is the number of filter coefficients.
The conventional tapped delay line realization of this inner-product calculation is shown in Figure 1.

Figure 1 : Conventional Tapped-Delay Line FIR Filter

The direct computation for one point of FIR requires: N multiplications +(N-1) additions. A distributed arithmetic
(DA) realization is employed. This approach employs no explicit multipliers in the design, only look-up tables (LUTs),
shift registers, and a scaling accumulator.
2.1 Filter Design Using DA
Distributed Arithmetic (DA) is a well-known method for eliminating resources in multiply-and-accumulate structures
(MACs) implementing digital signal processing (DSP) functions. DA trades memory for combinatory elements,
resulting in an efficient implementation in FPGAs. Another feature of DA is its easy serialization of the input, which
further reduces the cost of operation when FIR data rate is low compared to the system clock, a common scenario in
FIR applications.The input of a FIR can be expressed in the composition of its bits, as shown in
X[n] =
where x[n][b] is the bth bit of x[n] and n-bits in is the number of bits of input. The resulting output of the FIR filter as
y[n]=
Changing the summation order gives the results shown in
y[n] =
FIR Filter Design on Chip Using VHDL
Mrs.Vidya H. Deshmukh, Dr.Abhilasha Mishra, Prof.Dr.Mrs.A.S.Bhalchandra
MIT College of Engineering, Aurangabad
IPASJ International Journal of Computer Science(IIJCS)
Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm
A Publisher for Research Motivation ........ Email: editoriijcs@ipasj.org
Volume 2, Issue 7, July 2014 ISSN 2321-5992



Volume 2 Issue 7 July 2014 Page 13


=
= (4)
where: and X[b] is a collection of the bth bits of n-taps different taps
There are 2ntaps different values of T. If T is pre-calculated and stored inside a RAM or ROM, the FIR computation
becomes n-bits in table lookup operations using x[b] and (nbits_in1) additions. Multiplication operations are
eliminated. So the FIR computation using DA for one point of FIR requires Nbits_in table lookups +(nbits_in-1)
additions The cost to eliminate multiplication is a memory block to store 2ntaps pre-computed values. The serialization
of table lookup and addition is possible because table T is the same for each b. If one table lookup and one addition can
be finished in one cycle, the total computation will finish in b cycles. The serialization of the FIR introduces further
opportunity to reduce the size of the design, which is the key to an efficient FPGA design. Let n-taps =p q. If we split
taps into p groups, each group has q taps. Then the FIR becomes as shown as
y(n) =
=
By splitting n-taps into two level summations, we have the result
y(n) =
This provides a efficient way to implement on FPGA by utilizing the built-in RAM , Look-up Table and suitable
pipeling structure.
3. IMPLEMENTATION OF FIR FILTER ON FPGA
The functional block diagram is as shown below

Figure 2.1: Functional Block of FIR Filter
4-tap FIR Filter Using DA with four taps (ntaps =4) and four bits for inputs (nbits_in =4) is shown in Figure 2.2
Figure 2.2: 4-Tap Fir Filter Using DA In the first cycle, all 0th bits of input x[n] to x[n-3] are fed into the lookup table
as an input address; in the second cycle, all 1st bits of inputs input x[n] to x[n-3] are fed into the lookup table; in the
third cycle, all 2nd bits of inputs input x[n] to x[n-3] are fed into the lookup table; and in the fourth cycle, all 3rd bits of
inputs input x[n] to x[n-3] are fed into the lookup table. The shifter shifts the outputs of the lookup table for the inputs
of the adder, which accumulates for the final result. The split lookup table implementation of a FIR with eight taps
(ntaps =8) and four bits for inputs (nbits_in =4) is shown in Figure 2.3. The eight taps have been split into two
groups. Each has four taps, and each group addresses separate lookup tables. The system clock rate of many FIR filter
systems is a multiple of the data rate (or data sampling rate). For typical FPGA implementation, the size of the design
is key for efficient implementation. Thus, exploitation of the ratio between the system clock rate and data rate is an
effective approach to reduce the size of the design.


IPASJ International Journal of Computer Science(IIJCS)
Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm
A Publisher for Research Motivation ........ Email: editoriijcs@ipasj.org
Volume 2, Issue 7, July 2014 ISSN 2321-5992



Volume 2 Issue 7 July 2014 Page 14
















Figure 2.3: Split Lookup Table Implementation for 8-tap FIR Filter

In other words, folding or serialization of the computation can reduce the size of the design. The DA algorithm for FIR
introduces bit-serialization of the operations. This property of the DA can be very efficient for exploring the ratio
between system clock rate and data rate. If the number of bits of input is nbits_in, it takes nbits_in table lookup and
additions to finish one output point of the FIR. If the system clock rate is nbits_in times faster than data rate, the
serialization of table lookup and additions is done with the optimized timing. The parameter sample_ratio defines the
ratio between the system clock rate (sys_clk_frq) and the data sampling rate (data_rate), as shown in sample ratio is
ratio of sys_clk_frquency and data_rate.
3.1Filter Coefficients Calculations
LPF FIR using Kaiser Windowing technique is evaluated on the developed system. The Kaiser window equation is
given by:


Kaiser Window Coeff
KCoff
Fixed Point Coeff
(KCoff*2
16
)
0.00006103 4
0.00022888 15
0.00038146 25
0.0004730 31
0.00006103 31
0.00022888 25
0.00038146 15
0.0004730 4

4.RESULTS
1. Simulation window
2. Synthesis report(area utilization) +timing analysis
3. MAtlab comprasion
When we compare fir filter in Mathlab and VHDL we get following results.


IPASJ International Journal of Computer Science(IIJCS)
Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm
A Publisher for Research Motivation ........ Email: editoriijcs@ipasj.org
Volume 2, Issue 7, July 2014 ISSN 2321-5992



Volume 2 Issue 7 July 2014 Page 15







5. CONCLUSIONS
Here we design lowpass fir filter using VHDL which is able to attenuate frequency higher than 4 Khz. The high sample
rate (8000 per second) and the ability to change many characteristics of the design including the number of taps makes
this FIR filter a versatile macro with a diverse range of DSP applications. we get fast response of filter on targeted
device in 9sec by using xilline impact tool.
FIR filter using VHDL which provides a wide range of programmable logic that can be used to develop high
performance DSP products. The XC4000 family of Field Programmable Gate Arrays (FPGAs) offers designers a
diverse selection of functionality to build almost any system design. The FPGA can adapt to last minute design
modifications as well as future design iterations without making extensive hardware or software modifications.
Distributed Arithmetic (DA) Algorithm provides Multiplier-Free Computation, Low Cost, Optimized for Actel,
FPGAs. also provide Folding Architecture to Minimize Design Size, Serialized Computation when System
Clock,Rate is Faster than the Data Sample Rate.
Efficient Structure Using Embedded RAMs.
Actel and FPGA-Optimized RTL Code.
On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs
1. Embedded RAMs Initialized as DA Lookup Table
2. DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs
3. Multiple DA lookup Tables to Split Large Number of Taps
This code Supports 2 to 128 Taps fir filter.
FIR filter have 1- to 32-Bit Input Data and Coefficient Precision
Application of the ASIC Fir Filter Chip
Could be used as an integral filter unit of system on board designs.
Could be used to design filter banks.
Its configurability makes it a very good option for high end designs.
Since 8 tap fir filter are commonly used in industrial applications, design would come in handy in tailor made
situations.
It can be use as high performance DSP product.
IPASJ International Journal of Computer Science(IIJCS)
Web Site: http://www.ipasj.org/IIJCS/IIJCS.htm
A Publisher for Research Motivation ........ Email: editoriijcs@ipasj.org
Volume 2, Issue 7, July 2014 ISSN 2321-5992



Volume 2 Issue 7 July 2014 Page 16


REFERENCES
[1] www.dsprelated.com/3.fir-digital-fir-design.html
[2] htttp://www.doulos.com/knoweldge/vhdl-designer-guide-design-flow-using vhdl/
[3] http://www.ultraforom.com/.forom/showthread.php=6606
[4] htttp://www.model.com/content/modelsem-pe-simulation-and debug
[5] Digital Signal Processing by N.G. Palan pp.315-375.
[6] Digital Signal Processing by Mitra pp. 432-471.
[7] Digital Signal Processing by Shalivahanan Vallavaraj Gnanapriya, Appendix .
[8] Digital Signal Processing by Proakis Manolakis pp. 230-241.[9]htttp://en.wikipedia.org/wiki/Kaiser window
[10] VHDLPrimer Bhaskar pp.110-121.
[11] VHDL Analysis and Modeling of Digital System by Zainalabedln Navabl pp. 550-583.
[12] VHDL Design Technique for Analog and Digital Circuit by Randall L.Geiger pp. 212-215.
[13] VHDL Programming by Example by Douglas L. Perry pp.225-227