Yr/Dept: II CSE

Lect.No Unit No Topics to be covered Text Page No Week

1 I Eight ideas T1 11 w1
2 I Components of a computer system T1/R1/R2 13//03//1966 w1
2 I Technology T1 24 w1
3,4 I Performance T1/R1/R2 28/13/50 w1
5 I Power wall T1 40 w1
5 I Uniprocessors to multiprocessors T1/R1 43/18 w1
6 I Instructions T1/R1/R2 62/37/400 w2
6 I Operations & operands T1/R1/R2 63/27/348 w2
7 I Representing instructions T1/R1/R2 80/38/349 w2
7 I Logical operations T1/R2 87/362 w2
8 I control operations T1/R1/R2 90/44/362 w2
9,10 I Addressing and addressing modes T1/R1/R2 111/48/401 w2
11 II ALU T1/R2/R5 178/306/252 w3
11 II Addition and subtraction T1/R1/R2/R4/R6 178/368/312/177 w3
12,13 II Multiplication T1/R1/R2/R6 183/376/317 w3
14,15 II Division T1/R1/R2/R6 189/390/324 w3
16,17 II Floating Point operations T1/R1/R2/R6 196/393/334 w4
18 II Subword parallelism T1 222 w4
20,21 III Basic MIPS implementation T1 244 w4
22,23 III Building datapath T1/R1/R3/R5 251/479/147/223 w5
24,25 III Control Implementation scheme T1/R1 259/479 w5
26 III Pipelining T1/R1/R2 272/453 w5
27,28 III Pipelined datapath and control T1/R4 286/684 w6
29 III Handling Data hazards & Control hazards T1/R1 303/461 w6
30 III Exceptions T1 325 w6
31,32 IV Instruction-level-parallelism T1/R2/R3 332/444/280 w7
33,34 IV Parallel processing challenges T1 504 w7
35,36 IV Flynn's classification T1/R2 509/630 w7
37,38 IV Hardware multithreading T1/R2 516/646 w8
39 IV Multicore processors T1/R2 519/684 w8
40 V Memory hierarchy T1/R1 374/292 w8
41 V Memory technologies T1/R2 378/158 w8
42,43 V Cache basics T1/R1/R2 383/314/110 w9
44,45 V Measuring and improving cache T1/R1/R2 398/329/121 w9
46 V Virtual memory, TLBs T1/R1/R2 427/337/283 w9
47 V
Input/output system, programmed I/O,
DMA and interrupts R1/R2/R3 234,208/217,473 w10
48 V I/O processors R2/R3 242/474 w10
Staff in charge HOD Principal
5. John P. Hayes, Computer Architecture and Organization, Third Edition, Tata Mc Graw Hill,1998.
6. http://nptel.ac.in/.
UNIT V MEMORY AND I/O SYSTEMS
SMTEC/ DEPT/14-15/ODD/CP/REV 01
St.MOTHER THERESA ENGINEERING COLLEGE, THOOTHUKUDI, VAGAIKULAM - 628102
Staff Name : J. AVINASH DHANDAPANI
Subject Code/Name : CS6303 COMPUTER ARCHITECTURE
Date: 08/07/14
Text Books:
1.David A. Patterson and John L. Hennessey, Computer organization and design, Morgan Kauffman / Elsevier, Fifth edition, 2014.
1. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, Computer Organisation, Sixth edition, Mc Graw-Hill Inc, 2012.
UNIT II ARITHMETIC OPERATIONS
Reference Books:
UNIT I OVERVIEW & INSTRUCTIONS
UNIT III PROCESSOR AND CONTROL UNIT
UNIT IV PARALLELISM
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING
COURSE PLAN
4. Govindarajalu, Computer Architecture and Organization, Design Principles and Applications", Second edition, Tata McGraw Hill, New Delhi, 2010.
2. William Stallings Computer Organization and Architecture , Seventh Edition , Pearson Education, 2006.
3. Vincent P. Heuring, Harry F. Jordan, Computer System Architecture, Second Edition, Pearson Education, 2005.