International Journal of Electronics Engineering & Applications, Vol.

III, Issue III

A Single Source Cascaded Multilevel Inverter
Poornima D
1
, Bharath Kumar M R
2
, Andrew Mathew Domnic F
3
1
Assistant Professor, Nehru institute of Engineering & Techonology, Coimbatore, Tamilnadu.
2
Pre final year, Nehru institute of Engineering & Techonology, Coimbatore, Tamilnadu.
3
Pre final year, Nehru institute of Engineering & Techonology, Coimbatore, Tamilnadu.
Email: dpoornima@gmail.com , mrbharathee@gmail.com , andrew.mdeee@gmail.com
Abstract:
The power rating at industrial equipment is constantly hiking. Now it is reached to the megawatt level,
corresponding to the medium-voltage (2.3, 3.3, 4.!, or !." k#$ network. %t is hard to connect a single
power semiconductor switch directly to medium voltage grids. &or this, multilevel inverters have
emerged as the solution 'or working with higher voltage levels. &or applications with voltage higher than
!k#, cascaded ( )ridge multilevel inverters are commonly used. To generate separated voltage sources a
multi-phase trans'ormer is usually applied to generate these *+ sources 'rom a three phase ,+ power
source. The input current o' inverter cells with speci'ic phase shi't due to multi-phase trans'ormer can
lower the high 'requency harmonics, mass secondary wires and connection will de'initely not only
increase the si-e and weight o' the equipment, )ut also complicate the wiring. %n order to overcome all
these draw)acks, a new cascaded multilevel inverter is proposed. The new topology has a modular
structure like (-)ridge topology and is easy to )e e.tended to higher level. /roposed topology can greatly
simpli'y the system wiring, 0ust requiring very low space. 1ach cell ((-)ridge cell$ can )e regarded as
containing a )oost converter, a low capacitance *+ capacitor and a hal' )ridge inverter. 2,T3,4
simulations are also included to veri'y the per'ormance and 'unctioning o' the proposed system along
with a hardware design.
Keywords: Hbridge cell, multilevel inverters, boost converter, hal! bridge inverter, harmonics,
multiphase trans!ormer, "C capacitor.
[1 !"#R$D%&#!$"
A multiphase trans!ormer is used to generate separated voltage sources
!rom a three phase AC suppl#. $or applications greater than %&' H ( )ridge
inverters are used but in this case, lots o! isolated voltage sources are needed. *he
concept o! utili+ing multilevel voltages was !ounded around thirt# #ears ago
,-./.Advantages o! this was good 0ualit# o! power, low switching losses, high
voltage capabilit# and good electromagnetic compatibilit#. *he main
disadvantages o! this techni0ue are that a larger number o! switching
semiconductors are re0uired !or lowervoltage s#stems and the small voltage steps
must be supplied on the dc side either b# a capacitor ban& or isolated voltage
sources. *he !irst topolog# introduced was the series Hbridge design ,-/. *his was
!ollowed b# the diode clamped ,12/ converter which utili+ed a ban& o! series
22
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
capacitors. A later invention ,3/ detailed the !l#ing capacitor design in which the
capacitors were !loating rather than seriesconnected. Another multilevel design
involves parallel connection o! inverter phases through interphase reactors ,%/. In
this design, the semiconductors bloc& the entire dc voltage, but share the load
current. Several combinational designs have also emerged ,4/ some involving
cascading the !undamental topologies ,5-1/. *hese designs can create higher
power 0ualit# !or a given number o! semiconductor devices. *his is possible due to
the multipl#ing e!!ect o! the di!!erent voltage levels.
[2 &A'&AD(D )*BR!D+('
A singlephase structure o! an mlevel cascaded inverter is illustrated in
[Fi,ure 1- Each separate dc source 6!C7 is connected to a singlephase !ull
bridge, or Hbridge, inverter ,-2-3/. Each inverter level can generate three
di!!erent voltage outputs, 8'
dc
, 9, and ('
dc
b# connecting the dc source to the ac
output b# di!!erent combinations o! the !our switches, S
-
, S
1
, S
.
, and S
2
. *o obtain
8'
dc
, switches S
-
and S
2
are turned on, whereas ('
dc
can be obtained b# turning on
switches S
1
and S
.
. )# turning on S
-
and S
1
or S
.
and S
2
, the output voltage is 9. *he
ac outputs o! each o! the di!!erent !ullbridge inverter levels are connected in series
such that the s#nthesi+ed voltage wave!orm is the sum o! the inverter outputs. *he
number o! output phase voltage levels m in a cascade inverter is de!ined b# m :
1s8-, where s is the number o! separate dc sources. An e;ample phase voltage
wave!orm !or an --level cascaded Hbridge inverter with 3 S"CSs and 3 !ull
bridges is shown in [Fi,ure 2. *he phase voltage
v
an
: v
a-
8 v
a1
8 v
a.
8 v
a2
8 v
a3
<<<.6-7
$or a stepped wave!orm such as the one depicted in [Fi,ure . with 3 steps, the
$ourier *rans!orm !or this wave!orm !ollows:
' 6=t7 : '
dc
> ,cos 6n?
-
7

8 cos 6n?
1
7 8<<..8 cos 6n?
s
7/ sin 6n=t7,@here n : -,
., 3, 4<<<<<.617
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International Journal of Electronics Engineering & Applications, Vol. III, Issue III
Fi,ure1- 'in,/e*0hase structure o1 a mu/ti/e2e/ cascaded )*brid,es in2erter-
Fi,ure-2- $ut0ut 0hase 2o/ta,e wa2e1orm o1 an 11*/e2e/ cascade in2erter
$rom 6-7, the magnitudes o! the $ourier coe!!icients when normali+ed with respect
to '
dc
are as !ollows:
H 6n7 : ,cos 6n?
-
7

8 cos 6n?
1
7 8<<. 8 cos 6n?
s
7/, @here n : -, ., 3, 4 ... 6.7
*he conducting angles, ?
-
, ?
1
... ?
s
, can be chosen such that the voltage total
harmonic distortion is a minimum. Aenerall#, these angles are chosen so that
24
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
predominant lower !re0uenc# harmonics, 3
th
, 4
th
, --
th
, and -.
th
, harmonics are
eliminated.
[3 &!R&%!# D!A+RAM
*he below given is the circuit diagram o! the inverter.each inverter cell is
cascaded with the other and the output is connected to the motor load.
Fi,ure 3: &ircuit Dia,ram o1 the in2erter
[Fi,ure-3- shows a circuit diagram o! the multilevel inverter. *he model output
voltage wave!orm o! ninelevel cascaded multilevel inverter is shown in the
[Fi,ure .-
Fi,ure .- Mode/ out0ut 2o/ta,e o1 the in2erter
25
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
*he ma;imum output phase voltage is given as 13' pp. *he steps to s#nthesi+e
the ninelevel voltage wave!orms are as !ollows.
-. $or an output voltage level '9 : 9, no switch in the Hbridges are turned on.
1. $or an output voltage level '9 : .', turn on the switches S-, S1, S5, S-1, S-%.
.. $or an output voltage '9 : %', turn on all the switches as mentioned in step 1
and S4.
2. $or an output voltage level '9 : B', turn on all the switches in the step . and
S--.
3. $or an output voltage level '9 : -1', turn on all the switches in the step . and
S-3. Condition - means the switch is on and 9 means the switch is o!!. Each
switch is turned on onl# once per c#cle and there!ore reduces switching losses.
[. ('#!MA#!$" $F '3!#&)!"+ A"+4('
$ourier series o! the 0uarterwave s#mmetric S H bridge multilevel inverter
output wave!orm is written as given in e0uation 617 in which ?
s
are the optimi+ed
switching angles, which must satis!# the !ollowing condition
?
-
C ?
1
C D D D C ?
S
C EF1<<<.. 627
*he method to solve the optimi+ed harmonic switching angles will be e;plained in
this section. $rom e0uation 6-7, the harmonic components in the wave!orm can
described as !ollows:
-. *he amplitude o! dc component e0uals +ero.
1. *he amplitude o! all odd harmonic components including !undamental one, are
given b#
H 6n7 : 637
.. *he amplitude o! all even harmonics e0ual +ero. *hus, onl# the odd harmonics
in the 0uarterwave s#mmetric multilevel wave!orm need to be eliminated. *he
switching angles o! the wave!orm will be adGusted to get the lowest *H" in the
output voltage
H6n7: ,cos6n?
-
7

8 cos6n?
1
78 cos6n?
.
7 8 cos6n?
2
7/ ,6%7
I! needed to control the pea& value o! the output voltage to be '- and eliminate the
!i!th and seventh order harmonics, the modulation inde; is given b# M : E'-F2'
dc
the resulting harmonic e0uations are
,cos 6?
-
7

8 cos6?
1
78 cos6?
.
7 8 cos6?
2
7/: '
-
647
,cos 63?
-
7

8 cos63?
1
78 cos63?
.
7 8 cos63?
2
7/ : 9 657
,cos 64?
-
7

8 cos64?
1
78 cos64?
.
7 8 cos64?
2
7/ : 9 6B7
And the !irst e0uation can be rewritten as
,cos6?
-
7

8 cos6?
1
78 cos6?
.
7 8 cos6?
2
7/ : M 6-97
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International Journal of Electronics Engineering & Applications, Vol. III, Issue III
Each Hbridge inverter unit has a conduction angle which is calculated to
minimi+e the harmonic components. *he conduction angles are the !actors
determining the amplitude o! the harmonic components. In nine level inverter !our
dc sources are needed so that the dc voltage levels are chosen so as not to generate
the !i!th and seventh order harmonics while achieving the desired !undamental
voltage. *his is a s#stem o! three simultaneous e0uations with !our un&nownsH ?-,
?1, ?. and ?2. *hese values are !ound b# solving the simultaneous e0uations 6"#
$7.
Fi,ure-5- A 0u/se wa2e, showin, the de1initions o1 ymin, yma. and D-
Iulsewidth modulation uses a rectangular pulse wave whose pulse width is
modulated resulting in the variation o! the average value o! the wave!orm as
shown in the !ig 3. I! we consider a pulse wave!orm f6t7 with a low value y
min
, a
high value y
ma%
and a dut# c#cle " 6see 1i,ure 17, the average value o! the
wave!orm is given b#:
# : 6--7
As f6t7 is a pulse wave, its value is y
ma%
!or 9 C t C " .* and y
min
!or ".* C t C * .
*he above e;pression then becomes:
# :
:
: ". #
ma;
8 6- "7 #
min
6-17
*his latter e;pression can be !airl# simpli!ied in man# cases where y
min
: 9 as # :
". #
ma;.
$rom this, it is obvious that the average value o! the signal 6#7 is directl#
dependent on the dut# c#cle ".
27
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
Fi,ure 6: A sim0/e method to ,enerate the P3M 0u/se train
*he simplest wa# to generate a I@M signal is the interceptive method,
which re0uires onl# a saw tooth or a triangle wave!orm 6easil# generated using a
simple oscillator7 and a comparator. @hen the value o! the re!erence signal 6the
red sine wave in 1i,ure 77 is more than the modulation wave!orm 6blue7, the I@M
signal 6magenta7 is in the high state, otherwise it is in the low state corresponding
to a given signal intersective I@M: the signal 6here the red sine wave7 is
compared with a saw tooth wave!orm 6blue7. @hen the latter is less than the
!ormer, the I@M signal 6magenta7 is in high state 6-7. Jtherwise it is in the low
state 697 as show on [Fi,ure-6.
[53$RK!"+ A"D $P(RA#!$"
*he load is an AC motor o! induction motor with o! -3watts, 1.9', 39H+.
A 2 Hbridge inverter cells are used. *hese also act as a boost converter. Jne
aspect which sets the cascaded Hbridge apart !rom other multilevel inverters is the
capabilit# o! utili+ing di!!erent "C voltages on the individual Hbridge cells which
results in splitting the power conversion amongst highervoltage lower!re0uenc#
and lowervoltage higher!re0uenc# inverters. A protot#pe o! nine level cascaded
multilevel inverter has been !abricated and tested. *he switching signals !or the
model are generated !rom A* mega 5microcontroller. *he voltages to the
components are regulated using 4593 IC. *he driver circuits are also used to give
pulse !or switches in the power circuit. *he power circuit is isolated b# using opto
coupler circuit 6MC.91.KIC5-47. Jptocouplers also &nown as optoisolators
provide optical isolation and coupling between control circuit and power circuit,
creating ph#sical and electrical isolation signal coupling between them.
Jptocouplers which can be assembled using traditional semiconductor pac&ages
28
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
contain a light emitting diode and photo sensitive semiconductor devices in the
same housing.
[5-1B4$&K D!A+RAM
Fi,ure 7: B/oc8 Dia,ram o1 cascaded mu/ti/e2e/ in2erter with sin,/e D& source
[5-2 B4$&K D!A+RAM D('&R!P#!$"
An AC suppl# voltage 1.9' 39H+ is given as the input suppl#. *his suppl#, with
the help o! proper recti!ication is given to all the components. Here, a $ull wave
recti!iers and bridge recti!iers are used !or recti!#ing the AC suppl# voltage to
obtain "C. *he nine level cascade multilevel inverter consists o! 2 Hbridge
inverters. *otall# -% switches are used. IL$329 MJS$E*Hs are used as switches.
Along with this a 1.9 3', 39H+, -99mA, pulse trans!ormer is used to produce the
re!erence wave!orm !or the controller.
[6 (9P(R!M("#A4 R('%4#'
Fi,ure :: +ate Pu/se 3a2e1orm
29
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
Fi,ure ;: $ut0ut 3a2e1orm o1 in2erter
[7 )ARD3AR( D('!+"
Fi,ure-1<- )ardware circuit
*he above [Fi,ure-1< shows the hardware circuit o! the inverter. $our H bridge
inverters are used !or a single phase. A total o! -% switches are used. A B level
inverter has been modeled. A low power induction motor has been used as the
load. *his is the circuit o! a single inverter bridge. $our IA)* switches are used to
obtain the output voltage. *he voltage depends on the switching times o! the
IA)*. *here is a charging capacitor C and a source resistance L. the output is
ta&en !rom 1 to cascade it with the ne;t inverter bridge. *his is the circuit o! the
pulse generator !or a single phase. A sine wave o! 39 H+ is compared with a
pulsating "C o! 39 H+ and i! the result is positive output is one and i! negative the
30
International Journal of Electronics Engineering & Applications, Vol. III, Issue III
output is +ero. *he microcontroller has been programmed to produce the correct
phase shi!ted gate pulses.
[: &$"&4%'!$"
*his proGect presents an important change in the cascaded multilevel inverters b#
using a single source. Iroposed circuit dispenses with masses o! isolated "C
voltage sources which are re0uired in conventional cascaded inverters. Simulation
had been done !or . phases in phase I o! the proGect and the hardware !or a single
phase has been developed in the second phase. *his can be used in voltage
regulation, audio e!!ects and ampli!ications, *elecommunication and power
deliver#.
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International Journal of Electronics Engineering & Applications, Vol. III, Issue III
R(F(R("&('
[1] Masa&a+u Muneshima, Hui Mhang, Shohei *o&unaga,Shota Nrushibata, *a&ashi Oodama, and
Masa&atsu Pomura:Q A Pew )oost *#pe Cascaded Inverter @ith Single "C SourceQ, 5th
International Con!erence on Iower Electronics ECCE Asia,pp.-4-B-413 619--7
[2] Maruthu Iandi Ierumal,"evaraGan PanGudapan: RIer!ormance Enhancement J! Embedded
S#stem )ased Multilevel Inverter Nsing Aenetic AlgorithmQ, Sournal J! Electrical Engineering,
'ol. %1, Po. 2, 19--, -B9(-B5
,./ S. @en, and O. M. Smedle#: RS#nthesis o! Multilevel Converters )ased on Singleand or *hree
Ihase Converter )uilding )loc&sT, IEEE *rans. Iower. Electron. 'ol.1., Po.., pp.-124-13%
619957.
,2/ I. @. Hammond: TA new Approach to enhance Iower Uualit# !or Medium 'oltage AC "rivesT,
IEEE *rans. Ind. Appl., 'ol..., Po.-, pp.191195 6-BB47
,3/ A. Pabae, I. *a&ahashi, and H. A&agi: TA Pew Peutral IointClamped I@M Inverter, and
Applications T, IEEE *rans. Ind. Appl., 'ol.-A-4, Po.3, pp.3-531. 6-B5-7
,%/ S. Lodrigue+, S. Vai, and $. M. Ieng: TMultilevel Inverters: A Surve# o! *opologies, Controls, and
Applications T, IEEE *rans. Ind. Appl., 'ol.2B, Po.2, pp.4124.5 619917
[7] $. M. Ieng, @. Uian and ". Cao: RLecent Advances in Multilevel ConverterFInverter *opologies
and ApplicationsT, *he 19-9 International Iower Electronics Con!erence, pp.2B139-.
,5/ $. M. Ieng: TA Aenerali+ed Multilevel Inverter *opolog# with Sel! 'oltage )alancingT, IEEE
*rans. Ind. Appl., 'ol..4, Po.1, pp.%--%-5 6199-7.
,B/ O. @APA, W. Vi and M. Mheng : T A new trans!ormerless cascaded multilevel converter topolog#
T, ECCE 199B, pp..-12.-1B 6199B7.
,-9/ C. @APA and W. Vi : T A Surve# on *opologies o! Multilevel Converters and Stud# o! *wo
Povel *opologies T, IIEMC 199B, pp.5%95%3 6199B7.
,--/ W.Suresh and A.O.Ianda:QIer!ormance o! cascade multilevel H bridge inverter with single "C
source b# emplo#ing low !re0uenc# three phase trans!ormers.Q *he 19-9 International Iower
Electronics Con!erence, pp.2B339..
,-1/ Oeith A, Mi&e @. @ielebs&i, $ang M. Ieng,QControl o! cascaded multilevel invertersQ, IEEE
*rans.Iower Electronics, Ma# 1992.pp4.14.5
[13] RMultilevel Iower ConvertersQ Surin Ohom!oi and Veon M. *olbert ,*he Nniversit# o!
*ennessee pp .12.39
[14] RIower ElectronicsQ I.S. )himbra, 1nd Edition, Ohanna Iublishers.pp12B1%1
[15] RIower Electronics, Circuits "evices and ApplicationsQ, Muhammad H.Lashid,*hird
Edition, AcademicIresspp2-2213
32