En - ku990r Svc Eng - 080611 Не Нужные Водяные Знаки

Date: June, 2008 / Issue 1.
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Service Manual
KU990R
Internal Use Only
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1. INTRODUCTION.................................. 5
1.1 Purpose ...................................................... 5
1.2 Regulatory Information ............................... 5
2. PERFORMANCE..................................7
2.1 System Overview.........................................7
2.2 Usable environment .....................................8
2.3 Radio Performance......................................8
2.4 Current Consumption.................................16
2.5 RSSI BAR..................................................17
2.6 Battery BAR...............................................17
2.7 Sound Pressure Level ...............................18
2.8 Charging ....................................................18
3. TECHNICAL BRIEF............................19
3.1 General Description...................................19
3.2 GSM Mode.................................................21
3.3 UMTS Mode...............................................25
3.4 LO generation and distribution circuits ......27
3.5 Off-chip RF Components...........................27
3.6 Digital Baseband (DBB/MSM6280) ...........37
3.7 Subsystem(MSM6280) ..............................40
3.8 Power Block...............................................48
3.9 External memory interface.........................53
3.10 H/W Sub System .....................................55
3.11 Feature List ..............................................72
3.12 Multimedia Chip Interface........................78
3.13 Touch Screen Interface ...........................86
3.14 Lens Cover Detection Interface ...............87
3.15 Main Features..........................................88
4. TROUBLE SHOOTING.......................95
4.1 RF Component ..........................................95
4.2 SIGNAL PATH...........................................96
4.3 Checking VCTCXO Block..........................98
4.4 Checking Front-End Module Block ..........100
4.5 Checking UMTS Block.............................103
4.6 Checking GSM Block...............................108
4.7 Power on trouble......................................114
4.8 SIM detect trouble....................................119
4.9 Key sense trouble ( KEYPAD ) ................120
4.10 Keypad backlight trouble .......................122
4.11 Micro SD trouble....................................124
4.12 Audio trouble..........................................125
4.13 Camera trouble......................................138
4.14 Main LCD trouble...................................144
4.15 Bluetooth trouble....................................147
4.16 Bluetooth RF Test ..................................148
4.17 Touch Screen trouble ............................149
4.18 Lens cover detection trouble..................150
5. DOWNLOAD.....................................151
5.1 Introduction..............................................151
5.2 Downloading Procedure ..........................151
5.3 Troubleshooting Download Errors ..........164
5.4 Caution ....................................................169
6. BLOCK DIAGRAM ...........................170
6.1 GSM & UMTS RF Block ..........................170
6.2 Interface Diagram....................................172
7. CIRCUIT DIAGRAM..........................175
8. BGA IC PIN MAP..............................185
9. PCB LAYOUT ...................................193
10. Calibration......................................197
10.1 Usage of Hot-Kimchi ..............................197
11. EXPLODED VIEW & REPLACEMENT
PART LIST ..................................... 201
11.1 EXPLODED VIEW................................ 201
11.2 Replacement Parts
<Mechanic component> ....................... 203
<Main component>............................... 206
11.3 Accessory ............................................. 224
Table Of Contents
LGE Internal Use Only Copyright 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
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1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your companys employees, agents, subcontractors, or person working on your
companys behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system.
There are may be risks of toll fraud associated with your telecommunications system. System users
are responsible for programming and configuring the equipment to prevent unauthorized use. The
manufacturer does not warrant that this product is immune from the above case but will prevent
unauthorized use of commoncarrier telecommunication service of facilities accessed through or
connected to it. The manufacturer will not be responsible for any charges that result from such
unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the phones or compatibility with the net
work, the telephone company is required to give advanced written notice to the user, allowing the user
to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
1. INTRODUCTION
1. INTRODUCTION
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
A phone may interfere with sensitive laboratory equipment, medical equipment, etc. Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
Service personnel should ground themselves by using a wrist strap when exchange system boards.
When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
Use a suitable, grounded soldering iron.
Keep sensitive parts in these protective packages until these are used.
When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
1. INTRODUCTION
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2. PERFORMANCE
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2.1 System Overview
2. PERFORMANCE
Item Specification
Shape GSM900/1800/1900 and WCDMA2100 - Bar type Handset
Size 103.5 X 54.4 X 14.8 mm
Weight Under 112 g (with 1000mAh Battery)
Power 3.7 V normal, 1000 mAh Li-Ion
Talk Time Over 170 min (WCDMA, Tx=10 dBm, Voice)
with 1000mAh) Over 200 min (GSM, Max Tx-29dBm, Voice)
Standby Time Over 250 Hrs (WCDMA, DRX=1.28)
(with 1000mAh) Over 250 Hrs (GSM, Paging period=5)
Antenna Internal type
LCD Main 3 TFT, WQVGA, 262K
LCD Backlight White LED Back Light
Camera 5.0 Mega pixel + VGA Video Call Camera
Vibrator Yes (Coin Type)
LED Indicator No
MIC Yes
Receiver Yes
Earphone Jack Yes (18 pin)
Connectivity Bluetooth, USB
External Memory Yes(Micro SD)
I/O Connect 18 Pin
2.2 Usable environment
1) Environment
2) Environment (Accessory)
* CLA : 12 ~ 24 V(DC)
2.3 Radio Performance
1) Transmitter - GSM Mode
* In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910
2. PERFORMANCE
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Item Specification
Voltage 3.7 V(Typ), 3.2 V(Min), [Shut Down : 3.2 V]
Operation Temp -20 ~ +60C
Storage Temp -30 ~ +80C
Humidity 85 % (Max)
Reference Spec. Min Typ. Max Unit
TA Power Available power 100 220 240 Vac
No Item GSM DCS & PCS
100k~1GHz -39dBm
9k ~ 1GHz -39dBm
MS allocated 1G~[A]MHz -33dBm
Channel
1G~12.75GHz -33dBm
[A]M~[B]MHz -39dBm
Conducted [B]M~12.75GHz -33dBm
1 Spurious 100k~880MHz -60dBm 100k~880MHz -60dBm
Emission 880M~915MHz -62dBm 880M~915MHz -62dBm
Idle Mode
915M~1GHz -60dBm 915M~1GHz -60dBm
1G~[A]MHz -50dBm 1G~[A]MHz -50dBm
[A]M~[B]MHz -56dBm [A]M~[B]MHz -56dBm
[B]M~12.5GHz -50dBm [B]M~12.5GHz -50dBm
2. PERFORMANCE
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** In case of DCS : [A] -> 1710, [B] -> 1785 * In case of PCS : [A] -> 1850, [B] -> 1910
30M ~ 1GHz -36dBm
30M~1GHz -36dBm
MS allocated 1G~[A]MHz -30dBm
Channel
1G ~ 4GHz -30dBm
[A]M~[B]MHz -36dBm
Radiated [B]M~4GHz -30dBm
2 Spurious 30M ~ 880MHz -57dBm 30M~880MHz -57dBm
Emission 880M ~ 915MHz -59dBm 880M~915MHz -59dBm
Idle Mode
915M~1GHz -57dBm 915M~1GHz -57dBm
1G~[A]MHz -47dBm 1G~[A]MHz -47dBm
[A]M~[B]MHz -53dBm [A]M~[B]MHz -53dBm
[B]M~4GHz -47dBm [B]M~4GHz -47dBm
3 Frequency Error 0.1ppm 0.1ppm
4 Phase Error
5(RMS) 5(RMS)
20(PEAK) 20(PEAK)
3dB below reference sensitivity 3dB below reference sensitivity
Frequency Error RA250 : 200Hz RA250: 250Hz
5 Under Multipath and HT100 : 100Hz HT100: 250Hz
Interference Condition TU50 : 100Hz TU50: 150Hz
TU3 : 150Hz TU1.5: 200Hz
0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB
200kHz -30dB 200kHz -30dB
Due to 400kHz -60dB 400kHz -60dB
Output RF
modulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB
6 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -65dB
Spectrum
3000 ~ 6000kHz -71dB 6000kHz -73dB
6000kHz -77dB
Due to
Switching
transient
1200kHz -21dB 1200kHz -24dB
1800kHz -24dB 1800kHz -27dB
2. PERFORMANCE
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Frequency offset 800kHz
7 Intermodulation attenuation
Intermodulation product should
be Less than 55dB below the
level of Wanted signal
Power control Power Tolerance Power control Power Tolerance
Level (dBm) (dB) Level (dBm) (dB)
5 33 3 0 30 3
6 31 3 1 28 3
7 29 3 2 26 3
8 27 3 3 24 3
9 25 3 4 22 3
10 23 3 5 20 3
8 Transmitter Output Power 11 21 3 6 18 3
12 19 3 7 16 3
13 17 3 8 14 3
14 15 3 9 12 4
15 13 3 10 10 4
16 11 5 11 8 4
17 9 5 12 6 4
18 7 5 13 4 4
19 5 5 14 2 5
15 0 5
9 Burst timing Mask IN Mask IN
2. PERFORMANCE
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2) Transmitter - WCDMA Mode
No Item Specification
1 Maximum Output Power Class 3 : +24dBm(+1/-3dB)
2 Frequency Error 0.1ppm
3 Open Loop Power control in uplink 9dB@normal, 12dB@extreme
Adjust output(TPC command)
cmd 1dB 2dB 3dB
+1 +0.5/1.5 +1/3 +1.5/4.5
4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5
-1 -0.5/-1.5 -1/-3 -1.5/-4.5
Group (10 equel command group)
+1 +8/+12 +16/+24
5 Minimum Output Power -50dBm(3.84MHz)
Qin/Qout : PCCH quality levels
6 Out-of-synchronization handling of output power Toff@DPCCH/Ior : -22 -> -28dB
Ton@DPCCH/Ior : -24 -> -18dB
7 Transmit OFF Power -56dBm(3.84MHz)
8 Transmit ON/OFF Time Mask
25us
PRACH,CPCH,uplinlk compressed mode
25us
9 Change of TFC
Power varies according to the data rate
DTX : DPCH off
(minimize interference between UE)
10 Power setting in uplink compressed 3dB(after 14slots transmission gap)
11 Occupied Bandwidth(OBW) 5MHz(99%)
-35-15*(f-2.5)dBc@f=2.5~3.5MHz,30k
12 Spectrum emission Mask
-35-1*(f-3.5)dBc@f=3.5~7.5MHz,1M
-39-10*(f-7.5)dBc@f=7.5~8.5MHz,1M
-49dBc@f=8.5~12.5MHz,1M
3)Receiver - GSM Mode
2. PERFORMANCE
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13 Adjacent Channel Leakage Ratio(ACLR)
33dB@5MHz, ACP>-50dBm
43dB@10MHz, ACP>-50dBm
-36dBm@f=9~150KHz, 1K BW
-36dBm@f=50KHz~30MHz, 10K BW
-36dBm@f=30MHz~1000MHz, 100K BW
14
Spurious Emissions -30dBm@f=1~12.5GHz, 1M BW
(*: additional requirement) (*)-41dBm@f=1893.5~1919.6MHz, 300K
(*)-67dBm@f=925~935MHz, 100K BW
(*)-79dBm@f=935~960MHz, 100K BW
(*)-71dBm@f=1805~1880MHz, 100K BW
15 Transmit Intermodulation
-31dBc@5MHz,Interferer -40dBc
-41dBc@10MHz, Interferer -40dBc
16 Error Vector Magnitude (EVM)
17.5%(>-20dBm)
(@12.2K, 1DPDCH+1DPCCH)
17 Transmit OFF Power
-15dB@SF=4.768Kbps, Multi-code
transmission
2. PERFORMANCE
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3) Transmitter - HSDPA Mode
1 Maximum Output Power
Sub-Test
1=1/15, 2=12/15 21~25dBm / 3.84 MHz
3=13/15 4=15/8 20~25dBm / 3.84 MHz
5=15/7 6=15/0 19~25dBm / 3.84 MHz
Sub-test Power Start of Ack/Nack Power Transmitter
in table step boundary step power step
C.10.1.4 size, P tolerance
2 HS-DPCCH
[dB] [dB]
1 Start of Ack/Nack 6 +/- 2.3
5
2 Start of CQI 1 +/- 0.6
3 Middle of CQI 0 +/- 0.6
4 End of CQI 5 +/- 2.3
3 Spectrum Emission Mask Sub-Test : 1=1/15, 2=12/15, 3=13/15,
4=15/8, 5=15/7, 6=15/0
Frequency offset Minimum Measurement
from carrier f requirement Bandwidth
2.5 ~ 3.5 MHz -35-15(f-2.5)dBc 30 kHz
3.5 ~ 7.5 MHz -35-1(f-3.5)dBc 1 MHz
7.5 ~ 8.5 MHz -35-10(f-7.5)dBc 1 MHz
8.5 ~ 12.5 MHz -49dBc 1 MHz
4 Adjacent Channel Leakage Sub-Test : 1=1/15, 2=12/15, 3=13/15,
Power Ratio (ACLR) 4=15/8, 5=15/7, 6=15/0
> 33 dB @ 5 MHz
> 43 dB @ 10 MHz
5 Error Vector Magnitude 3GPP Not Complete
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2. PERFORMANCE
4)Receiver - GSM Mode
1 Sensitivity (TCH/FS Class II) -105dBm -105dBm
2
Co-Channel Rejection
C/Ic=7dB Storage -30 ~ +85
(TCH/FS Class II, RBER, TU high/FH)
3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB
Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB
Wanted Signal :-98dBm 1st Wanted Signal :-96dBm 1st
4 Intermodulation Rejection interferer:-44dBm 2nd interferer:-44dBm 2nd
interferer:-45dBm interferer:-44dBm
5
Blocking Response Wanted Signal :-101dBm Wanted Signal :-101dBm
(TCH/FS Class II, RBER) Unwanted : Depend on Frequency Unwanted : Depend on Frequency
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2. PERFORMANCE
5) Receiver - WCDMA Mode
1 Reference Sensitivity Level -106.7 dBm(3.84 MHz)
-25dBm(3.84MHz)
2 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec)
UE@+20dBm output power(Class3)
3 Adjacent Channel Selectivity (ACS)
33dB
-56dBm/3.84MHz@10MHz
4 In-band Blocking UE@+20dBm output power(Class3)
-44dBm/3.84MHz@15MHz
-44dBm/3.84MHz@f=2050~2095 and
2185~2230MHz
-30dBm/3.84MHz@f=2025~2050 and
5 Out-band Blocking 2230~2255MHz
-15dBm/3.84MHz@f=1~2025 and
2255~12500MHz
6 Spurious Response
-44dBm CW
-46dBm CW@10MHz
7 Intermodulation Characteristic -46dBm/3.84MHz@20MHz
-57dBm@f=9KHz~1GHz, 100K BW
8 Spurious Emissions -47dBm@f=1~12.5GHz, 1M BW
-60dBm@f=1920MHz~1980MHz, 3.84M BW
-60dBm@f=2110MHz~2170MHz, 3.84M BW
2. PERFORMANCE
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6) Receiver - HSDPA Mode
2.4 Current Consumption
1) KU990R/U990 Current Consumption
(Stand by and Voice Call Test Condition : Bluetooth off, LCD backlight off,Neighbor Cell off) (VT Test
Condition : Speaker off, LCD backlight On)
Stand by Voice Call VT
WCDMA
Under 4.00 mA Under 350 mA Under 550mA
(DRX=1.28) (Tx=10dBm) (Tx=10dBm)
Under 4.00 mA Under 300 mA
GSM Paging=5 period (Tx=29dBm)
1 Maximum Input Level Sub-Test : 1=1/15, 2=12/15, 3=13/15,
(BLER or R), 16QAM Only 4=15/8, 5=15/7, 6=15/0
BLER < 10% or R >= 700kbps
2.5 RSSI BAR
2.6 Battery BAR
2. PERFORMANCE
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Indication Standby
Bar 4 Over 3.81 0.03V
Bar 4 3 3.80 0.03V
Bar 3 2 3.70 0.03V
Bar 2 1 3.61 0.03V
Bar 1 Empty 3.49 0.03V
Low Voltage, 3.49 0.03V (Stand-by) / 3.49 0.03V (Talk)
Warning message+ Blinking [Interval : 3min(Stand-by) / 1min(Talk)]
Power Off
3.20 0.03V (Stand-by)
3.10 0.03V (Talk)
Level Change WCDMA GSM
BAR 4 3 -88 2 dBm -90 2 dBm
BAR 3 2 -98 2 dBm -95 2 dBm
BAR 2 1 -108 2 dBm -100 2 dBm
BAR 1 0 -112 2 dBm -106 2 dBm
2. PERFORMANCE
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2.7 Sound Pressure Level
2.8 Charging
Charging Method : CC & CV (Constant Current and Constant Voltage)
Maximum Charging Voltage : 4.2 V
Maximum Charging Current : 600 mA
Normal Battery Capacity : 1000 mAh
Charging Time : Max 3 hours (except for trickle charging time)
Full charging indication current (charging icon stop current) : 80 mA
Cut-off voltage : 3.20 V (Stand-By), 3.10V (Talk)
No Test Item Specification
1 Sending Loudness Rating (SLR) 8 3 dB
2 Receiving Loudness Rating (RLR)
Nor -4 3 dB
Max -15 3 dB
3 Side Tone Masking Rating (STMR) Min 17 dB
4 Echo Loss (EL) Min 40 dB
5 Idle Noise-Sending (INS) Max -64 dBm0p
6 Idle Noise-Receiving (INR)
Nor Under -47 dBPA
Max Under -36 dBPA
7 Sending Loudness Rating (SLR) 83dB
8 Receiving Loudness Rating (RLR)
Nor -1 3 dB
Max -12 3 dB
9 Side Tone Masking Rating (STMR) Min 25 dB
10 Echo Loss (EL) Min 40 dB
11 Idle Noise-Sending (INS) Max -55 dBm0p
12 Idle Noise-Receiving (INR)
Nor Under -45 dBPA
Max Under -40 dBPA
TDMA Noise
-. GSM : Power Level : 5
DCS/PCS : Power Level : 0
(Cell Power : -90 ~ -105 dBm)
13
-. Acoustic (Max Vol.)
MS/Headset SLR : 8 3dB
MS/Headset RLR : -15 3dB/-12dB
(SLR/RLR : Mid-value setting)
MS
Headset
MS and
Headset
Max Under -62 dBm
3. TECHNICAL BRIEF
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3.1 General Description
The U990 supports UMTS-2100, GSM-900, DCS-1800, and PCS-1900 based
GSM/GPRS/EDGE/UMTS. All receivers and the UMTS transmitter use the radioOne
1
Zero-IF
architecture to eliminate intermediate frequencies, directly converting signals between RF and
baseband. The quad-band GSM transmitters use a baseband-to-IF upconversion followed by an offset
phase-locked loop that translates the GMSK-modulated or 8-PSK-modulated signal to RF.
1
QUALCOMMs branded chipset that implements a Zero-IF radio architecture.
3. TECHNICAL BRIEF
[Fig 1.1] Block diagram of RF part
A generic, high-level functional block diagram of U990 is shown in Figure 1-1. One antenna collects
base station forward link signals and radiates handset reverse link signals. The antenna connects with
receive and transmit paths through a FEM(Front End Module).
The UMTS receive paths each include an LNA, an RF band-pass filter, and a downconverter that
translate the signal directly from RF-to-baseband using radioOne ZIF techniques. The RFICs Rx
analog baseband outputs, for the receive chains, connect to the MSM IC. The UMTS and GSM Rx
baseband outputs share the same inputs to the MSM IC.
For the transmit chains, the RTR6275 IC directly translates the Tx baseband signals (from the MSM
device) to an RF signal using an internal LO generated by integrated on-chip PLL and VCO. The
RTR6275 IC outputs deliver fairly high-level RF signals that are first filtered by Tx SAWs and then
amplified by their respective UMTS PAs. The high- and low-band UMTS RF transmit signals emerge
from the RTR6275 transceiver.
In the GSM receive path, the received RF signals are applied through their band-pass filters and
down-converted directly to baseband in the RTR6275 transceiver IC. These baseband outputs are
shared with the UMTS receiver and routed to the MSM IC for further signal processing.
The GSM/EDGE transmit path employs one stage of up-conversion and, in order to improve efficiency,
is divided into phase and amplitude components to produce an open-loop Polar topology:
1. The on-chip quadrature up-converter translates the GMSK-modulated signal or 8-PSK modulated
signal, to a constant envelope phase signal at RF;
2. The amplitude-modulated (AM) component is applied to the ramping control pin of Polar power
amplifier from a DAC within the MSM
U990 power supply voltages are managed and regulated by the PM6650 Power Management IC. This
versatile device integrates all wireless handset power management, general housekeeping, and user
interface support functions into a single mixed signal IC. It monitors and controls the external power
source and coordinates battery recharging while maintaining the handset supply voltages using low
dropout, programmable regulators.
The devices general housekeeping functions include an ADC and analog multiplexer circuit for
monitoring on-chip voltage sources, charging status, and current flow, as well as userdefined off-chip
variables such as temperature, RF output power, and battery ID. Various oscillator, clock, and counter
circuits support IC and higher-level handset functions. Key parameters such as under-voltage lockout
and crystal oscillator signal presence are monitored to protect against detrimental conditions.
3. TECHNICAL BRIEF
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3. TECHNICAL BRIEF
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3.2 GSM Mode
3.2.1 GSM Receiver
The Dual-mode U990s receiver functions are split between the three RFICs as follows:
GSM-900, DCS-1800, PCS-1900 and UMTS-2100 modes both use the RTR6275 IC only. Each
mode has independent front-end circuits and down-converters, but they share common baseband
circuits (with only one mode active at a time). All receiver control functions are beginning with SBI2-
controlled parameters.
RF Front end consists of antenna, antenna switch module (LSHS-M090UH) which includes three RX
saw filters (GSM-900, DCS-1800 and PCS-1900). The antenna switch module allows multiple
operating bands and modes to share the same antenna. In U990, a common antenna connects to one
of six paths: 1) UMTS-2100 Rx/Tx, 2) GSM-900 Rx, 3) GSM-900 Tx, 4) DCS-1800 Rx, and 5) DCS-
1800, PCS-1900 Tx(High Band Txs share the same path), 6) PCS-1900 Rx. UMTS operation requires
simultaneous reception and transmission, so the UMTS Rx/Tx connection is routed to a duplexer that
separates receive and transmit signals. GSM900, DCS1800, and PCS1900 operation is time division
duplexed, so only the receiver or transmitter is active at any time and a frequency duplexer is not
required.
Control Logic (L : 0 ~ 0.1V, H : 2.6 ~ 2.8V)
L/H : L and H are acceptable
2
The RFIC operating modes and circuit parameters are MSM-controlled through the proprietary 3-line Serial Bus Interface (SBI). The Application
Programming Interface (API) is used to implement SBI commands. The API is documented in AMSS Software - please see applicable AMSS
Software documentation for details.
Vc3 Vc2 Vc1 Vdd
GSM900 Tx L H H H
DCS1800/PCS1900 Tx L L H H
UMTS Tx/Rx H L H H
GSM 900 Rx L L/H L H
DCS 1800 Rx H L/H L H
PCS 1900 Rx L L/H L H
[Table 1.1] Antenna Switch Module Control logic
The GSM900, DCS1800, and PCS1900 receiver inputs of RTR6275 are connected directly to the
transceiver front-end circuits(filters and antenna switch module). GSM900, DCS1800, and PCS1900
receiver inputs use differential configurations to improve common-mode rejection and second-order
non-linearity performance. The balance between the complementary signals is critical and must be
maintained from the RF filter outputs all the way into the IC pins
Since GSM900, DCS1800, and PCS1900 signals are time-division duplex (the handset can only
receive or transmit at one time), switches are used to separate Rx and Tx signals in place of frequency
duplexers - this is accomplished in the switch module.
The GSM900, DCS1800, and PCS1900 receive signals are routed to the RTR6275 through band
selection filters and matching networks that transform single-ended 50-sources to differential
impedances optimized for gain and noise figure. The RTR input uses a differential configuration to
improve second-order inter-modulation and common mode rejection performance. The RTR6275 input
stages include MSM-controlled gain adjustments that maximize receiver dynamic range.
The amplifier outputs drive the RF ports of the quadrature RF-to-baseband downconverters. The
downconverted baseband outputs are multiplexed and routed to lowpass filters (one I and one Q)
having passband and stopband characteristics suitable for GMSK or 8-PSK processing. These filter
circuits include DC offset corrections. The filter outputs are buffered and passed on to the MSM6280 IC
for further processing (an interface shared with the RFR6275 UMTS receiver outputs)
3. TECHNICAL BRIEF
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3. TECHNICAL BRIEF
- 23 -
[Fig 1.2] RTR6275 RX feature
3.2.2 GSM Transmitter
The RTR6275 transmitter outputs(DA_HB2_OUT and DA_LB1_OUT) include on-chip output matching
inductors. 50ohm output impedance is achieved by adding a series capacitor at the output pins. The
capacitor value may be optimized for specific applications and PCB characteristics based on pass-band
symmetry about the band center frequency, the suggested starting value is shown in Figure1.3.
The RTR6275 IC is able to support GSM 900 and GSM 1800/1900 mode transmitting. This design
guideline shows a tri-band GSM application.
Both high-band and low band outputs are followed by resistive pads to ensure that the load Presented
to the outputs remains close to 50ohm. The low-band GSM. Tx path also includes a Tx-band SAW filter
to remove noise-spurious components and noise that would be amplified by the PA and appear in the
GSM Rx band
3. TECHNICAL BRIEF
- 24 -
91 91
6pF
120 120
68
5pF 51
[Fig 1.3] GSM Transmitter matching
3. TECHNICAL BRIEF
- 25 -
3.3 UMTS Mode
3.3.1 Receiver
The UMTS duplexer receiver output is routed to LNA circuits within the RTR6275 device. The UMTS Rx
input is provided with an on-chip LNA that amplifies the signal before a second stage filter that provides
differential downconverter. This second stage input is configured differentially to optimize second-order
intermodulation and common mode rejection performance. The gain of the UMTS frontend amplifier and
the UMTS second stage differential amplifier are adjustable, under MSM control, to extend the dynamic
range of the receivers. The second stage UMTS Rx amplifiers drive the RF ports of the quadrature RF-
tobaseband downconverters. The downconverted UMTS Rx baseband outputs are routed to lowpass
filters having passband and stopband characteristics suitable for UMTS Rx processing. These filter
circuits allow DC offset corrections, and their differential outputs are buffered to interface shared with
GSM Rx to the MSM IC. The UMTS baseband outputs are turned off when the RTR6275 is
downconverting GSM signals and on when the UMTS is operating.
3.3.2 Transmitter
The UMTS Tx path begins with differential baseband signals (I and Q) from the MSM device. These
analog input signals are amplified, filtered, and applied to the quadrature up-converter mixers. The up-
converter output is amplified by multiple variable gain stages that provide transmit AGC control. The
AGC output is filtered and applied to the driver amplifier; this output stage includes an integrated
matching inductor that simplifies the external matching network to a single series capacitor to achieve
the desired 50- interface.
The RTR6275 UMTS output is routed to its power amplifier through a bandpass filter, and delivers fairly
high-level signals that are filtered and applied to the PA. Transmit power is delivered from the duplexer
to the antenna through the switch module.
The transceiver LO synthesizer is contained within the RTR6275 IC with the exception of the off-chip
loop filter components and the VC-TCXO. This provides a simplified design for multimode applications.
The PLL circuits include a reference divider, phase detector, charge pump, feedback divider, and digital
logic generator.
UMTS Tx. Using only PLL1, the LO generation and distribution circuits create the necessary LO signals
for nine different frequency converters. The UMTS transmitter also employs the ZIF architecture to
translate the signal directly from baseband to RF. This requires FLO to equal FRF, and the RTR6275 IC
design achieves this without allowing FVCO to equal FRF. The RTR6275 IC is able to support UMTS
2100/1900 and UMTS 850 mode transmitting.
This design guideline shows only UMTS 2100 applications.
3. TECHNICAL BRIEF
- 26 -
[Figure 1.4] RTR6275 IC functional block diagram

3.4 LO generation and distribution circuits
The integrated LO generation and distribution circuits are driven by internal VCOs to support various
modes to yield highly flexible quadrature LO outputs that drive all GSM/EDGE and UMTS band
upconverters and downconverters; with the help of these LO generation and distribution circuits, true
zero-IF architecture is employed in all GSM and UMTS band receivers and transmitters to translate the
signal directly from RF to baseband and from baseband to RF.
Two fully functional fractional-N synthesizers, including VCOs and loop filters, are integrated within the
RTR6275 IC. The first synthesizer (PLL1) creates the transceiver LOs that support the UMTS
2100/1900/1800 transmitter, and all four GSM band receivers and transmitters including: GSM850,
GSM900, DCS1800, and PCS1900. The second synthesizer (PLL2) provides the LO for the UMTS
2100/1900/1800 receiver. An external TCXO input signal is required to provide the synthesizer
frequency reference to which the PLL is phase and frequency locked. The RTR6275 IC integrates
most of PLL loop filter components onchip except two off-chip loop filter series capacitors, and
significantly reduces off-chip component requirement. With the integrated fractional-N PLL
synthesizers, the RTR6275 has the advantages of more flexible loop bandwidth control, fast lock time,
and low-integrated phase error.
3.5 Off-chip RF Components
3.5.1 UMTS PAM (U105: AWT6277R)
The UMTS PA output power is monitored by power detector circuits (U101 : RTR6275) . This detector
voltage can be used for transmitter calibration and monitor to meet RF system specification.
3. TECHNICAL BRIEF
- 27 -
[Figure 1.5] UMTS PAM, Duplexer, Coupler
20dB
8 dB
NA
C165
100p
C163 C160
22u
51
R124
L122
NA
100
R126
2
4
5
3
1
Q100
KRX102E
C162
0.01u
15nH
L123
2
RFIN
RFOUT
8
VCC1
1 10
VCC2
4
VMODE
VREF
5
AWT6277R
U105
GND1
3
GND2
6
7
GND3
9
GND4
GND5
11
5.6p C169
C161
56p
SCDY0003403
5
0
O
H
M
43
C
O
U
P
2
IN
1
O
U
T
C173
100p
U104
R123
68
C159
8.2p
1.8p
C170
L128
4.7nH
L124
3.3nH
L126
8.2nH
EFCH1950TDF1
FL104
G1
2
G2
3
G3
5
IN
1 O1
4
R125
100
1u
C164
FL103 A
N
T
21
G
N
D
1
G
N
D
2
48
G
N
D
3
G
N
D
4
9
G
N
D
5
6
G
N
D
6
3 7
R
X
5
T
X
SAYZY1G95EB0B00
WCDMA_2100_TX_OUT
PA_ON
VREG_TCXO_2.85V
+VPWR
PA_R1
PWR_DET
3.5.2 VCTCXO (X100 : TG-5010LH(19.2M))
The Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO) provides the
reference frequency for all RFIC synthesizers as well as clock generation functions within the
MSM6280 IC. The oscillator frequency is controlled by the MSM6280 IC.s TRK_LO_ADJ pulse density
modulated signal in the same manner as the transmit gain control TX_AGC_ADJ. A two-pole RC
lowpass filter is recommended on this control line.
The PM6650 IC controls the handset power-up sequence, including a special VCTCXO warm-up
interval before other circuits are turned on. This warm-up interval (as well as other TCXO controller
functions) is enabled by the MSM TCXO_EN line . The PM6650 IC VREG_TCXO regulated output
voltage is used to power the VCTCXO and is enabled before most other regulated outputs.
Any GSM mode power control circuits within the MSM6280 IC require a reference voltage for proper
operation and sufficient accuracy. Connecting the PM6650 IC REF_OUT directly to the MSM6275 IC
GSM_PA_PWR_CTL_REF provides this reference. This sensitive analog signal needs a 0.1 F low
frequency filter near to MSM side, and isolate from digital logic and clock traces with ground on both
sides, plus ground above and below if routed on internal layers.
3.5.3 Front-End Module (FL100 : LSHS-M090UH)
This equipment uses a single antenna to support all handset operating modes, with an antenna switch
module select the operating frequency and band. UMTS operation requires simultaneous reception
and transmission, so the UMTS Rx/Tx connection is routed to a duplexer that separates receive and
transmit signals. The active connection is MSM-selected by three control lines (GPIO[9], GPIO[10],
and GPIO[11]). These GPIOs are programmed to be ANT_SEL0, ANT_SEL1, and ANT_SEL2
respectively.
3. TECHNICAL BRIEF
- 28 -
[Table 1.2] Front End Module control logic
Vc3 Vc2 Vc1 Vdd
GSM900 Tx L H H H
UMTS Tx/Rx H L H H
GSM 900 Rx L L L H
DCS 1800 Rx H L L H
PCS 1900 Rx L L L H
3. TECHNICAL BRIEF
- 29 -
3.5.4 PMIC Functional Block Diagram (U501 : PM6650-2M)
Input power management
- Valid external supply attachment and removal detection
- Supports unregulated (closed-loop) external charger supplies and USB supplies as input power sources
- Supports lithium-ion main batteries
- Trickle, constant current, constant voltage, and pulsed charging of the main battery
- Supports coin cell backup battery (including charging)
- Battery voltage detectors with programmable thresholds
- VDD collapse protection
- Charger current regulation and real-time monitoring for over-current protection
- Charger transistor protection by power limit control
- Control drivers for two external pass transistors and one external battery MOSFET MOSFET is optional
- Voltage, current, and power control loops
- Automated recovery from sudden momentary power loss
Output voltage regulation
- One boost (step-up) switched-mode power supply (SMPS) for driving white LEDs and hosting USBOTG
- Three buck (step-down) switched-mode power supplies that efficiently generate MSMC, MSME, and PA
(or second MSMC) supply voltages
- Supports dynamic voltage scaling (DVS) for MSMC and PA
- Eleven low dropout regulator circuits with programmable output voltages, implemented using three
different current ratings: 300 mA (two), 150 mA (six), and 50 mA (three). These can be used to power
MSMA, MSMP, RFRX1, RFRX2, RFTX, SYNT, TCXO, WLAN, MMC, USB, and RUIM circuits.
- All regulators can be individually enabled/disabled for power savings
- Low power mode available on MSMA and MSMP regulators
- All regulated outputs are derived from a common bandgap referenceclose tracking
Integrated handset-level housekeeping functions reduces external parts count, size, cost
- Analog multiplexer selects from 8 internal and up to 18 external inputs
- Multiplexer outputs offset and gain are adjusted, increasing the effective ADC resolution
- Adjusted multiplexer output is buffered and routed to an MSM device ADC
- Dual oscillators -32.768 kHz off-chip crystal and on-chip RC assures MSM device sleep clock
- Crystal oscillator detector and automated switch-over upon lost oscillation
- Real time clock for tracking time and generating associated alarms
- On-chip adjustments minimize crystal oscillator frequency errors
- Circuits control TCXO warm-up and synchronize, deglitch, and buffer the TCXO signal
- TCXO buffer control for optimal QPH/catnap timing
- Three-stage over-temperature protection (smart thermal control)
Integrated handset-level user interfaces
- Four programmable current sinks recommended as keypad backlight, LCD backlight,
camera flash, and general-purpose drivers
- Vibration motor driver programmable from 1.2 to 3.1V in 100 mV increments
- Speaker driver with programmable gain, turn-on time, and muting; differential operation
(drives external 8 speakers with volume controlled 500 mW)
IC-level interfaces
- MSM device-compatible 3-line SBI for efficient initialization, status, and control
- Supports the MSM devices interrupt processing with an internal interrupt manager
- Many functions monitored and reported through real-time and interrupt status signals
- Dedicated circuits for controlled power-on sequencing, including the MSM devices reset signal
- Several events continuously monitored for triggering power-on/power-off sequences
- Supports and orchestrates soft resets
- USB-OTG transceiver for full-speed (12 Mb/s) and low speed (1.5 Mb/s) interfacing of the MSM device to
computers as a USB peripheral, or connecting the MSM device to other peripherals
- RUIM level translators enable MSM device interfacing with external modules
Twelve multi-purpose pins that can be configured as digital or analog I/Os, bi-directional I/Os, or current
sinks. Default functions support the RUIM level translators, power-on circuits, analog multiplexer inputs, an
LED driver, and a reference voltage buffer.
Highly integrated functionality in a small package - 84-pin BCCS with a large center slug for electrical
ground, mechanical stability, and thermal relief
3. TECHNICAL BRIEF
- 30 -
3. TECHNICAL BRIEF
- 31 -
[Figure 1.7] PM6650 Block Diagram
3.5.5 GSM PAM (U101:TQM7M5003)
The TQM7M5003 is an extremely small (7 x 7 mm), GSM/EDGE PAM for handset applications. This
module has been optimized for excellent EDGE efficiency and Pout in a Polar Loop environment at
EDGE class E2+ operation while maintaining high GSM/GPRS efficiency.
The small size and high performance is achieved with high-reliability 3
rd
generation InGaP HBT
technology. With 50 and output, no external matching or bias components are required.
The module incorporates two highly-integrated InGaP power amplifier die with a CMOS controller.
Each amplifier has three gain stages with on-die inter-stage matching implemented with a high Q
passives technology for optimal performance. The CMOS controller implements a fully integrated
power control within the module for GSM operations, and serves as the AM/AM path in EDGE
operations. This eliminates the need for any external couplers, power detectors, current sensing etc.,
to assure the output power level. The module has Tx enable and band select inputs. Module
construction is a low-profile overmolded landgrid array on laminate.
3. TECHNICAL BRIEF
- 32 -
[Figure 1. 8] GSM PAM Schematic
HIGH
MODE
LOW
GSM_PA_BAND
10 dB
GSM
DCS/PCS
PQ
8 dB
C138
NA
33u
C135
120
R119
120
R118
51
R114
91
R112
R117 2.2K
C142
0.75p
8p C136
91
R113
1u
C137
L113
14
GND6
G
N
D
7
1
6
1
7
G
N
D
8
7
GSM_IN
9
GSM_OUT
3
TX_EN
VBATT
4
12
VCC
VRAMP
6
4.7nH
TQM7M5003
U101
2
BS
DCS_PCS_IN
1
D
C
S
_
P
C
S
_
O
U
T
1
5
5
GND1
GND2
8
10
GND3
11
GND4
13
GND5
2
G1
3
G2
5
G3 1
IN
4
O1
EFCH897MTDB1
FL101
15nH
L112
C146 10p
68p
C143
68
R111
GSM_PA_BAND
+VPWR
DCS_PCS_TX
GSM_TX
GSM_PA_RAMP
GSM_PA_EN
3. TECHNICAL BRIEF
- 33 -
3.5.6 UMTS Duplexer(FL103:SAYZY1G95EB0B00)
A UMTS duplexer splits a single operating band into receive and transmit paths. Important
performance requirements include;
Insertion loss, this component is also in the receive and transmit paths ;
In the U990 typical losses : UMTS2100_ Tx = 1.5 dB, UMTS2100_ Rx = 1.8 dB
Out-of-band rejection or attenuation, the duplexer provides input selectivity for the receiver, output
filtering for the transmitter, and isolation between the two. Rejection levels for both paths are
specified over a number of frequency ranges. Two Tx-to-Rx isolation levels are critical to receiver
performance:
Rx-band isolation, the transmitter is specified for out-of-band noise falling into the Rx band. This
noise leaks from the transmit path into the receive path, and must be limited to avoid degrading
receiver sensitivity. The required Rx-band isolation depends on the PA out of-band noise levels and
Rx-band losses between the PA and LNA. Minimum duplexer Rx band isolation value is about 46.7
dB.
Tx-band isolation, the transmit channel power also leaks into the receiver. In this case, the leakage is
outside the receiver passband but at a relatively high level. It combines with Rx band jammers to
create cross-modulation products that fall in-band to desensitize the receiver. The required Tx-band
isolation depends on the PA channel power and Tx-band losses between the PA and LNA. Minimum
duplexer Tx-band isolation value is about 51.7dB.
Passband ripple, the loss of this fairly narrowband device is not flat across its passband. Passband
ripple increases the receive or transmit insertion loss at specific frequencies, creating performance
variations across the band.s channels, and should be controlled.
Return loss, minimize mismatch losses with typical return losses of 10 dB or more (VSWR <2:1).
Power handling, high power levels in the transmit path must be accommodated without degraded
performance. The specified level depends on the operating band class and mobile station class (per
the applicable standard), as well as circuit losses and antenna EIRP. Several duplexer characteristics
depend upon its source and load impedances. QUALCOMM strongly recommends an isolator be
used between the UMTS PA and duplexer to assure proper performance.
3.5.7 UMTS Rx RF filter (FL102 : EFCH2140TDE1)
An RF filter is located between the UMTS LNA and mixer. Insertion loss is important, but not as critical
as losses before the LNA. The most important parameters of this component include:
Out-of-band rejection or attenuation levels, usually specified to meet these conditions:
- Far out-of-band signals - ranging from DC up to the first band of particular concern and from the
last band of particular concern to beyond three times the highest passband frequency.
- Tx-band leakage - the transmitter channel power, although attenuated by the duplexer, still
presents a cross-modulation threat in combination with Rx-band jammers. The RF filter must
provide rejection of this Tx-band leakage.
- Other frequencies of particular concern . bands known to include other wireless transmitters that
may deliver significant power levels to the receiver input.
3. TECHNICAL BRIEF
- 34 -
[Table 1.3] UMTS Rx SAW Filter Specification
3. TECHNICAL BRIEF
- 35 -
3.5.8 Bluetooth (M800 : LBRQ-2B43A)
The MSM6280 includes BT baseband embedded BT 1.1 compliant baseband core, so the other
bluetooth components are bluetooth RF module and Antenna. Figure1.9 shows the bluetooth system
architecture in the U990.
[Figure 1.9] Bluetooth system architecture
- 36 -
3. TECHNICAL BRIEF
3.5.9 FM Radio (U103 : TEA5766UK)
This FM Module is a single chip, electronically tuned, FM stereo radio with RDS/RBDS demodulator
and decoder for low voltage applications, with fully integrated IF selectivity and demodulation. This
equipment tunes the European, US, and Japanese FM bands.
Figure1.10 shows the FM Radio system architecture in the U990.
[Figure 1.10] FM Radio system architecture in the U990
- 37 -
3. TECHNICAL BRIEF
3.6 Digital Baseband (DBB/MSM6280)
3.6.1 General Description
A. Features (MSM6280)
Support for multimode operation - HSDPA, tri-band WCDMA (UMTS), quad GSM/GPRS/EDGE
Support for HSDPA downlink up to 7.2Mbps (initial commercial release will support 3.6Mbps
HSDPA. Later releases will have support for 7.2 Mbps HSDPA)
Support for WCDMA (UMTS) uplink data rate up to 384 kbps
High-performance ARM926EJ-S running at up to 225 MHz (later at 270 MHz for 7.2 Mbps HSDPA)
ARM Jazelle Java hardware acceleration for faster Java-based games and other applets
QDSP4000 high-performance DSP cores
Integrated Bluetooth 1.2 baseband processor for wireless connectivity to peripherals
Qcamera
TM
with 15 fps QVGA viewfinder resolution, and support for 4 MP camera sensors
Direct interface to digital camera module with video front end (VFE) image processing
True 3D graphics for advanced wireless gaming
SecureMSM v2.0 includes support for Open Mobile Alliance (OMA) DRM v2.0, SIM-lock and IMEI
integrity. Support for Q-fuse.
Audio on par with portable music players
Vocoder support (AMR, FR, EFR, HR)
Advanced 14 x 14 mm, 0.5 mm pitch, 409-pin lead-free CSP packaging technology
SD/SDIO hardware support
3. BB Technical Description
3. TECHNICAL BRIEF
- 38 -
Figure. Simplified Block Diagram of Baseband
3. TECHNICAL BRIEF
- 39 -
Figure. Simplified Block Diagram of RF
- 40 -
3. TECHNICAL BRIEF
3.7 Subsystem(MSM6280)
3.7.1. ARM Microprocessor Subsystem
The MSM6280 device uses an embedded ARM926EJ-S microprocessor. This microprocessor,
through the system software, controls most of the functionality for the MSM, including control of the
external peripherals such as the keypad, LCD, SDRAM, and NAND-Flash devices. Through a
QUALCOMM proprietary serial bus interface (SBI) the ARM926EJ-S configures and controls the
functionality of the RTR6275, RFR6275 and PM6650 devices.
3.7.2 WCDMA R99 features
The MSM6280 device supports release 99 June 2004 of the W-CDMA FDD standard, including the
following features:
All modes and data rates for W-CDMA frequency division duplex (FDD), with the following
restrictions:
The downlink supports the following specifications:
- Up to four physical channels, including the broadcast channel (BCH), if present
- Up to three dedicated physical channels (DPCHs)
- Spreading factor (SF) range support from 4 to 256
- The following transmit diversity modes are supported:
Space time transmit diversity (STTD)
Time-switched transmit diversity (TSTD)
Closed-loop feedback transmit diversity (CLTD)
The uplink supports the following specifications:
The uplink provides the following UE support:
- One physical channel, eight TrCH, and 16 TrBks starting at any frame boundary
- A maximum data rate of 384 kbps
Full SF range support from 4 to 256
SMS (CS and PS)
PS data rate - 384 kbps DL / 384 kbps UL
CS data rate - 64 kbps DL / 64 kbps UL
AMR (all rates)
3. TECHNICAL BRIEF
- 41 -
3.7.3 HSDPA features
The MSM6280 device supports the HSDPA release 5 standard:
Supports HS-DSCH (HS-SCCH, HS-PDSCH and HS-DPCCH) in addition to the R99 transport
channels as defined in 3GPP specifications.
Supports a maximum of four simultaneous HS-SCCH channels as defined in 3GPP specifications.
Supports a maximum of 10 HS-PDSCH channels and supports both QPSK and 16 QAM modulation.
It supports UE category 6 in SW release 2.0 and category 8 in SW release 4.0.
Supports CQI, and ACK/NACK on HS-DPCCH channel as defined in 3GPP specifications.
Supports all incremental redundancy versions for HARQ, as defined in 3GPP specifications.
Can switch between HS-PDSCH and DPCH channel resources, as directed by the network.
Can be configured to support any of the two power classes 3 or 4 as defined in 3GPP R5
specifications (25.101).
Supports network activation of compressed mode by SF/2 or HLS on the DPCH for conducting inter-
frequency or inter-RAT measurements when the HS-DSCH is active.
Supports STTD on both associated DPCH and HS-DSCH simultaneously.
Supports CLTD mode 1 on the DPCH when the HS-PDSCH is active.
Supports STTD on HS-SCCH when either STTD or CLTD Mode 1 are configured on the associated
DPCH.
Supports TFC selection limitation on the UL factoring in the transmissions on the HS-DPCCH as
required in TS 25.133.
3. TECHNICAL BRIEF
- 42 -
3.7.4 GSM features
The following GSM modes and data rates are supported by the MSM6280 device hardware. Support
modes conform to release '99 specifications of the sub-feature.
Voice features
FR
EFR
AMR
HR
A5/1, A5/2, and A5/3 ciphering
Circuit-switched data features
9.6k
14.4k
Fax
Transparent and non-transparent modes for CS data and fax
No sub-rates are supported.
3.7.5 GPRS features
Packet switched data (GPRS)
DTM (Simple Class A) operation
Multi-slot class 12 data services
CS schemes: CS1, CS2, CS3, and CS4
GEA1, GEA2, and GEA3 ciphering
Maximum of four Rx timeslots per frame
3.7.6 EDGE features
EDGE E2 power class for 8 PSK
DTM (simple Class A), multi-slot class 12
Downlink coding schemes - CS 1-4, MCS 1-9
Uplink coding schemes - CS 1-4, MCS 1-9
BEP reporting
SRB loopback and test mode B
8-bit, 11-bit RACH
PBCCH support
1 phase/2 phase access procedures
Link adaptation and IR
NACC, extended UL TBF.
3. TECHNICAL BRIEF
- 43 -
3.7.7 MSM6280 device audio processing features
Integrated wideband stereo CODEC
16-bit DAC with typical 88 dB dynamic range
Supports sampling rates up to 48 kHz on the speaker path and 16 kHz on the microphone path
VR- Voice mail + voice memo
Acoustic echo cancellation
Audio AGC
Audio Codecs: AMR-NB, AAC, AAC Plus, Enhanced AAC Plus, Windows Audio v9, Real Audio 8
(G2)
Internal vocoder supporting AMR, FR, EFR, and HR
3.7.8 MSM6280 microprocessor subsystem
Industry standard ARM926EJ-S embedded microprocessor subsystem
16 kB instruction and 16 kB data cache
Instruction set compatible with ARM7TDMI
ARM version 5TEJ instructions
Higher performance 5 stage pipeline, Harvard cached architecture
Higher internal CPU clock rate with on-chip cache
Java hardware acceleration
Enhanced memory support
Please note that NOR/PSRAM will not be supported on MSM6280.
75 MHz and 90 MHz bus clock for SDRAM
32-bit SDRAM
Dual memory buses separating the high-speed memory subsystem (EBI1) from low-speed
peripherals (EBI2) such as LCD panels
1.8 V or 2.6 V memory interface support (excluding EBI1)
NAND FLASH memory interface
- 8/16-bit data I/O width NAND flash support
- 1- or 4-bit ECC
- 512-byte/2KB page-size support
- 2 chip selects supported for NAND Flash
Boot from NAND
Low-power SDRAM (LP-SDRAM) interface
Internal watchdog and sleep timers
- 44 -
3. TECHNICAL BRIEF
3.7.9 Supported interface features
USB On-the-Go core supports both slave and host functionality
Three universal asynchronous receiver transmitter (UART) serial ports
USIM controller (via UART)
Integrated 4-bit secure digital (SD) controller for SD and Mini SD cards
Parallel LCD interface
General-purpose I/O pins
External keypad interface
3.7.10 Supported multimedia features
Provide additional general purpose MIPS by using:
Two QDSP4000s
Dedicated hardware accelerators and compression engines
Improve Java, BREW, and game performance
Integrated Java and 2D/3D graphics accelerator with Sprite engine
Enable various accessories via USB host connectivity.
Integrated USB host controller functionality
Enable compelling visual and audio applications.
Qcamera
TM
High-quality digital camera processing, supporting CCD or CMOS image sensors up to 4-megapixel
with 15 fps capture rate
15 fps QVGA viewfinder
Qtv
TM
Audio and video decoder that supports VOD, MOD and Broadcast multimedia services.
Audio Codecs supported: AMR-NB, AAC, AAC Plus, Enhanced AAC Plus, Windows Audio v9,
RealAudio v8
Integrated stereo wideband Codec for music/digital clips
CMX
Video Codecs supported: MPEG-4, H.263, H.264, Windows Media v9 and RealNetworks v10
Video telephony services: Qvideophone
TM
A two-way mobile video conferencing solution that delivers 15 fps @ QCIF
Video Codecs supported: MPEG-4 and H.263
Audio Codecs supported: AMR-NB.
- 45 -
3. TECHNICAL BRIEF
Qcamcorder
TM
Real time mobile video encoder
Video Codecs supported: MPEG-4, H.263.H.264
Audio Codecs supported: AMR-NB, AAC
Recording performance: 15 fps @ QVGA, 384 kbps
gpsOne
TM
Integrated gpsOne processing
Standalone gpsOne mode in which the handset acts as a GPS receiver
CMX
TM
(MIDI and still image, animation, text, LED/vibrate support)
72 simultaneous polyphonic tones
44 kHz sampling rate
512 kB wave table
Support of universal file formats
Standard MIDI Format (SMF)
SP-MIDI
SMAF Audio playback (MA-2, MA-3, MA-5)
XMF/OLS
MFil (requires Docomo license)
PNG decoder
Pitch bend range support
LED/vibrate support
Scalable Vector Graphics (SVG- Tiny 1.1 + SVG Tiny 1.2)
MLZ decoder
Integrated PNG/SAF A.T.
- 46 -
3. TECHNICAL BRIEF
3.7.11 Serial Bus Interface(SBI)
The MSM6280 devices SSBI is designed specifically to be a quick, low pin count control protocol for
QUALCOMMs RTR6275, RFR6275 and PM6650 ASICs. Using the SSBI, the RTR6275, RFR6275,
and PM6650 devices can be configured for different operating modes and for minimum power
consumption, extending battery life in Standby mode. The SSBI also controls DC baseband offset
errors.
3.7.12 Wideband CODEC
The MSM6280 device integrates a wideband voice/audio CODEC into the mobile station modem
(MSM). The CODEC supports two differential microphone inputs, one differential earphone output, one
single-ended earphone output, and a differential analog auxiliary interface. The CODEC integrates the
microphone and earphone amplifiers into the MSM6280 device, reducing the external component
count to just a few passive components. The microphone (Tx) audio path consists of a two-stage
amplifier with the gain of the second stage set interally. The Rx/Tx paths are designed to meet the
ITU-G.712 requirements for digital transmission systems.
- 47 -
3. TECHNICAL BRIEF
3.7.13 Vocoder Subsystem
The MSM6280 devices QDSP4000 supports AMR,FR,EFR and HR. In addition, the QDSP4000 has
modules to support the following audio functions: DTMF tone generation, DTMF tone detection, Tx/Rx
volume controls, Tx/Rx automatic gain control (AGC), Rx Automatic Volume Control (AVC), EarSeal
Echo Canceller (ESEC), Acoustic Echo Canceller (AEC), Noise Suppression (NS), and programmable,
13-tap, Type-I, FIR, Tx/Rx compensation filters. The MSM6280 devices integrated ARM9TDMI
processor downloads the firmware into the QDSP4000 and configures QDSP4000 to support the
desired functionality.
3.7.14 ARM Microprocessor subsystem
The MSM6280 device uses an embedded ARM926EJ-S microprocessor. This microprocessor,
through the system software, controls most of the functionality for the MSM device, including control of
the external peripherals such as the keypad, LCD, RAM, ROM, and EEPROM devices.
Through a generic single serial bus interface (SSBI) the ARM926EJ-S configures and controls the
functionality of the RFR6275, RTR6275, and PM6650 devices.
3.7.15 Mode Select and JTAG Interfaces
The mode pins to the MSM6280 device determine the overall operating mode of the ASIC. The options
under the control of the mode inputs are Native mode, which is the normal subscriber unit operation,
ETM mode, which enables the built-in trace mode, and test mode for factory testing. The MSM6280
device meets the intent of the ANSI/IEEE 1149.1A-1993 feature list. The JTAG interface can be used
to test digital interconnects between devices within the mobile station during manufacture.
3.7.16 General-Purpose Input/Output Interface
The MSM6280 device has general-purpose bidirectional input/output pins. Some of the GPIO pins
have alternate functions supported on them. The alternate functions include USB interface, additional
RAM, ROM, general-purpose chip selects, parallel LCD interface, and a UART interface. The function
of these pins is documented in the various software releases.
3.7.17 UART
The MSM6280 device employs three UARTs. UART1 has dedicated pins while UART2 and UART3
share multiplexed pins.
UART1 for data
UART2 (can be used for USIM interface)
UART3 for data
3.7.18 USB
The MSM6280 device integrates a universal serial bus (USB) controller that supports both
unidirectional and bidirectional transceiver interfaces. The USB controller acts as a USB peripheral
communicating with the USB host.
- 48 -
3. TECHNICAL BRIEF
3.8 Power Block
3.8.1 General
MSM6280, included RF, is fully covered by PM6650(Qualcomm PMIC). PM6650 cover the power of
MSM6280, MSM memory, RF block, Bluetooth, USIM and TCXO. Major power components are :
PM6650 : Phone power supply
AAT3169 : LCD Backlight/Flash charge pump
3.8.2 PM6650
The PM6650 device (Figure 1-1) integrates all wireless handset power management. The power
management portion accepts power from all the most common sources - battery, external charger,
adapter, coin cell back-up - and generates all the regulated voltages needed to power the appropriate
handset electronics. It monitors and controls the power sources, detecting which sources are applied,
verifying that they are within acceptable operational limits, and coordinates battery and coin cell
recharging while maintaining the handset electronics supply voltages. Eight programmable output
voltages are generated using low dropout voltage regulators, all derived from a common trimmed
voltage reference.
A dedicated controller manages the TCXO warm-up and signal buffering, and key parameters (under-
voltage lockout and crystal oscillator signal presence) are monitored to protect against detrimental
conditions.
MSM device controls and statuses the PM6650 IC using Single Serial Bus Interface (SSBI)
supplemented by an Interrupt Manager for time-critical information. Another dedicated IC Interface
circuit monitors multiple trigger events and controls the power-on sequence.
- 49 -
3. TECHNICAL BRIEF
Figure 1-1. PM6650 Functional Block Diagram
- 50 -
3. TECHNICAL BRIEF
3.8.3 Charging control
A programmable charging block in PM6650 is used for battery charging. It is possible to set limits for
the charging current. The external supply typically connects directly to pin (VCHG). The voltage on this
pin (VCHG) is monitored by detection circuitry to ascertain whether a valid external supply is applied or
not. For additional accuracy or to capture variations over time, this voltage is routed internally to the
housekeeping ADC via the analog multiplexer. PM6650 circuits monitor voltages at VCHARGER and
ICHARGE pins to determine which supply should be used and when to switch between the two
supplies. These pins are connected to the Source (or emitter) and Drain (or collector) contacts of the
pass transistor respectively.
4.2V~3.81V
100~70 (%)
3.80V~3.71V
69~45 (%)
3.70V~3.62V
44~20 (%)
3.61V~3.50V
19~3 (%)
3.49V~3.28V
2~0 (%)
KU990R Battery Bar Display(Stand By Condition)
- 51 -
3. TECHNICAL BRIEF
Trickle Charging
Trickle Charging of the main battery, enabled through SBI control and powered from VDD, is provided
by the PM6650 IC, The trickle charger is on-chip programmable current source that supplies current
from VDD to pin (VBAT). Trickle charging can be used for lithium-ion and nickel-based batteries, with
its performance specified below (3.2V). The charging current is set to 80mA.
Parameter Min Typ Max Unit
Trickle Current 60 80 100 mA
- 52 -
3. TECHNICAL BRIEF
Constant Current Charging
The PM6650 IC supports constant current charging of the main battery by controlling the charger pass
transistor and the battery transistor. The constant current charging continues until the battery reaches
its target voltage, 4.2V.
Constant Voltage Charging
Constant voltage charging begins when the battery voltage reaches a target voltage, 4.2V. The end of
constant voltage charging is commonly detected 10% of the full charging current.
Charging Method : CC & CV (Constant Current & Constant Voltage)
Maximum Charging Voltage : 4.2V
Maximum Charging Current : 600mA
Nominal Battery Capacity : 1000mAh
Charger Voltage : 5.1V
Charging time : Max 3h (Except time trickle charging)
Full charge indication current (icon stop current) : 100mA
Low battery POP UP : Idle - 3.49V, Dedicated(GSM/WCDMA) - 3.49V
Low battery alarm interval : Idle - 3 min, Dedicated - 1min
Cut-off voltage : 3.20V(idle), 3.1V(call)
- 53 -
3. TECHNICAL BRIEF
3.9 External memory interface
The MSM6280 device was designed to provide two distinct memory interfaces. EBI1 was targeted for
supporting high speed synchronous memory devices. EBI2 was targeted towards supporting slower
asynchronous devices such as LCD, NAND flash, SRAM, etc. In addition, MSM6280 provide SD bus
interface. KU990R supports 512MByte free user memory using SD interface.
EBI1 Features
- 16 bit static and dynamic memory interface
- 32 bit dynamic memory interface
- 24 bits of address for static memory devices which can support up to 32MBytes on each chip select
- Synchronous burst memories supported (burst NOR, burst PSRAM)
- Synchronous DRAM memories supported
- Byte addressable memory supporting 8 bit, 16 bit and 32 bit accesses
- Pseudo SRAM (PSRAM) memory support
EBI2 Features
- Support for asynchronous FLASH and SRAM(16bit & 8bit).
- Interface support for byte addressable 16bit devices (UB_N & LB_N signals).
- 2Mbytes of memory per chip select.
- Support for 8 bit/16bit wide NAND flash.
- Support for parallel LCD interfaces, port mapped of memory mapped(18 or 16 bit).
2Gb NAND(16bit, Large Block ) flash memory + 1Gb SDRAM (32bit)
1-CS(Chip Select) are used.
The SD bus allows the dynamic configuration of the number of data line from 1 to 4 Bidirectional data
signal. After power up by default, the Device will use only DAT0. After initialization, host can change
the bus width.
Interface Spec
Device Part Name Maker Read Access Time Write Access Time
NAND TYA000BC00DOGG Toshiba 50 ns 30 ns
SDRAM TYA000BC00DOGG Toshiba 15 ns 15 ns
Table#1. External memory interface
- 54 -
3. TECHNICAL BRIEF
Figure. Simplified Block Diagram of Memory Interface
MSM6280
SDRAM
1Gbit
(512M x 2)
NAND
2Gb
(256MB)
DATA[31:0]
ADDRESS[14:0]
WE*
CS*
CAS*
RAS*
CLK_EN
CLK
DQM[3:0]
NAND_CS*
NAND_RE*
NAND_WE*
NAND_CLE
NAND_WP*
NAND_ALE
NAND_READY
DATA[15:0]
EBI1
EBI2
- 55 -
3. TECHNICAL BRIEF
3.10 H/W Sub System
3.10.1 RF Interface
A. RTR6275(WCDMA_Tx, GSM_Tx/Rx)
MSM6280 controls RF part(RTR6275) using these signals.
SBST : SSBI I/F signals for control Sub-chipset
PA_ON1 : Power AMP on RF part
RX0_I/Q_M/P,TX_I/Q_M/P : I/Q for T/Rx of RF
TX_AGC_ADJ : control the gain of the Tx signal prior to the power amplifier
DAC_REF : Reference input to the MSM Tx data DACs
(WCMDA 2100 PAM Enable)
R213
NA
33nF
C223
R211 2K
0 R215
AA1
XMEM1_CS_N1_GPIO76
XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77
Y6
XMEM2_CS_N2_GPIO35
W15
AA15
XMEM2_CS_N3_GPIO36
H6
UART2_DP_RX_DATA_GPIO89
L25
UART3_RFR_N_GPIO87
USB_RX_DATA_GPIO29
N19
B6
SYNTH2_GPIO65
TCK
D16
TCXO_EN_GPIO94
F19
TDI
D15
TDO
A17
TMS
F15
TRK_LO_ADJ
L13
H15
TRST_N
H13
TX_AGC_ADJ
TX_ON_GRFC10
H12
F18
SYNTH0_GP_PDM0_GPIO92
RTCK
H16
SBDT1_GPIO1
SBST1_GPIO93
H18
PA_ON0
F17
PA_ON1_GPIO2
H11
AA25
Q_IM_CH0
Q_IM_CH1
W23
Y25
Q_IP_CH0
Q_IP_CH1
V23
B12
Q_OUT
A12
Q_OUT_N
AE13
LCD_EN_GPIO37
A22
AB25
I_IM_CH0
V25
I_IM_CH1
AC25
I_IP_CH0
I_IP_CH1
W25
I_OUT
B13
I_OUT_N
A13
D17
GP_PDM2_PA_RAN_GE1
B8
GRFC0_GPIO3
A8
GRFC1_AUX_SBDT_GPIO4
D9
GRFC2_GPIO5
GRFC3_GPIO6
F10
GRFC4_AUX_SBCK_GPIO7
H10
D11
GRFC5_AUX_SBST_GPIO8
GRFC7_GPIO10
T23
B4
GRFC8_GPIO11
D5
GRFC9_GPIO12
GRFX6_GPIO9
T19
F8
GPIO66
GP_PDM1_PA_RAN_GE0
H17
F12
DAC_REF
A6
GPIO28
H9
GPIO43
R19
BT_DATA_GPIO20
E26
BT_SBCK_GPIO23
BT_SBDT_GPIO22
E25
F23
BT_SBST_GPIO24
BT_TX_RX_N_GPIO21
H21
CAMCLK_PO_GP_MN_GPIO13
J21
AUX_PCM_CLK_GRFC14_GPIO80
K19
N21
AUX_PCM_DIN_GRFC13_GPIO14
G4
AUX_PCM_DOUT_GRFC12_GPIO103
AUX_PCM_SYNC_GRFC11_GPIO102
J8
G23
BT_CLK_GPIO25
MMP_INT_N
RMT_INT
CAM_MCLK
LCD_RESET_N
VGA_CAM_RESET_N
CAM_SELECT_N
MICROSD_DETECT
VGA_CAM_PWDN
BT_DATA
BT_SBDT
BT_SBCK
BT_SBST
BT_TX_RX_N
BT_CLK
MMP_HPCM_FSYNC
LCD_LDO_EN
MMP_HPCM_DI
MMP_HPCM_CLK
MMP_HPCM_DO
RX_IM
RX_IP
RX_QM
RX_QP
DAC_REF
PA_ON
TCXO_EN
TRK_LO_ADJ
TX_AGC_ADJ
LIN_INVERTER
HOOK_SENSE_N
LCD_IF_MODE
CAM_MODE1_N
CAM_MODE3_N
HP_AMP_EN
TX_QM
TX_IM
GSM_PA_EN
TX_QP
TX_IP
ANT_SEL2
GSM_PA_BAND
FM_INTX
TX_ON
PA_R1
ANT_SEL0
ANT_SEL1
FM_BUSEN
USB_SELECT_N
LIN_PWM_MAG
LIN_MOTOR_EN
Figure. Schematic of RF Interface of MSM6280
- 56 -
3. TECHNICAL BRIEF
B. the others
TRK_LO_ADJ : TCXO(19.2M) Control
PA_ON : WCDMA(2100) TX Power Amp Enable
ANT_SEL[0-2] : Ant Switch Module Mode Selection(WCDMA,GSM Tx/Rx,DCS-PCS Tx/Rx)
GSM_PA_BAND : GSM/DCS-PCS Band Selection of Power Amp
GSM_PA_RAMP : Power Amp Gain Control of APC_IC
GSM_PA_EN : Power Amp Gain Control Enable of APC_IC
- 57 -
3. TECHNICAL BRIEF
3.10.2 MSM Sub System
3.10.2.1. USIM Interface
SIM interface scheme is shown in Figure.
And, there control signals are followed
USIM_CLK : USIM Clock
USIM_Reset : USIM Reset
USIM_Data : USIM Data T/Rx
3.10.2.2 UART Interface
UART signals are connected to MSM GPIO through IO connector with 115200 bps speed.
MSM6280
PM6650
USIM
USIM CLK
USIM Reset
USIM Data
USIM Data
USIM Reset
USIM CLK
VREG_UIM 2.85V
Figure. SIM Interface
GPIO_Map Name Note
GPIO_96 UART_RXD Data_Rx
GPIO_95 UART_TXD Data_Tx
Table. UART Interface
- 58 -
3. TECHNICAL BRIEF
3.10.2.3 USB
The MSM6280 device contains a Universal Serial Bus (USB) interface to provide an efficient
interconnect between the mobile phone and a personal computer (PC). The USB interface of the
MSM6280 was designed to comply with the definition of a peripheral as specified in USB Specification,
Revision 1.1. Therefore, by definition, the USB interface is also compliant as a peripheral with the USB
Specification, Revision 2.0. The USB Specification Revision 1.1 defines two speeds of operation,
namely low-speed (1.5 Mbps) and full-speed (12 Mbps), both of which are supported by the
MSM6280.
Name Note
USB_DAT Data to/from MSM
USB_SE0 Data to/from MSM
USB_OE_N Out-Put Enable of Transceiver
USB_VBUS USB_Power From Host(PC)
USB_D+ USB Data+ to Host
USB_D USB Data- to Host
Table. USB Signal Interface
Figure. Schematic of USB block(MSM6280 Side & PM6650 Side)
U
S
B
_
D
A
T
_
V
P
N
2
6
N
2
5
U
S
B
_
O
E
_
T
P
_
N
U
S
B
_
S
E
0
_
V
M
N
2
3
M
1
6
M
M
C
_
C
L
K
_
S
D
C
C
M
M
C
_
C
M
D
_
G
P
I
O
H
1
4
L
1
4
M
M
C
_
D
A
T
A
_
S
D
C
G
P
I
O
4
0
D
6
D
7
G
P
I
O
4
2
P
M
_
I
N
T
_
N
P
S
_
H
O
L
D
U
S
B
_
S
E
0
U
S
B
_
D
A
T
U
S
B
_
O
E
_
N
I
C
R
O
S
D
_
C
M
D
O
S
D
_
D
A
T
A
[
0
]
M
I
C
R
O
S
D
_
C
L
K
USB_CTL_N
USB_VBUS
16
USB_DAT
17
USB_D_P
18
19
USB_SE0
USB_D_M
20
GP1_DRV_N(M
21
4
.
7
u
C
5
4
0
4
7
K
R
5
1
4
USB_VBUS
USB_DAT
MSM_USB_D+
USB_SE0
MSM_USB_D-
- 59 -
3. TECHNICAL BRIEF
3.10.3 HKADC(House Keeping ADC)
The MSM6280 device has an on-chip 8-bit analog-to-digital converter (HKADC) which is tended to
digitize DC signals corresponding to analog parameters such as battery voltage, temperature, and RF
power levels. The MSM6280 device has six analog input pins which are multiplexed to the input of the
internal HKADC.
Figure. MSM6280HKADC Block diagram
Table. HKADC channel table
PCB Version Check PCB_Rev_ADC HKADC4
ADC Reference voltage REF_ADC HKADC2
Ear jack Detection for TTY TTY_ADC_DET HKADC3
Battery Temperature Check
Battery voltage level
RF PAM Temperature Check
Note
Battery_THERM
VBATT_SENSE
AMUX_OUT
Signal
HKADC5
HKADC1
HKADC0
Channel
3.10.4 Key Pad
There are 5 key buttons. Shows the Key Matrix & Keypad circuit.
END Key is connected to PMIC(PM6650).
- 60 -
3. TECHNICAL BRIEF
Table. Key Matrix Mapping Table
Figure. Main Keypad Circuit
CLR SEND ROW(2)
AF ROW(1)
Capture
Lock ROW(0)
COL(1) COL(0)
CLR SEND
R
7
0
1
5
1
K
701 700
V
A
7
0
2
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
1
E
V
L
C
1
4
S
0
2
0
5
0
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
3
KEY_ROW[2]
VREG_MSMP_2.7V
KEY_COL[0]
KEY_COL[1]
- 61 -
3. TECHNICAL BRIEF
Figure. Side Keypad Circuit
LOCK KEY
FOCUS
CAMERA
SW1100
KEY_ROW[1]
KEY_ROW[0]
KEY_COL[0]
KEY_COL[1]
1100
Figure. END Keypad Circuit
END
ON_SW KEY
E
V
L
1
4
K
0
2
2
0
0
V
A
7
0
0
END
PM_ON_SW_N
3.10.5 Camera Interface
U990 Installed a 5M Pixel and 0.3Mega Camera.
Below figure shows the camera board to board connector and camera I/F signal.
- 62 -
3. TECHNICAL BRIEF
Figure. Camera PCB Board to Board Connector
GB042-30S-H10-E3000
1
u
CAM_VDD_SA_2.7V
CAM_VDD_IO_2.7V
C
6
0
8
C605
0.1u
10p
C610
30
17
18
19
20
21
22
23
24
14
15
2
3
4
5
6
7
8
9
16
25
26
27
28
29
CN600
1
10
11
12
13
0.1u
C612
C606
10p
R601 10
R607
33
0.1u
C607
10p
C611
CAM_VDD_AF_2.7V
CAM_VDD_CORE_1.2V
V
A
6
0
1
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
V
A
6
0
2
C614
E
V
L
C
1
8
S
0
2
0
1
50.1u
C601
0.1u
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
V
A
6
0
0
10u
C600
R604 10
CAM_VDD_SD_1.8V
10 R603
10p
C613
C
6
0
9
0
.
1
u
R608 10
C602
1u
R602 10
STROBE_TRIGGER
MMP_CAM_PCLK
5M_CAM_DATA[0] 5M_CAM_DATA[1]
MMP_CAM_RESET_N MMP_CAM_INT
MMP_CAM_HSYNC
MMP_CAM_VSYNC
MMP_I2C_SDA
MMP_I2C_SCL
5M_CAM_MCLK
10 R719
VGA_VDD_2.7V
R725 10
10 R724
16
25
26
27
28
29
30
17
18
19
20
21
22
23
24
1
10
11
12
13
14
15
2
3
4
5
6
7
8
9
CN701
C711
0.1u 10p
C713
R718 10
E
V
L
C
1
8
S
0
2
0
1
5
V
A
7
1
5
R
7
2
9
NA
r
e
s
i
s
t
o
r
10p
C715
10
R717
V
A
7
1
4
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
10 R720
C712
10p
E
V
L
C
1
8
S
0
2
0
1
5
V
A
7
1
3
C709
0.1u
VGA_VDD_1.8V
C714
10p 0.1u
C710
VGA_CAM_DATA[2]
VGA_CAM_DATA[3]
VGA_CAM_DATA[4] VGA_CAM_DATA[7]
I2C_SDA
I2C_SCL
MMP_CAM_VSYNC
MMP_CAM_HSYNC
VGA_CAM_RESET_N
RCV+
RCV-
MOTOR+
MOTOR- x+
x-
Y+
Y-
VGA_CAM_DATA[6]
VGA_CAM_PWDN
VGA_CAM_DATA[5]
VGA_CAM_MCLK
MMP_CAM_PCLK
VGA_CAM_DATA[0]
VGA_CAM_DATA[1]
- 63 -
3. TECHNICAL BRIEF
The MEGA Camera module is connected to Main PCB with 30pin Board to Board connector Its
interface is dedicated camera interface port in Multimedia chip. The camera port supply 13MHz master
clock to camera module, vertical sync signal, horizontal sync signal, reset signal and 8bits data from
camera module. The camera module is controlled by I2C port from Multimedia chip.
[ Pin Description ]
Table. Interface between MEGA Camera Module and MAIN PCB (in camera module)
The VGA Camera module is connected to FPCB with 20pin Board to Board connector (AXK720147G).
Its interface is dedicated camera interface port in MSM6280. The camera port supply 13.MHz master
clock to camera module and receive 13MHz pixel clock (15fps), vertical sync signal, horizontal sync
signal, reset signal and 8bits data from camera module. The camera module is controlled by I2C port
from MSM6280.
[ Pin Description ]
- 64 -
3. TECHNICAL BRIEF
Table. Interface between VGA Camera Module and FPCB (in camera module)
Camera I/O Power I VREG_CAM_2.8V 20
Camera I/O Power I VREG_MSMP_2.8V 19
Camera reset signal I CAM_RESET_N 18
I2C Clock I I2C_SCL 17
GND GND GND 15
I2C Clock I I2C_SCD 16
GND GND GND 3
Clock for Camera Data Out(13M) O CAM_PCLK 4
Data O CAM_DATA(0) 5
Horizontal Sync O CAM_HSYNC 14
Vertical Synch O CAM_VSYNC 13
Master Clock(24M) I CAM_MCLK 2
Camera power down i CAM_PWDN 1
Note Port Name No
- 65 -
3. TECHNICAL BRIEF
3.10.6 LCD Module (LS030B3UX01 : SHARP)
- The IM220DBN2A model is a Color TFT Main supplied by SHARP.
This LCD Module has a 3.0 inch diagonally measured active display area with 240(RGB)X400
resolution. each pixel is divided into Red, Green and Blue sub-pixels and dots which are arranged in
vertical stripes.
* Features
- Display mode(Main LCD) : Normally Black, Transmissive VA mode 265K colors
- LCD Driver IC: LS030B3UX01(Magnachip)
- Driving Method : A-Si TFT Active Matrix
- 16 bit CPU interface Parallel
Figure. LCD Module Block Diagram
EBI2_OE_N
EBI2_WE_N
EBI2_ADDR[11]
EBI2_DATA[0:15]
MMP_CS_N
LCD_RESET_N
LCD_MAKER_ID
LCD_IF_MODE
MMP_LCD_CS_N
MMP_LCD_RD_N
MMP_LCD_WE_N
MMP_LCD_ADS
MMP_LCD_DATA[0:15]
MSM6280
Multimedia
Chip
LCD 3.0
TFT(WQVGA)
- 66 -
3. TECHNICAL BRIEF
3.10.7 Display
LCD module is connected to Main PCB with 40 pin B TO B connector The LCD module is controlled by
16-bit EBI2 in MSM6280 via Multimedia Chip.
OTP Program Pin
ENBY0036001
1.0T, Socket
GB042-40S-H10-E3000
7
INOUT_B3
INOUT_B4
6
FL301 ICVE10184E150R500FR
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
C
3
2
2
2
2
p
C
3
2
3
2
2
p
R315 51
2
2
p
C
3
2
5
VA300
ICVN0505X150FR
25
26
27
28
29
9
21
30
31
32
33
34
35
36
37
38
39
22
40
23
24
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
CN300
1
10
11
VA301
51 R314
NA
C320
C326
22p
G
2
1
INOUT_A1
INOUT_A2
2
3
INOUT_A3
INOUT_A4
4
INOUT_B1
9
8
INOUT_B2
INOUT_B3
7
6
INOUT_B4
ICVE10184E150R500FR FL303
5
G
1
1
0
51 R316
R318 0
5
G
1
1
0
G
2
1
INOUT_A1
INOUT_A2
2
3
INOUT_A3
INOUT_A4
4
INOUT_B1
9
8
INOUT_B2
INOUT_B3
7
6
INOUT_B4
51 R317
2
2
p
C
3
2
4
0.1u
C321
6
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
7
INOUT_B3
INOUT_B4
LCD_VDD_2.8V
LCD_VSYNC_OUT
LCD_MAKER_ID
MMP_LCD_WE_N
MMP_LCD_VSYNC_OUT
WLED_PWR
WLED_2
WLED_4
WLED_5
MMP_LCD_VSYNC_IN
LCD_IF_MODE
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[14]
LCD_DATA[15]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
LCD_DATA[12]
LCD_DATA[13]
WLED_1
WLED_3
MMP_LCD_ADS
MMP_LCD_CS_N
LCD_RESET_N
MMP_LCD_RD_N
MMP_LCD_DATA[9]
MMP_LCD_DATA[10]
MMP_LCD_DATA[11]
MMP_LCD_DATA[12]
MMP_LCD_DATA[13]
MMP_LCD_DATA[14]
MMP_LCD_DATA[15]
LCD_DATA[12]
LCD_DATA[13]
LCD_DATA[14]
LCD_DATA[15]
MMP_LCD_DATA[0]
MMP_LCD_DATA[1]
MMP_LCD_DATA[2]
MMP_LCD_DATA[3]
MMP_LCD_DATA[4]
MMP_LCD_DATA[5]
MMP_LCD_DATA[6]
MMP_LCD_DATA[7]
MMP_LCD_DATA[8]
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
- 67 -
3. TECHNICAL BRIEF
3.10.7.1 Audio Signal Processing & Interface
Audio signal processing is divided uplink path and downlink path.
The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal
and then transmits it to DBB Chip (MSM6280).
This transmitted signal is reformed to fit in GSM & WCDMA frame format and delivered to RF Chipset.
The downlink path amplifies the signal from DBB chip (MSM6280) and outputs it to receiver (or
speaker). The receive path can be directed to either one of two earphone amplifiers or the auxiliary
output. The outputs earphone1 (EAR1OP, EAR1ON) and auxiliary out (LINE_OP, LINE_ON) are
differential outputs. Earphone2 (HPH_L, HPH_R) is a single-ended output stage designed to drive a
headset speaker.
The microphone interface consists of two differential microphone inputs, one differential auxiliary input
and a two-stage audio amplifier.
Figure. Audio Interface Detailed Diagram(MSM6280)
- 68 -
3. TECHNICAL BRIEF
Figure . Audio part schematics
MSM6280 Audio CODEC pins
0
.
1
u
C
2
3
5
C
2
3
6
0
.
1
u
L200
100nH
N
A
C
2
0
3
C200
10p
SDCC_DAT
SDCC DAT2
M
I
C
1
N
A
F
2
0
M
I
C
1
P
A
E
2
0
A
F
2
1
M
I
C
2
N
A
F
2
2
M
I
C
2
P
M
I
C
B
I
A
S
T
1
5
L
I
N
E
_
L
_
I
N
A
C
2
1
A
C
2
2
L
I
N
E
_
L
_
I
P
A
C
1
8
L
I
N
E
_
O
N
L
I
N
E
_
O
P
A
C
1
7
A
C
2
0
L
I
N
E
_
R
_
I
N
L
I
N
E
_
R
_
I
P
A
C
1
9
H
P
H
_
L
W
1
7
A
A
1
7
H
P
H
_
R
H
P
H
_
V
R
E
F
A
A
1
9
E
A
R
1
O
N
A
E
1
8
E
A
R
1
O
P
A
F
1
8
C
C
O
M
P
A
A
2
0
A
F
1
9
A
U
X
I
N
A
E
1
9
A
U
X
I
P
A
U
X
O
U
T
A
A
1
8
H
P
_
R
H
P
_
L
M
I
C
1
P
M
I
C
1
N
M
I
C
2
P
R
C
V
+
R
C
V
-
M
I
C
B
I
A
S
S
P
K
_
L
S
P
K
_
R
- 69 -
3. TECHNICAL BRIEF
MIC
10u
C563
C568 22n
C569
NA
C564
47p
2
G1
3
G2
1
O
4
P
SPM0204HE5-PB-3
MIC500
33p
C575
10p
C576
C567 22n
MICBIAS
MIC1P
MIC1N
Headset Hook Switch
R905
10K
VREG_MSMP_2.7V
R907
5.1K
C905
0.1u
1
0
0
K
R
9
0
6
1
M
R
9
0
4
2
GND
1
OUT
VCC
5
3 VIN+
VIN- 4
U902
NCS2200SQ2T2G
HOOK_SENSE_N
EAR_MIC_P
3. TECHNICAL BRIEF
- 70 -
AUDIO DAC/ADC, AMP etc. (WM8983)
FB501
FB500
NA
C550
0.1u
C514
C535 1u
C532 1u
R2_GPIO3
6
RIN
5
4
RIP
ROUT1
29
ROUT2
23
16
SCLK
SDIN
17
27
VMID DACDAT
10
DBVDD
14
DCVDD
13 12
DGND
L2_GPIO2
3
LIN
2
1
LIP
LOUT1
30
25
LOUT2
7
LRC
11
MCLK
MICBIAS
32
18
MODE
OUT3
22
21
OUT4
33
PGND
U502
ADCDAT
9
28
AGND1
24
AGND2
AUXL
19
AUXR
20
31
AVDD1
AVDD2
26
8
BCLK
15
CSB_GPIO1
4.7u
C520
WM8983
C533
4.7n
R511
18K
R533
0
10u
C525
C
5
3
4
1
u
10u
C513
1
0
0
K
R
5
1
9
4.7n
C542
NA
C531
1K
R516
R510
1K
C541
1u
1u
C549
1u C548
C536 1u
C518
4.7u
C
5
3
9
1
u
12n
C547
C524
0.1u
NA
C544
C519
0.1u
C551
NA
C521
0.1u
C543
NA
12n
C530
18K
R517
C516
4.7u
C517
0.1u
MIC_PWR
MMP_A_MCLK
CODEC_I2C_SCL
CODEC_I2C_SDA
HP_R
HP_L
HP_EAR_L
MIC2P
HP_EAR_R
MID_MICP
SPK_L
SPK_R
FM_AUDIO_L
FM_AUDIO_R
MMP_A_BCLK
MMP_ADO_DACDAT
MMP_A_LRCLK
MMP_ADI_ADCDAT
SPK_OUT-
SPK_OUT+
VREG_5V
VREG_WM_2.7V
VREG_MSME_1.8V
MIDI_3.3V
19
2
21
3
4
5
6
7
CN500
1
R
5
2
8
1
0
0
K
FB504
VREG_MSMP_2.7V
2.2uH
L504
TV_OUT
EAR_MIC_P
RMT_INT-USB_D+
FM_ANT
MIDI_EAR_L
MIDI_EAR_R
3.10.7.2 Audio Mode
There are three audio modes (Voice call, speaker phone, MIDI/MP3).
Audio & Sound Main Component
There are 8 main components in KU990R.
3. TECHNICAL BRIEF
- 71 -
Table. Audio Mode
Table. Audio main component list
Headset MP3 Headset
Headset MIDI Bell Headset
Speaker MP3 Loud Mode
MP3
Speaker MIDI Bell Loud Mode
MIDI
Speaker Phone Loud Mode
Headset Voice Call Headset
Speaker Phone Loud Mode Speaker phone
Receiver Voice Call
Description
Receiver Mode
Voice Call
Device MODE
-42 dB microphone SPOB-413S42-
RC3310BC
CAM MIC 7
32 ohm receiver EMR0906SP Receiver 5
8 ohm Speaker EMS1634APB1 Speaker 4
-42 dB microphone SPM0204HE5-PB Main MIC 6
Ear MIC HC-MQD-LG059 Ear MIC 8
Analog Switch for MIC BIAS NC7SB3157L6X Analog Switch 3
ADC/DAC, AB class SPK AMP
Base-Band Modem
Note
WM8983
MSM6280
Maker Part No.
Audio Codec
MSM6280
Component
2
1
3. TECHNICAL BRIEF
- 72 -
# Multimedia Chip
3.11 Feature List
3.11.1 IC Characteristics
MCP with Internal SDRAM, no need for external memory.
Package: 180-pin TFBGA (8 x 8 mm)
90nm process
Core voltage - 1.0 V
IO voltage - Eleven strips, separate voltage between 1.8 and 3.3 V
3.11.2 Multimedia Performance
Digital Still Camera support with ISP on chip up to 5M pixel.
- Photo-album and photo-editing capabilities.
- Superior quality, (e.g. including lens shading).
- Camera controls for flash, optical zoom,focus, shutter and iris.
Camcorder operation as a DivX recorder /player at 30 fps CIF, VGA resolution.
AVI file format with MP3 audio.
Player for general DivX content, up to 30 fps CIF resolution. MP3 or WMA audio.
3GPP MMS compliant video clip recorder, supporting CIF/QCIF H.263, MPEG4 recording with AMR
voice or AAC audio.
Player for 3GPP MMS / streaming video clips, up to 30 fps CIF H.263, MPEG4, and H.264 with AMR
voice or AAC/Enhanced AACPlus audio.
3GPP-compliant videophone, with H.263 or MPEG4 video at QCIF 15 fps (full-duplex).
MIDI player (for ring tones, melodies).
Compliant with 3GPP standards, including
support for Mobile XMF for melodies with custom instruments.
3. TECHNICAL BRIEF
- 73 -
Audio stereo recorder player MP3/WMA
ID3 tags display
Spectral bars
Lyrics display
Equalizer
3D Surround Audio
3.11.3 DRM
MDTV Conditional access compliant to JSR-177 (AES and TDES)
Key exchange support
True RNG (Random Number Generator)
3.11.4 3D Graphics
3D hardware + software accelerator targeting VGA 30 fps games with PlayStation
TM
-1 enhanced
quality.
- Setup and viewport transforms
- Bilinear and Trilinear texturing
- Multi-texturing
- Flat and Gourard shading
- 24-bit ARGB support
- Compressed textures (2 bits/texel)
- Mipmaping
- Full scene anti-aliasing (x4 / x16)
- 16-bit Z-buffer
- 4-bit stencil buffer
- Fog
- Alpha blending
- Dot3 bump mapping
Fill rate: 120M pixels/sec
Polygon rate 0.8M triangles/sec
3. TECHNICAL BRIEF
- 74 -
3.11.5 Image Sensor
10/12/14/16-bit RGB - Bayer Grid
- CMOS up to 5MP
- CCD up to 5MP
- Pixel clock - Up to 90 MHz.
- Active pixel rate - up to 75M pixels/sec:
- 15fps @ 5MP
- 25fps @ 3MP
- 30fps @ 2MP
- Black-level evaluation and correction
- Defective pixel correction
- Auto exposure and White-balance
- Edge enhancement and auto focus.
- Lens shading correction
- Polyphase image scaling.
- Digital zoom up to X4 in 16 steps
- 8/16-bit YCbCr - 4:2:2
- Input streaming bus - as CCIR601
- Progressive (CMOS/CCD sensors) or interlaced (PAL/NTSC decoders) mode
- Pixel clock - Up to 120 MHz (8-bit), 60Mhz (16-bit)
- Input resolution - Up to 5M pixels
- Auto focus
- Polyphase image scaling
- Digital zoom up to X4 in 16 steps
3.11.6 LCD Port
Output resolution - up to VGA
Supports dual-panels (two LCDs)
Bypass from Host port to LCD CPU bus
Up to 18-bit color depth (262K colors)
CPU bus 8/9/16/18 bit compliant to all known vendors.
RGB bus 3/6/18 bit up to 30Mhz clock
3.11.7 TV-out Port
Composite analog interface
- NTSC-M
- PAL-B,D,G,H,I
3. TECHNICAL BRIEF
- 75 -
3.11.8 Video and Graphics Postprocessing
Handles Video (YUV) and Graphic (RGB)
Video de-blocking
Blending of video and graphics - up to 256 levels of blending
Resizing (upscale and downscale) using quality polyphase filter
Rotation and flip - 90, 180 and 270 degrees
Picture brightness, contrast, and saturation control
Display gamma adjustment
Color space reduction
3.11.9 Serial Audio Ports
ZR3453X has two audio/voice ports: one port is used for host bypass connection, and another for
connecting to a codec or to a Bluetooth voice port.
- PCM master/slave
- I2S master/slave (5 lines including clock)
- AC97 master (5 lines including AC-Link reset)
- Audio output master clock (I2S), up to 48 MHz
- Supports sample rates of 8, 11.025, 16, 22.05, 24, 32, 44.1 or 48 kHz
3.11.10 Serial Data Ports
I2C Multiple device support 100 and 400 kHz
UART with flow control up to 3Mb/sec
SPI port with Bit clock up to 40 MHz
- (Motorola, National microwire, TI synchronous serial interface )
3.11.11 Mass Storage
High-speed SD/MMC I/F
NAND-flash storage
SPI-flash
CE-ATA HDD.
SDIO peripherals
3.11.12 USB
USB 2.0 High speed/full speed
USB On The Go
USB applications:
- USB mass storage
- PictBridge
- Webcam
3.11.13 Host Port
Two flavors:
- Generic interface 8/16-bit Intel style.
Connects as memory map (4-bit address)
- LCD like 8/9/16 bit multiplexed bus.
Connects as an LCD (1-bit address)
3.11.14 Clocks
Main clock input frequency, 10 to 31 MHz:
- Directly from system PMU main clock and bypass its control
- Embedded crystal oscillator (12Mhz)
- Optional GPS TCXO
Four configurable clock-out pins to drive external components:
(e.g. Audio codec, Sensor, PWM)
3.11.15 Boot
Host boot
Standalone boot
3.11.16 Debug
JTAG for code debug
UART for fast system ramp up
3.11.17 Power
Very low power consumption, smaller than150mW for all intense multimedia applications.
Low power sleep mode 100 W
- Host can control display audio and peripherals via bypass
Light sleep mode 500uW
- Specifically for GPS accurate off-line tracking
3. TECHNICAL BRIEF
- 76 -
3. TECHNICAL BRIEF
- 77 -
Figure 1-1 presents a typical multimedia cellular phone system where ZR3453X is used as a co-
coprocessor. In this system, ZR3453X is connected to the following devices:
Baseband chip (the host)
CCD/CMOS Image Sensor for capturing video and still
LCD panel(s)for displaying video
Audio CODEC (A2D, D2A) for capturing voice and playing voice/music
Media Flash (SmartMedia, NANDFlash, MMC or SD) to store media data (two active I/F, e.g. one
NAND and one SD)
Connector to TV
[ Figure 1-1 ]
3.12 Multimedia Chip Interface
3.12.1 Host Interface
3.12.1.1 Host Interface
The HOST interface connects the ZR3453X and the host processor
(a handset baseband
chip) in two optional modes:
On the host memory bus.
On the host LCD bus.
3. TECHNICAL BRIEF
- 78 -
VREG_MSMP_2.7V
M13
NCSN
L13
HGINTN
A7
B7
HRDN
HWRN
B9
HD0
D12
HD1
C10
B12
HD10
A12
HD11
HD12
B11
A11
HD13
HD14
C9
B10
HD15
HD2
C12
C13
HD3
C14
HD4
HD5
B14
HD6
C11
B13
HD7
A14
HD8
HD9
A13
A10
HA11
HA12
A9
C8
HA13
C7
HA14
HCS0N
B8
HCS1N
A8
10K
R310
R311 0
NA R313
NA
R309
MMP_CS_N
MMP_INT_N
MMP_LCD_BYPASS_CS_N
NAND_ALE
EBI2_ADDR[11]
EBI2_ADDR[13]
EBI2_ADDR[14]
EBI2_DATA[0:15]
EBI2_DATA[15]
EBI2_DATA[14]
EBI2_DATA[13]
EBI2_DATA[12]
EBI2_DATA[11]
EBI2_DATA[10]
EBI2_DATA[9]
EBI2_DATA[8]
EBI2_DATA[7]
EBI2_DATA[6]
EBI2_DATA[5]
EBI2_DATA[4]
EBI2_DATA[3]
EBI2_DATA[2]
EBI2_DATA[1]
EBI2_DATA[0]
EBI2_ADDR[12]
EBI2_OE_N
EBI2_WE_N
[ Block Diagram ]
[ Schematics ]
3. TECHNICAL BRIEF
- 79 -
3.12.2 Host - LCD - Bypass mode
The Host-LCD Bypass bypasses the host interface pins to the LCD pins.
This means that the bus transactions performed by the host are transferred to the LCD pins, enabling
the host to have full control over one or two LCD panels, even when the ZR3453X is in sleep mode.
This is the default mode.
3.12.3 Camera interface
ZR3453X connects with the CCD or CMOS Image Sensor (CIS) via its image sensor port.
ZR3453X supports several system configurations:
CCD bayer 10,12,14,16 bit (ZR34532 only)
CMOS bayer 10,12,14,16 bit
YCbCr 8 bit
YCbCr 8 bit with pixel valid
YCbCr 16 bit
3. TECHNICAL BRIEF
- 80 -
3. TECHNICAL BRIEF
- 81 -
3.12.4 LCD Interface
The ZR3453X LCD port supports mobile LCD panels of upto VGA size and upto 60fps refresh rate.
There are various bus formats and color depth up to 18-bit (262K colors).
[ Block Diagram ]
M9
VIDP
VIDH
P11
N12
VIDI
N7
VIDJ
VIDK
L8
P13
VIDL
L9
VIDM
VIDN
N13
VIDO
M11
E3
LVS
C4
LWRN
LD12
C1
LD13
C2
C5
LD14
LD15
C6
D3
LD16
LD17
D1
B6
LD2
LD3
B4
LD4
A4
C3
LD5
A3
LD6
LD7
A2
A1
LD8
LD9
B2
E4
LHS
LRDN
D5
D4
LA0
LACT
E2
LCK
E1
A6
LCS0N
LCS1N
D2
LD0
B5
A5
LD1
LD10
B1
B3
LD11
TP301
TP300
MMP_LCD_CS_N
MMP_LCD_ADS
MMP_LCD_RD_N
MMP_LCD_WE_N
MMP_LCD_VSYNC_IN
MMP_LCD_VSYNC_OUT
MMP_LCD_DATA[15]
MMP_CAM_DATA[7]
MMP_CAM_DATA[6]
MMP_CAM_DATA[5]
MMP_CAM_DATA[4]
MMP_CAM_DATA[3]
MMP_CAM_DATA[2]
MMP_CAM_DATA[1]
MMP_CAM_DATA[0]
MMP_LCD_DATA[0]
MMP_LCD_DATA[1]
MMP_LCD_DATA[2]
MMP_LCD_DATA[3]
MMP_LCD_DATA[4]
MMP_LCD_DATA[5]
MMP_LCD_DATA[6]
MMP_LCD_DATA[7]
MMP_LCD_DATA[8]
MMP_LCD_DATA[9]
MMP_LCD_DATA[10]
MMP_LCD_DATA[11]
MMP_LCD_DATA[12]
MMP_LCD_DATA[13]
MMP_LCD_DATA[14]
[ Schematics ]
- 82 -
3. TECHNICAL BRIEF
3.12.5 TV out Interface
The display data is converted to video with video-encoder according to CCIR-601 and sampled by 10-
bit DAC and transmitted over an analog pad as a composite video signal.
This mode is used in a system where ZR3453X is connected gluelessly to a TV screen that requires
real-time display data. ZR3453X generates TV signal according to the NTSC and PAL standards.
The TVDATA pin can drive a full video level signal directly into a 75 terminated TV cable.
[ Block Diagram ]
392ohm 1%
330p
C335
E
1
3
V
E
N
B
Y
P
I
N
TVDATA
G14
TVREF
F13
22p
C331
R
3
3
9
3
9
0
330p
C334
R
3
3
8
7
5
2.2uH
L300
TV_OUT
[ Schematics ]
- 83 -
3. TECHNICAL BRIEF
3.12.6 Audio Interface
In this configuration ZR3453X is connected to an external audio codec.
There are three possible configurations:
Audio/Voice codec with two ports: PCM and I2S
Audio/Voice codec with one port: I2S
Audio/voice/data codec with one port: AC97
In all configurations ZR3453X connects its external audio ports to the codec single or two
ports.
The host uses its internal voice codec for voice communication. There is no bypass of voice.
The host controls the codec configuration via I2C bus directly. The host codec analog audio output is
connected to the external audio codec and muxed with the codec audio path from the ZR3453X on the
way is to the speaker.
The microphone is connected to the external audio codec and the baseband internal codec.
ZR3453X appears in Figure 3-35 as a master on the bit clock and frame sync. This is only one of the
possible configurations. In external audio configuration ZR3453X can run all the Audio/voice
applications including conversation recording .
- 84 -
3. TECHNICAL BRIEF
3.12.7 USB interface
ZR3453X is a USB 2.0 Device or On-the-Go dual-role device (OTG) with the following
characteristics:
Complies with USB (Universal Serial Bus) 2.0 specifications
Complies with On-the-Go Supplement 1.0a
Integrated 45-ohm termination, 1.5Kilohm pull-up and 15-Kilohm pull-down resistors.
Supports 480-Mbps high-speed, 12-Mbps full-speed and 1.5Mbps low-speed (Host mode only) data
transmission rates.
Control + 4 endpoints:
- EP0 - two-way Control
- 2-input , 2-output - Bulk, INT or ISO
Suspend, resume, reset and SOF signaling
3.4K
1%
UDN
P4
P3
UDP
P6
UID
URSET
M7
J4
UVBUS
L
5
A
G
N
D
_
U
S
B
C
K
5
A
G
N
D
_
U
S
B
T
F
1
2
A
G
N
D
_
V
D
A
C
R
3
4
0
3
.
3
K
R335 0
MMP_USB_D+
MMP_USB_D-
VREG_5V
+VPWR
1
0
0
K
R
3
4
5
U304
D+
3
D-
5
GND
4
1
HSD1+
7
HSD1-
2
HSD2+
HSD2-
6
SEL
10
9
VCC
8
_OE
FSUSB30UMX
0.01u
C336
USB_SELECT_N
MSM_USB_D-
MMP_USB_D-
USB_D+
USB_D-
MSM_USB_D+
MMP_USB_D+
- 85 -
3. TECHNICAL BRIEF
3.12.8 MMC interface
ZR3453X has a dedicated port for multimedia cards. It can support SD (Secure Digital) cards and
SecureMMC (standard multimedia cards with security functions).
The same port can be used for HDD CE_ATA connecti on or SDIO to peri pheral devi ces
(e.g.; MDTV front-end).
MMC
MMC v4
Dual voltage (separate IO power domain, host GPIO control)
1 or 4 bit cards
Multiple cards support (if dual-voltage or high-speed interface are not used)
Up to 43 MHz bit clock
SD
1 or 4 bit bus support
High-Speed SD, up to 43 MHz bit clock
3.12.9 Power Domain
VMCLK
P12
P10
VPCLK
VVS
K12
M12
VHREF
SCLK
G1
H2
SCMD
SDAT0
F1
SDAT1
F2
SDAT2
E5
F3
SDAT3
G3
SWP
R312 33
MMP_CAM_MCLK
MMP_CAM_HSYNC
MMP_CAM_PCLK
MMP_CAM_VSYNC
MMP_MICROSD_CLK
MMP_MICROSD_DATA[3]
MMP_MICROSD_DATA[2]
MMP_MICROSD_DATA[1]
MMP_MICROSD_DATA[0]
MMP_MICROSD_CMD
- 86 -
3. TECHNICAL BRIEF
3.13 Touch Screen Interface
The TSC2007 device has a 12-bit analog-to-digital resistive touch screen converter including drivers
and the control logic to measure touch pressure. The TSC2007 device is controlled by I2C port from
MSM6280.
Touch Screen interface scheme is shown in Figure.
And, there control signals are followed
TOUCH_I2C_SCL : I2C CLOCK
TOUCH_I2C_SDA : I2C DATA
TOUCH_PENIRQ_N : DETECT
Figure. Touch Screen Interface
T
P
2
0
0
G
6
U
A
R
T
2
_
C
T
S
_
N
_
G
P
I
O
9
0
U
A
R
T
2
_
D
P
_
T
X
_
D
A
T
A
_
G
P
I
O
8
8
E
4
U
A
R
T
2
_
R
F
R
_
N
_
G
P
I
O
9
1
F
4
L
2
3
U
A
R
T
3
_
C
T
S
_
N
_
G
P
I
O
8
6
M
2
1
U
A
R
T
3
_
D
P
_
R
X
_
D
A
T
A
_
G
P
I
O
8
5
U
A
R
T
3
_
D
P
_
T
X
_
D
A
T
A
_
G
P
I
O
8
4
M
1
9
F
1
4
G
P
I
O
6
4
G
P
I
O
3
9
F
7
G
P
I
O
4
0
D
6
D
7
G
P
I
O
4
4
D
8
V
G
A
_
C
A
M
_
P
W
R
_
E
N
U
A
R
T
_
T
X
D
T
O
U
C
H
_
I
2
C
_
S
C
L
T
O
U
C
H
_
P
E
N
I
R
Q
_
N
T
O
U
C
H
_
I
2
C
_
S
D
A
C
A
M
_
M
O
D
E
2
_
N
U
S
I
M
_
D
A
T
A
P
M
_
I
N
T
_
N
U
S
I
M
_
C
L
K
U
S
I
M
_
R
S
T
_
N
0
R
7
0
0
A0
A1
C2
A1
AUX
GND
D2
PENIRQ-
B1 D1
SCL
C1
SDA
VDD_REF
A2
A3
X+
C3
X-
B3
Y+
D3
Y-
TSC2007IYZGR U700
B2
0.1u
LCD_VDD_2.8V
C701
R
7
0
3
2
.
7
K
N
A
R
7
0
2
C700
1u
2
.
7
K
R
7
0
4
X-
Y-
Y+
X+
TOUCH_PENIRQ_N TOUCH_I2C_SCL
TOUCH_I2C_SDA
- 87 -
3. TECHNICAL BRIEF
3.14 Lens Cover Detection Interface
The A3212EELLT device is an ultra-sensitive, pole in dependent Hall-effect switch with a latched
digital output. The A3212EELT device is controlled by the change of magnetic flux.
Lens Cover Detection interface scheme is shown in Figure.
And, a control signals are followed
CAM_COVER_DET : lens cover open/close detection signal
MSM6280
Hall IC
(A3212EELLT)
Lens Cover
OPEN
CLOSE
CAM_COVER_DET
Figure. Lens cover detection Interface
P
1
6
U
A
R
T
1
_
C
T
S
_
N
_
G
P
I
O
9
7
U
A
R
T
1
_
D
P
_
R
X
_
D
A
T
A
_
G
P
I
O
9
6
M
2
3
U
A
R
T
1
_
D
P
_
T
X
_
D
A
T
A
_
G
P
I
O
9
5
L
2
6
P
2
1
U
A
R
T
1
_
R
F
R
_
N
_
P
A
_
P
O
W
E
R
_
C
T
L
_
M
_
G
P
I
O
9
8
F
1
4
G
P
I
O
6
4
G
P
I
O
3
9
F
7
G
P
I
O
4
4
D
8
C
A
M
_
C
O
V
E
R
_
D
E
T
U
A
R
T
_
T
X
D
U
A
R
T
_
R
X
D
T
O
U
C
H
_
P
E
N
I
R
Q
_
N
C
A
M
_
M
O
D
E
2
_
N
U800
A3212EELLT-T
G1
G2 OUT
VDD
1
0
0
K
R
3
1
8
VREG_MSMP_2.7V
10p
C349 C348
0.1u
CAM_COVER_DET
- 88 -
3. TECHNICAL BRIEF
3.15 Main Features
1. Main features of KU990R
- BAR Type
- WCDMA(2100) + GSM(900,1800) + PCS(1900) Triple mode
- Main LCD: 240x400/3.0/262K TFT
- 5.1M Pixel AF Camera
- VGA CMOS Camera
- 16 module speaker
- Stereo Headset
- Video telephony in WCDMA with camera
- HSDPA up to 3.6 Mbps
- Loud Speaker phone(in GSM and WCDMA)
- 64 Poly Sound
- Audio: MP3, AAC, AAC+,AAC++, WMA, WAV
- MPEG4 encoder/decoder and play/save
- H.263 decoder
- Video Recording: VGA 30 fps
- JPEG en/decoder
- Support Bluetooth, USB
- FM Radio
- touch screen, touch feedback
- 103 x 54 x 15.6 mm
- 1000mAh soft pack
- 89 -
3. TECHNICAL BRIEF
2. Main Components of KU990R
LCD
MAIN Bottom Side MAIN Top Side
5M camera
Touch FPCB Bottom
Intenna
Strobe Flash
Sub Top Side
5M Camera FPCB
Sub Bottom Side
Touch FPCB Top
- 90 -
3. TECHNICAL BRIEF
2.1 Main Top Side
U702
MicroSD Select MSM and
MMP IC
U400 U602
U401
Touch Screen Driver IC U700
5M CAM LDO IC
U601
LCD Backlight Charge
Pump IC
U301 Over Voltage Protection IC
U505
U300 Switch IC for USB2.0 U304
Side Key FPCB SideKey Audio AMP LDO U503
LCD LDO IC
U303 USB/REMOCON SEL IC U507
End Key END CAM/HP MIC SEL IC U506
Clear Key 701 Headphone AMP IC U504
Send Key 700 FM Radio IC U103
Description Reference Description Reference
U103
U504
U506
U503
U507
U304
U702
U601
U602
U400
U401
701
700
END
SideKey
U303
U300
U301
U700
U505
- 91 -
3. TECHNICAL BRIEF
2.2 Main Bottom Side
RF Switch SW100 RTR6235 RF IC U100
MIC MIC500 SIM Connector J400
PM6635 PMIC U501
Linear Motor Control IC
U603
Main-Sub B-to-B Connector CN603 Linear Motor Driver IC U606
PAM IC for GSM U101 MSM6280 Modem IC U200
Main Intenna Connection PAD ANT PAD 27Mhz Crystal Oscillator X300
19.2MHz Crystal Oscillator for TCXO X100 DC-DC Converter IC U701
Antenna Switching Module FL100 ZR3453 DSP IC U302
Memory IC U402 LCD Connector CN300
Charging IC U500 5M CAM FPCB Connector CN600
Battery Connector PAD OUT PAD Strobe Flash Connector CN601
32.768KHz Crystal Oscillator X500 U605
WM8983 Audio DAC/ADC AMP IC U502 Mode Switch SW600
TA and USB Connector CN500 Touch FPCB Connector CN701
SW600
CN701
U606
CN300
CN601
CN600
U701
U200
U302
X300
J400
MIC500
SW100
U100
FL100
ANT PAD
U101
X100
U402
OUT PAD
U500
X500
U501
CN603
CN500
U502
U603
U605
- 92 -
3. TECHNICAL BRIEF
2.3 Sub PCB
Backup Battery BAT900 Bluetooth Driver IC M800
Main-Sub B-to-B
Connector
CN801
Hall IC for Camera Cover
Detection
U800
U904 U901
Headset Hook Switch IC U902
Hall IC for Wheel Switch
Detection
U903
5MP Camera Power IC
U900
T-Flash Connector S800 CAM MIC MIC900
Module Speaker SPEAKER Bluetooth Antenna PAD BT PAD
S800
SPEAKER
U902
U900
BT PAD
MIC900
CN801
BAT900
M800
U903
U901
U800
U904
- 93 -
3. TECHNICAL BRIEF
2.4 Touch FPCB
Vibrator PAD Vibrator
Touch Window Connector CN102
Main B-to-B Connector
(FPCB to Main PCB)
CN101
Receiver PAD Receiver
CN101
Receiver
Vibrator
CN102
- 94 -
3. TECHNICAL BRIEF
2.5 5M Camera FPCB
Main PCB Connector
(FPCB to Main PCB)
CN602
5M Camera Module
Connector
CN601
CN602
CN601
- 95 -
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
4.1 RF Component

Reference Description Reference Description
U100 GSM/UMTS Transceiver (RTR) X100 VCTCXO(19.2MHz)
FL103 UMTS Duplexer FL104 UMTS TX SAW
FL102 UMTS RX SAW U105 UMTS PAM
FL100 Front -End-Module U104 Coupler
SW100 RF Antenna Connector FL101 GSM900 TX SAW
U101 GSM/EDGE PAM
FL100
SW100
FL102
FL103
U100
U101
FL101
U104
U105
FL104
X100
- 96 -
4. TROUBLE SHOOTING
4.2 SIGNAL PATH
4.2.1 UMTS PATH
COMMON TX/RX PATH
UMTS TX PATH
UMTS RX PATH
4.2.2 GSM PATH
- 97 -
4. TROUBLE SHOOTING
COMMON TX/RX PATH
DCS/PCS TX PATH
GSM TX PATH
GSM RX PATH
PCS RX PATH
DCS RX PATH
4.3 Checking VCTCXO Block
The reference frequency (19.2MHz) from X100 (VCXO) is used UMTS TX part, GSM part and BB part.
4. TROUBLE SHOOTING
- 98 -
TCXO
0.1u
C139
C147 1000p
100ohm R115
1000p
C145
0.01u
C141
8200p C148
1000p
C140
X100
2
GND OUT
3
VCC
4
VCONT
1
19.2MHz
R120 100K
TC7SH04FS
U102
C144 1000p
TRK_LO_ADJ VREG_TCXO_2.85V
TCXO_BT
VREG_BT_2.85V
TCXO_PM
RTR6275_TCXO

TP1
TP2 TP3
TP4
Schematic of the TCXO Block
Test Point of the TCXO Blcok
TP1
TP2
TP4
TP3
4. TROUBLE SHOOTING
- 99 -
Check TP1
VCC of VCXO
VCC 2.8V
Check TP2
TRK_LO_ADJ
3V Voltage 0V
Check TP3, TP4
With Oscilloscope
19.2MHz Signal
VCXO is OK
Check other part
Check PMIC
Check MSM
Check soldering
and components
Yes
Yes
Yes
No
No
No
4.4 Checking Front-End Module Block
4. TROUBLE SHOOTING
- 100 -
Schematic of the Front-End Module Block
Test Point of Front-End Module Block
47p
C109
C115
47p
47p
C113
12
GND5
14
GND6
GND7
15
GND8
17
18
GND9
NC
7
PCS_RX1
22
PCS_RX2
21
25
PGND1
26
PGND2
8
UMTS_TX_RX
VC1
5
4
VC2
VC3
3
VDD
6
ANT
10
DCS_PCS_TX
13
DCS_RX1
20
19
DCS_RX2
EGSM_RX1
24
23
EGSM_RX2
EGSM_TX
16
1
GND1
2
GND2
GND3
9
11
GND4
LSHS-M090UH
47p
C114
VREG_RF_SMPS
ANT_SEL2
ANT_SEL0
ANT_SEL1
TP1 TP2 TP3
TP4
TP1
TP3
TP4
TP2
4. TROUBLE SHOOTING
- 101 -
- UMTS Tx/Rx - GSM900 Tx
- DCS1800/PCS1900 Tx - GSM Rx / PCS1900 Rx
Logic Table of the FEM
Vc3 Vc2 Vc1 Vdd
GSM900 Tx L H H H
UMTS Tx/Rx H L H H
GSM 900 Rx L L/H L H
DCS 1800 Rx H L/H L H
PCS 1900 Rx L L/H L H
TP2 (Vc2)
TP3 (Vc3)
TP1 (Vc1)
TP2 (Vc2)
TP3 (Vc3)
TP1 (Vc1)
TP2 (Vc2)
TP3 (Vc3)
TP1 (Vc1)
TP2 (Vc2)
TP3 (Vc3)
TP1 (Vc1)
- 102 -
4. TROUBLE SHOOTING
- DCS1800 Rx
Checking Switch Block power source
Check Soldering
ANT_SEL0, 1, 2 High Level
2.5V < Voltgae < 3.0V
Check VDD
TP4 VREG_RF_SMPS
Check the Logic
in each mode
YES
NO
TP2 (Vc2)
TP3 (Vc3)
TP1 (Vc1)
- 103 -
4. TROUBLE SHOOTING
4.5 Checking UMTS Block
4.5.1 Checking TX level
Schematic of the WCDMA Tx Block
Test Point of the WCDMA Tx Block
NA
L102
AC G
1
G
2
KMS-518
SW100
120p C101
12
GND5
14
GND6
GND7
15
GND8
17
18
GND9
NC
7
PCS_RX1
22
PCS_RX2
21
25
PGND1
26
PGND2
8
UMTS_TX_RX
VC1
5
4
VC2
VC3
3
VDD
6
ANT
10
DCS_PCS_TX
13
DCS_RX1
20
19
DCS_RX2
EGSM_RX1
24
23
EGSM_RX2
EGSM_TX
16
1
GND1
2
GND2
GND3
9
11
GND4
FL100
LSHS-M090UH
PQ
20dB
8 dB
NA
C165
L125
1.2nH
100p
C163
L121
2.2nH
C160
22u
51
R124
L122
NA
100
R126
C168
2
4
5
3
1
56p
Q100
KRX102E
C162
0.01u
15nH
L123
2
RFIN
RFOUT
8
VCC1
1 10
VCC2
4
VMODE
VREF
5
AWT6277R
U105
GND1
3
GND2
6
7
GND3
9
GND4
GND5
11
C167
56p
5.6p C169
C161
56p
SCDY0003403
5
0
O
H
M
43
C
O
U
P
2
IN
1
O
U
T
C173
100p
U104
R123
68
C159
8.2p
C152
3.9p
1.8p
C170
L128
4.7nH
L124
3.3nH
L126
8.2nH
EFCH1950TDF1
FL104
G1
2
G2
3
G3
5
IN
1 O1
4
R125
100
1u
C164
C
1
5
6
2
.2
p
FL103 A
N
T
21
G
N
D
1
G
N
D
2
48
G
N
D
3
G
N
D
4
9
G
N
D
5
6
G
N
D
6
3 7
R
X
5
T
X
SAYZY1G95EB0B00
WCDMA_2100_TX_OUT
PA_ON
VREG_TCXO_2.85V
+VPWR
PA_R1
PWR_DET
TP1
TP2
TP3
TP4
TP1
TP2
TP3
TP4
4. TROUBLE SHOOTING
- 104 -
For testing, Max power of UMT 2100 is needed.
Run a FTM program
set RF mode to IMT
set uplink freq. To
9750 click Tx on and
WCDMA set PA range
R1 on set Tx AGC to
410
Check Tx SAW
Filter
FL104
Check PAM block
U105
Check coupler U104
Check Duplexer
FL103
Check FEM FL100
4. TROUBLE SHOOTING
- 105 -
4.5.2 Checking UMTS PAM Control Block
PAM control signal
1. PWR_DET : UMTS Tx Power Detected value (Check R123)
2. TX_AGC_ADJ : UMTS RTR6275 Tx Amp Gain Control
3. VREG_TCXO_2.85V : UMTS PAM enable (about 2.85V)
4. +VPWR : UMTS PAM Main Voltage ( 3V < +VPWR < 4.2V)
5. PA_ON : Turns the PA on and off
6. PA_R1 : Control signals that step the active PA mode and bias
+VPWR
VREG_TCXO_2.85V
R123
UMTS2100
Coupler
- 106 -
4. TROUBLE SHOOTING
4.5.3 Checking RX level
TP1
TP2
TP3
TP4
Vbias
PQ
C104
1.2p
ANT101
NA
L102
AC G
1
G
2
KMS-518
SW100
120p C101
FL100
ANT100
0
L100
C102
12nH
L101
4.7nH
ANT102
TP1
- 107 -
4. TROUBLE SHOOTING
PQ
PQ
20dB
8 dB
NA
C165
L125
1.2nH
1nH
L118
C149
22p
1.5nH
L114
100p
C163
L121
2.2nH
C160
22u
51
R124
100
R126
C168
2
4
5
3
1
56p
Q100
KRX102E
C162
0.01u
15nH
L123
C153
56p
2
RFIN
RFOUT
8
VCC1
1 10
VCC2
4
VMODE
VREF
5
AWT6277R
U105
GND1
3
GND2
6
7
GND3
9
GND4
GND5
11
C167
56p
5.6p C169
L119
1nH
C161
56p
SCDY0003403
5
0
O
H
M
43
C
O
U
P
2
IN
1
O
U
T
C173
100p
U104
R123
68
0.5p
C155
C159
8.2p
C154
56p C152
3.9p
1.8p
C170
L116
1nH
L128
4.7nH
L124
3.3nH
L126
8.2nH
FL102
EFCH2140TDE1
G1
2
G2
5
IN
1
O1
3
O2
4
EFCH1950TDF1
FL104
G1
2
G2
3
G3
5
IN
1 O1
4
R125
100
L117
1.8nH
L115
1nH
1u
C164
C
1
5
6
2
.2
p
FL103 A
N
T
21
G
N
D
1
G
N
D
2
48
G
N
D
3
G
N
D
4
9
G
N
D
5
6
G
N
D
6
3 7
R
X
5
T
X
SAYZY1G95EB0B00
PA_ON
VREG_TCXO_2.85V
+VPWR
PA_R1
WLNA_OUT
WCDMA_MIX_IN_M
WCDMA_MIX_IN_P
VDD_RX
RX_WCDMA_2100
PWR_DET
Check Vbias over 2V?
Check the RF S/W
Check FEM
FL100
Check the Duplexer
FL103
Check the RTR6275
U100
Check TP2
Signal exist?
Check TP3
Signal exist?
Check TP4
Signal exist?
TP2
Vbias
TP4
TP3
- 108 -
4. TROUBLE SHOOTING
4.6 Checking GSM Block
4.6.1 Checking Front-End Module
Refer to chapter 3.4
1
2
3
- 109 -
4. TROUBLE SHOOTING
4.6.2 Checking RF Tx Level
PQ
C104
1.2p
ANT101
C115
47p
47p
C113
NA
L102
AC G
1
G
2
KMS-518
SW100
120p C101
12
GND5
14
GND6
GND7
15
GND8
17
18
GND9
NC
7
PCS_RX1
22
PCS_RX2
21
25
PGND1
26
PGND2
8
UMTS_TX_RX
VC1
5
4
VC2
VC3
3
VDD
6
ANT
10
DCS_PCS_TX
13
DCS_RX1
20
19
DCS_RX2
EGSM_RX1
24
23
EGSM_RX2
EGSM_TX
16
1
GND1
2
GND2
GND3
9
11
GND4
FL100
LSHS-M090UH
47p
C114
ANT100
0
L100
C102
12nH
L101
4.7nH
ANT102
ANT_SEL2
ANT_SEL0
ANT_SEL1
PQ
C138
NA
C142
0.75p
8p C136
L113
14
GND6
G
N
D
7
1
6
1
7
G
N
D
8
7
GSM_IN
9
GSM_OUT
3
TX_EN
VBATT
4
12
VCC
VRAMP
6
4.7nH
TQM7M5003
U101
2
BS
DCS_PCS_IN
1
D
C
S
_
P
C
S
_
O
U
T
1
5
5
GND1
GND2
8
10
GND3
11
GND4
13
GND5
15nH
L112
C146 10p
Schematic of the GSM Tx Block
Test Point of GSM Tx Block
TP1 TP2
TP3
TP1
TP2
TP3
4. TROUBLE SHOOTING
- 110 -
START
Check TP1
If GSM over 31 dBm?
If DCS/PCS over 28dBm?
Check TP2, TP3
If TP2 over 29dBm?
If TP3 over 25dBm?
Check PAM Block OK?
Refer to chapter 3.6.3
Check Soldering of PAM (U101)
If problem still exist,
replace the PAM
Change the Board
Problem resolved ?
Yes
Yes
Yes
Yes
No
No
No
No
GSM/DCS/PCS Tx is OK
Check other part
Check Front-End
Module
Refer to chapter 3.4
Check the RTR6275
GSM/DCS/PCS Tx is OK
- 111 -
4. TROUBLE SHOOTING
4.6.3 Checking PAM Block
HIGH
MODE
LOW
GSM_PA_BAND
10 dB
GSM
DCS/PCS
8 dB
33u
C135
120
R119
120
R118
51
R114
91
R112
R117 2.2K
91
R113
1u
C137
14
GND6
G
N
D
7
1
6
1
7
G
N
D
8
7
GSM_IN
9
GSM_OUT
3
TX_EN
VBATT
4
12
VCC
VRAMP
6
TQM7M5003
U101
2
BS
DCS_PCS_IN
1
D
C
S
_
P
C
S
_
O
U
T
1
5
5
GND1
GND2
8
10
GND3
11
GND4
13
GND5
2
G1
3
G2
5
G3 1
IN
4
O1
EFCH897MTDB1
FL101
68p
C143
68
R111
GSM_PA_BAND
+VPWR
DCS_PCS_TX
GSM_TX
GSM_PA_RAMP
GSM_PA_EN
TP1
TP2
TP3
Test Point Net name Description
TP1 GSM_PA_RAMP Power Amp Gain Control. Typically, 0.2 ~1.6V
TP2 GSM_PA_EN Power Amp Enable (ON : >2.5V, OFF : <0.7V)
TP3 +VPWR PAM Supply Voltage (Vcc > 3V)
Schematic of PAM Block
Test Point of PAM Block
TP1
TP2
TP3
- 112 -
4. TROUBLE SHOOTING
4.6.4 Checking RF Rx Level
Schematic of GSM-900, DCS-1800, PCS-1900 Rx Block
Test Point of Rx Block
DCS
GSM
PCS
15nH
L104
47p
C109
5.6nH L103
15nH
L107
NA
L102
AC G
1
G
2
KMS-518
SW100
L109 22nH
120p C101
12
GND5
14
GND6
GND7
15
GND8
17
18
GND9
NC
7
PCS_RX1
22
PCS_RX2
21
25
PGND1
26
PGND2
8
UMTS_TX_RX
VC1
5
4
VC2
VC3
3
VDD
6
ANT
10
DCS_PCS_TX
13
DCS_RX1
20
19
DCS_RX2
EGSM_RX1
24
23
EGSM_RX2
EGSM_TX
16
1
GND1
2
GND2
GND3
9
11
GND4
FL100
LSHS-M090UH
5.6nH L105
5.6nH L106
22nH
L110
L111 22nH
L108
5.6nH
VREG_RF_SMPS
TP1 TP2 TP3
TP3
TP2
TP1
- 113 -
4. TROUBLE SHOOTING
4. TROUBLE SHOOTING
- 114 -
4.7 Power on trouble
Power on sequence of KU990R is :
PWR key press PM_ON_SW_N go to low (VA700, PM6650-2M KPDPWR_N pin#24) PM6650-
2M Power Up VREG_MSMC_1.2V(C560), VREG_MSME_1.8V(R520), VREG_MSMP_2.7V(R513),
VREG_MSMA_2.6V(R508), VREG_TCXO_2.85V(C510) power up PON_RESET_N assert to MSM
Phone booting & PS_HOLD(D500) assert High to PMIC(PM6650-2M)
Start
Battery voltg. higher
than 3.2V?
Press PWR key
Keypad LED on?
VA700 high to low
when key press?
VREG_MSMC_1.2V,
VREG_MSMP_2.7V, VREG_MSME_1.8V
VREG_TCXO_2.85V,
VREG_MSMA_2.6V power up?
Is clock ok?
X100 : 19.2M
X500 : 32.768Khz
Change the Main board
Change or charging the
Battery
Follow the LED trouble
shoot
Check open Pattern
of power button
Check Dome Sheet
Check the TXCO and SLEEP CRYSTAL
NO
YES
YES
YES
YES
YES
NO
NO
NO
NO
4. TROUBLE SHOOTING
- 115 -
VREG_MSMC_1.2V(C560)
VREG_MSME_1.8V(R520)
TCXO ( 19.2MHz )
VREG_MSMP_2.7V(R513)
VREG_MSMA_2.6V(R508)
VREG_TCXO_2.75V(C510)
SLEEP CRYSTAL(32.768KHz)
4. TROUBLE SHOOTING
- 116 -
PM_ON_SW_N (D700)
RESET_IN_N(R208)
PS_HOLD(D500)
4. TROUBLE SHOOTING
- 117 -
4.7.1 USB trouble
USB Initial sequence of KU990R is :
USB connected to KU990R USB_VBUS(C540) go to 5V
USB_D+(VA202) go to 3.3V 48M Crystal on USB_DATA is triggered USB work
Start
USB_VBUS is about
to 5V?
USB_D+ is about to 3.3V?
48MHz is run?
Check C540, R514,U500
USB cable
Check VA500,U507,U304
Check X200
NO
YES
YES
YES
NO
NO
Cable is insert?
YES
Cable insert
NO
X200(48MHz)
C540(USB_VBUS)
U507(USB_D+)
R514(USB_VBUS)
U500(USB_VBUS)
VA500(USB_D+)
U304(USB_D+)
4. TROUBLE SHOOTING
- 118 -
4.7.2 UMS(USB MASS STORAGE) trouble
UMS Initial sequence of KU990R is :
USB connected to KU990R VREG_5V(R335, UMS) go to 5V VREG_USB_3.3V(R301) go to
3.3V USB_DATA is triggered USB work
Start
VREG_5V is about
to 5V?
VREG_USB_3.3V is
about to 3.3V?
MICRO SD function OK?
Check R335, D501
Check R301,C529, USB CABLE
Follow the micro sd trouble
NO
YES
YES
YES
NO
NO
Cable is insert?
YES
Cable insert
NO
C529 (VREG_USB_3.3V) D501(VREG_5V)
< TOP SIDE >
R335(VREG_5V)
R301(VREG_USB_3.3V)
4. TROUBLE SHOOTING
- 119 -
4.8 SIM detect trouble
USB Initial sequence of KU990R is :
VREG_USIM_3.0V(C552 of PM6650) go to 3.0V USIM clock, reset and data triggered USIM IF
work (Schematic and place are refer to SIM technical brief)
Start
Work well?
VREG_USIM_3.0V is 3.0V?
USIM_P_CLK is run?
End
Check J400, D400,C552
Yes
No
YES
NO
Re-insert the SIM card
Change SIM card
Work well? End
Yes
No
USIM_P_RST_N
C552(VREG_USIM_3.0V)
J400
USIM_P_CLK
USIM_P_DATA
4. TROUBLE SHOOTING
- 120 -
4.9 Key sense trouble ( KEYPAD )
Key Sense sequence of KU990R is :
Default condition ROW(0-2) is 2.7V Press the key Corresponding ROW(x) and COL(x) go to 0V
Scan pulse( Col => Row ) MSM sense what key pressed.
Check the R701,R705,R706 with no key press
Yes
NO
Change the DOME SHEET
Check the R701,R705,R706 with key press
ROW(0-2) is 2.7V?
Check R701,R705,R706
NO
Yes
ROW(0-2),
COL(0-1) is 0V?
Work well?
End
START
Check VA700~ VA707, R707~R710
NO
YES
NO
Change SIDE KEY
Work well?
NO
Work well?
YES
YES
NO
Dome sheet
Side Key
4. TROUBLE SHOOTING
- 121 -
Schematic of key sense part
CLR SEND
R
7
0
1
5
1
K
701 700
V
A
7
0
2
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
1
E
V
L
C
1
4
S
0
2
0
5
0
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
3
KEY_ROW[2]
VREG_MSMP_2.7V
KEY_COL[0]
KEY_COL[1]
END
ON_SW KEY
E
V
L
1
4
K
0
2
2
0
0
V
A
7
0
0
END
PM_ON_SW_N
VA702(COL0)
SEND
VA703(COL1)
VA701(ROW2)
CLR END
SIDE KEY
470 R709
R710 470
470 R708
5
1
K
R
7
0
6
V
A
7
0
4
E
V
L
C
1
4
S
0
2
0
5
0
5
1
K
R
7
0
5
VREG_MSMP_2.7V
R707 470
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
7
E
V
L
C
1
4
S
0
2
0
5
0
V
A
7
0
6
V
A
7
0
5
E
V
L
C
1
4
S
0
2
0
5
0
5
CN700
1
2
3
4
KEY_ROW[0]
KEY_ROW[1]
KEY_COL[1]
KEY_COL[0]
LOCK
SHOT
4. TROUBLE SHOOTING
- 122 -
4.10 Keypad backlight trouble
Key Pad Back Light is on as below :
Key pressing PM6650 KYPD_LED_EN go to Low LED On (Key Pad LED controlled by PM6650)
Start
Check device short :
LD700~705 and R711~716 (Main)
NO
Yes
Key press
Signal KYPD_LED_EN
is Low?
+VPWR is OK?
Change the main board
NO
Yes
Yes
Check device open :
LD700~705 and R711~716 (Main)
NO
Some LED
is not work?
Work well?
Yes
Change the main board
NO
End
LD700~705 (Main)
LD703 (+VPWR)
VA708 (KYPD_LED_EN) R711~716 (Main)
4. TROUBLE SHOOTING
- 123 -
(GREEN)
Rev. 1.1
(WHITE) (RED)
R
7
1
1
4
7
L
D
7
0
1
S
S
C
-
F
R
1
0
4
-
I
I
1
R
7
1
2
2
0
0
S
S
C
-
F
R
1
0
4
-
I
I
1
2
0
0
R
7
1
4
L
D
7
0
3
EVL14K02200
VA708
S
S
C
-
T
W
H
1
0
4
-
H
L
L
D
7
0
4
R
7
1
5
4
7S
S
C
-
T
W
H
1
0
4
-
H
L
R
7
1
3
4
7
L
D
7
0
0
L
E
G
G
-
S
1
4
G
L
D
7
0
2
L
D
7
0
5
L
E
G
G
-
S
1
4
G
4
7
R
7
1
6
KYPD_LED_EN
+VPWR
LD700~705 and R711~716 (Main)
VA708 (KYPD_LED_N)
LD703 (+VPWR)
Schematic of keypad backlight part
4. TROUBLE SHOOTING
- 124 -
4.11 Micro SD trouble
Micro SD is worked as below :
Micro SD insertion MICROSD_DETECT(R804) goes to low go working
MICROSD_DETECT(R804))
is low ?
Insert the Micro SD Card
Start
End
Check VREG_MMC_3.0V
is over 2.85V?
Work well?
YES
NO
SOCKET
R804(DETECT)
YES
Change the SUB board
Work well?
YES
NO
NO
Change the MAIN board
YES
NO
C807(VREG_MMC_3.0V)
4. TROUBLE SHOOTING
- 125 -
4.12 Audio trouble
4.12.1 Receiver path
Voice Receiver path as below:
MSM6280 Ear1ON/Ear1OP CN701(VGA CAM FPCB connector) Receiver
Start
Connect the phone to network
Equipment and setup call
Setup 1KHz tone out
Can you hear the tone?
YES
END
Check connector pin
or change the VGA CAM FPCB
YES
Change the Receiver
Hear the tone to the receiver?
NO
END
4. TROUBLE SHOOTING
- 126 -
VGA CAM
FPCB
connector
Receiver Receiver
pads
MSM6280
4. TROUBLE SHOOTING
- 127 -
4.12.2 Voice path for headset
Voice path for Head_Set as below:
MSM6280 HPH_R, HPH_L C548,C549 U502(audio codec) C578,C562 R529,C522
U504(Headset AMP) FB502, FB503 R525, R524 #4, #5 pin of CN500 headset Jack
Start
The sine wave appear at
C548,C549 ?
NO
Setup 1KHz tone out
And insert head_Set
C578,C562 ?
YES
Check the U502
or change the Main bd
NO
NO
YES
YES
END
Headset insertion detection
in the Main LCD Display OK?
Check #8 pin of CN500
NO
YES
Check the CN500 or change the
Main bd
R525,R524 ?
YES
Check the U504
NO
4. TROUBLE SHOOTING
- 128 -
CN500
R524
R525
8 9
1
2
1
3
1
9
2
2
1
3 4 5 6 7
C
N
5
0
0
1
1
0
1
1
R528 100K
F
B
5
0
4
T
V
_
O
U
T
E
A
R
_
M
I
C
_
P
R
M
T
_
P
W
R
_
O
N
_
N
R
M
T
_
I
N
T
-
U
S
B
_
D
+
R
M
T
_
A
D
C
-
U
S
B
_
D
-
V
B
A
T
T
F
M
_
A
N
T
M
I
D
I
_
E
A
R
_
L
M
I
D
I
_
E
A
R
_
R
E
A
R
_
S
E
N
S
E
_
N
Schematic of voice path
4. TROUBLE SHOOTING
- 129 -
C548 C549
U502
FB501
FB500
NA
C550
0.1u
C514
C535 1u
C532 1u
R2_GPIO3
6
RIN
5
4
RIP
ROUT1
29
ROUT2
23
16
SCLK
SDIN
17
27
VMID DACDAT
10
DBVDD
14
DCVDD
13 12
DGND
L2_GPIO2
3
LIN
2
1
LIP
LOUT1
30
25
LOUT2
7
LRC
11
MCLK
MICBIAS
32
18
MODE
OUT3
22
21
OUT4
33
PGND
U502
ADCDAT
9
28
AGND1
24
AGND2
AUXL
19
AUXR
20
31
AVDD1
AVDD2
26
8
BCLK
15
CSB_GPIO1
4.7u
C520
WM8983
C533
4.7n
R511
18K
R533
0
10u
C525
C
5
3
4
1
u
10u
C513
1
0
0
K
R
5
1
9
4.7n
C542
NA
C531
1K
R516
R510
1K
C541
1u
1u
C549
1u C548
C536 1u
C518
4.7u
C
5
3
9
1
u
12n
C547
C524
0.1u
NA
C544
C519
0.1u
C551
NA
C521
0.1u
C543
NA
12n
C530
18K
R517
C516
4.7u
C517
0.1u
MIC_PWR
MMP_A_MCLK
CODEC_I2C_SCL
CODEC_I2C_SDA
HP_R
HP_L
HP_EAR_L
MIC2P
HP_EAR_R
MID_MICP
SPK_L
SPK_R
FM_AUDIO_L
FM_AUDIO_R
MMP_A_BCLK
MMP_ADO_DACDAT
MMP_A_LRCLK
MMP_ADI_ADCDAT
SPK_OUT-
SPK_OUT+
VREG_5V
VREG_WM_2.7V
VREG_MSME_1.8V
MIDI_3.3V
U502
4. TROUBLE SHOOTING
- 130 -
FB502
FB503
U504
C562
R522
C578
R529
PQ
PQ
R524
68
SVSS
1
6
_
S
H
D
N
C1N
4
2
C1P
I
N
L
+
1
5
I
N
L
_
1
4
7
I
N
R
+
I
N
R
_
8
OUTL
12
OUTR
10 3
PGND
PVDD
1
5
P
V
S
S
P
_
G
1
7
S
G
N
D
6
1
3
S
V
D
D
1
9
SVDD2
11
U504
MAX9722BETE
4.7u
C565
C577
1u
R525
68
600 FB503
FB502 600
0
.
2
2
u
C
5
7
8
R
5
2
2
1
5
K
1
5
K
R
5
2
9
1u
C570
P
R
S
B
6
.
8
C
C
5
7
4
C
5
7
3
P
R
S
B
6
.
8
C
1u
C566
C
5
6
2
0
.
2
2
u
MIDI_EAR_R
MIDI_EAR_L
MIDI_3.3V
HP_AMP_EN
HP_EAR_L
HP_EAR_R
U504
4. TROUBLE SHOOTING
- 131 -
4.12.3 Loud speaker path (voice speaker phone/VT)
Loud speaker path as below:
MSM6280 SPK_R, SPK_L C532,C541 R510,R516 C533,C542 R511,R517
U502(audio codec) FB500,FB501 CN603(BtoB connector) OUT800, OUT801 (SPK PAD)
Speaker
Start
C532,C541?
NO
Setup 1KHz tone out
Set phone with speaker phone mode
FB500, FB501?
YES
Check the U502 or
NO
Check the CN603
NO
YES
YES
Change the speaker
NO
YES
END
pads of speaker?
4. TROUBLE SHOOTING
- 132 -
MICBIAS
T15
AC18
LINE_ON
LINE_OP
AC17
HPH_L
W17
AA17
HPH_R
EAR1ON
AE18
EAR1OP
AF18
HP_R
HP_L
RCV+
RCV-
MICBIAS
SPK_L
SPK_R
FB501
FB500
C535 1u
C532 1u
R2_GPIO3
6
RIN
5
4
RIP
ROUT1
29
ROUT2
23
16
SCLK
27
VMID DACDAT
10
L2_GPIO2
3
LIN
2
1
LIP
LOUT1
30
25
LOUT2
7
LRC
11
MCLK
MICBIAS
32
18
MODE
OUT3
22
21
OUT4
ADCDAT
9
24
AGND2
AUXL
19
AUXR
20
8
BCLK
15
CSB_GPIO1
C533
4.7n
R511
18K
10u
C525
C
5
3
4
1
u
K 9
4.7n
C542
NA
C531
1K
R516
R510
1K
C541 1u
C536 1u
C
5
3
9
1
u
12n
C547
C524
0.1u
NA
C544 C543
NA
12n
C530
18K
R517
MIC_PWR
MMP_A_MCLK
CODEC I2C SCL
HP_EAR_L
MIC2P
HP_EAR_R
MID_MICP
SPK_L
SPK_R
FM_AUDIO_L
FM_AUDIO_R
MMP_A_BCLK
MMP_ADO_DACDAT
MMP_A_LRCLK
MMP_ADI_ADCDAT
SPK_OUT-
SPK_OUT+
AXK740327G
V
R
E
G
_
M
M
C
_
3
.
0
V
8
9
3
30
31
32
33
34
35
36
37
38
39
4
40
5
6
7
15
16
17
18
19
2
20 21
22
23
24
25
26
27
28
29
CN603
G1
G2
1
10
11
12
13
14
V
R
E
G
_
M
S
M
P
_
2
.
7
V
+
V
P
W
R
V
R
E
G
_
B
T
_
2
.
8
5
V
MMP_CAM_PWR_EN
SPK_OUT+
SPK_OUT-
HOOK_SENSE_N
EAR_MIC_P
MICROSD_DATA[1]
MICROSD_DETECT
MICROSD_CLK
MICROSD_DATA[0]
MICROSD_CMD
CAM_VDD_AF_2.7V
CAM_MIC+
WHEEL_SW_L
WHEEL_SW_R
CAM_VDD_SD_1.8V
V_BACK_UP
TCXO_BT
BT_TX_RX_N
BT_SBST
BT_SBCK
BT_SBDT
BT_CLK
BT_DATA
MICROSD_DATA[3]
MICROSD_DATA[2]
4. TROUBLE SHOOTING
- 133 -
MSM
Pads of Speaker
C722
CN603
U502 (audio codec)
C532,C541
FB500, FB501
4. TROUBLE SHOOTING
- 134 -
4.12.4 Microphone for main MIC
Main Microphone path as below:
MIC C567,C568 MSM internal CODEC
MIC
10u
C563
C568 22n
C569
NA
C564
47p
2
G1
3
G2
1
O
4
P
SPM0204HE5-PB-3
MIC500
33p
C575
10p
C576
C567 22n
MICBIAS
MIC1P
MIC1N
10%
Place near
MSM pin W18
(CODEC VSS)
C
2
0
4
N
A
C238 0.1u
0
.
1
u
C
2
3
5
C
2
3
6
0
.
1
u
N
A
C
2
3
7
N
A
C
2
0
3
C200
10p
SDCC_DAT1_GPIO99
F25
M25
SDCC_DAT2_GPIO100
SDCC_DAT3_GPIO101
M26
M
I
C
1
N
A
F
2
0
M
I
C
1
P
A
E
2
0
A
F
2
1
M
I
C
2
N
A
F
2
2
M
I
C
2
P
L
I
N
E
_
L
_
I
N
A
C
2
1
L
I
N
E
_
L
_
I
P
A
C
2
0
L
I
N
E
_
R
_
I
N
L
I
N
E
_
R
_
I
P
A
C
1
9
C
C
O
M
P
A
A
2
0
A
F
1
9
A
U
X
I
N
A
E
1
9
A
U
X
I
P
MSM
MSM
MSM
M
I
C
1
P
M
I
C
1
N
Can you scoping some
sound signal at C567,C568?
Change the MIC or
Change the Main B'd
NO
YES
YES
make some sound or
voice to MIC
Work well? END
YES
Start
MIC_BIAS(R221) is 1.8V?
Change the Main B'd
NO
Make a call
4. TROUBLE SHOOTING
- 135 -
MIC500 (MIC for Handset)
C567, C568
MSM
4.12.5 Microphone for headset
MIC for Head_Set path as below:
Insert Headset EAR_SENSE_N(pin8) go 0V MSM6280 sense Head_Set insertion
MIC signal U502(audio codec) MSM6280.
Start
EAR_SENSE_N is 0V?
END
Make a call
Change the Main b'd
Change the Main b'd
MIC_BIAS is 2.7V ?
YES
YES
NO
NO
NO
Try ch ange the head set
Can you s coping s ome
sound signal at C539?
Change the MIC
YES
YES
make some sound or
voice t o MIC
Work w ell?
END
YES
Can you s coping s ome
sound signal at C235,L20 0?
Check t he U502 or
Change the Main Bd
NO
NO
YES
4. TROUBLE SHOOTING
- 136 -
8
9
12
13
14
15
16
17
19
2
21
3
4
5
6
7
CN500
1
10
11
R
5
2
8
1
0
0
K
FB504
VREG_MSMP_2.7V
2.2uH
L504
TV_OUT
EAR_MIC_P
RMT_PWR_ON_N
RMT_INT-USB_D+
RMT_ADC-USB_D-
VBATT
FM_ANT
UART TXD
USB_VBUS
MIDI_EAR_L
MIDI_EAR_R
EAR_SENSE_N
FB501
FB500
R2_GPIO3
6
RIN
5
4
RIP
ROUT1
29
ROUT2
23
16
SCLK
27
VMID DACDAT
10
L2_GPIO2
3
LIN
2
1
LIP
LOUT1
30
25
LOUT2
7
LRC
11
MCLK
MICBIAS
32
18
MODE
OUT3
22
21
OUT4
ADCDAT
9
24
AGND2
AUXL
19
AUXR
20
8
BCLK
15
CSB_GPIO1
10u
C525
C
5
3
4
1
u
K 9
NA
C531
C
5
3
9
1
u
C524
0.1u
NA
C544 C543
NA
MIC_PWR
MMP_A_MCLK
CODEC I2C SCL
HP_EAR_L
MIC2P
HP_EAR_R
MID_MICP
MMP_A_BCLK
MMP_ADO_DACDAT
MMP_A_LRCLK
MMP_ADI_ADCDAT
SPK_OUT-
SPK_OUT+
C
2
0
4
N
A
C2
0
.
1
u
C
2
3
5
C
2
3
6
0
.
1
u
L200
100nH
N
A
C
2
0
3
C200
10p
SDCC_DAT1_GPIO99
SDCC_DAT2_GPIO100
SDCC DAT3 GPIO101
M
I
C
1
N
A
F
2
0
M
I
C
1
P
A
E
2
0
A
F
2
1
M
I
C
2
N
A
F
2
2
M
I
C
2
P
L
I
N
E
_
L
_
I
N
A
C
2
1
A
C
2
0
L
I
N
E
_
R
_
I
N
L
I
N
E
_
R
_
I
P
A
C
1
9
C
C
O
M
P
A
A
2
0
A
F
1
9
A
U
X
I
N
A
E
1
9
A
U
X
I
P
M
I
C
1
P
M
I
C
1
N
M
I
C
2
P
4. TROUBLE SHOOTING
- 137 -
#8 pin of ear connector
to check EAR_SENSE_N
C535
MSM
4. TROUBLE SHOOTING
- 138 -
4.13 Camera trouble
Camera control signals are generated by ZORAN (Multimedia Chip)
and directly connected with ZORAN.
KU990R has two cameras. The one is a 5 Mega Camera, the other is VGA camera.
No
Camera is OK?
Check the camera conn. and
reconnect the camera
Change the LDO (U601, U602, U701, U900, U901)
Camera is OK
Check MMP_CAM_PCLK
Change the camera
Yes
NO
NO
Yes
(CN600)
End
Yes
End
NO
5M START
ZORAN output signal check
(MMP_CAM_RESET_N, MMP_
CAM_PWR_EN))
Yes
NO
Check master clock
5M_CAM_MCLK
(CN600)
Yes
Change the Analog Switch (U604, U607)
NO
Yes
Check the EMI/ESD filter
(FL600, FL601)
Yes
No
Change the Filter
4. TROUBLE SHOOTING
- 139 -
MMP_CAM_RESET_N
MMP_CAM_PWR_EN
CAM_VDD_CORE_1.2V
CAM_VDD_SA_2.7V
CAM_VDD_IO_2.7V
CAM_VDD_SD_1.8V
CAM_VDD_AF_2.7V
FL600
FL601
MMP_CAM_PCLK
5M_CAM_MCLK
U604 U607
4. TROUBLE SHOOTING
- 140 -
GB042-30S-H10-E3000
1
u
CAM_VDD_SA_2.7V
CAM_VDD_IO_2.7V
C
6
0
8
C605
0.1u
10p
C610
30
17
18
19
20
21
22
23
24
14
15
2
3
4
5
6
7
8
9
16
25
26
27
28
29
CN600
1
10
11
12
13
0.1u
C612
C606
10p
R601 10
R607
33
0.1u
C607
10p
C611
CAM_VDD_AF_2.7V
CAM_VDD_CORE_1.2V
V
A
6
0
1
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
V
A
6
0
2
C614
E
V
L
C
1
8
S
0
2
0
1
50.1u
C601
0.1u
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
V
A
6
0
0
10u
C600
R604 10
CAM_VDD_SD_1.8V
10 R603
10p
C613
C
6
0
9
0
.
1
u
R608 10
C602
1u
R602 10
STROBE_TRIGGER
MMP_CAM_PCLK
MMP_CAM_HSYNC
MMP_CAM_VSYNC
MMP_I2C_SDA
MMP_I2C_SCL
5M_CAM_MCLK
5
G
1
1
0
G
2
1
INOUT_A1
INOUT_A2
2
3
INOUT_A3
INOUT_A4
4
9
INOUT_B1
8
INOUT_B2
INOUT_B3
7
6
INOUT_B4
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
INOUT_A4
4
9
INOUT_B1
INOUT_B2
8
7
INOUT_B3
INOUT_B4
6
MMP_CAM_DATA[3]
5M_CAM_DATA[0]
5M_CAM_DATA[1]
5M_CAM_DATA[2]
5M_CAM_DATA[3]
MMP_CAM_DATA[4]
MMP_CAM_DATA[5]
MMP_CAM_DATA[6]
MMP_CAM_DATA[7]
5M_CAM_DATA[4]
5M_CAM_DATA[5]
5M_CAM_DATA[6]
5M_CAM_DATA[7]
MMP_CAM_DATA[0]
MMP_CAM_DATA[1]
MMP_CAM_DATA[2]
U604 NC7SB3157L6X
A
4
B0
3
1
B1
2
GND
6
S
5
VCC
0.1u
C622
NC7SB3157L6X U607
4
A
3
B0
B1
1
GND
2
S
6
VCC
5
0.1u
C621
+VPWR
+VPWR
5M_CAM_MCLK
CAM_MCLK VGA_CAM_MCLK
MMP_CAM_MCLK 5M_CAM_MCLK
CAM_SELECT_N
R333 NA
SCL
N14
SDA
P14
GPIO0
P2
M3
GPIO1
GPIO2
P7
N1
GPIO3
GPIO4
P1
GPIO5
M5
N6
GPIO6
GPIO7
M6
P5
GPIO8
N5
GPIO9
TP303
TP302
1
0
0
K
R
3
3
1
MMP_CAM_INT
MMP_I2C_SDA
MMP_I2C_SCL
MMP_STROBE_CHARGE
MICROSD_DETECT
MMP_CAM_RESET_N
MMP_CAM_PWR_EN
Schematic of 5M camera part
C605 : CAM_VDD_CORE_1.2V
R607 : 5M_CAM_MCLK
R331 : MMP_CAM_PWR_EN
FL600
FL601
U607
U604
R608 : 5M_CAM_PCLK
C601 : CAM_VDD_AF_2.7V
C609 : CAM_VDD_SA_2.7V
C606 : CAM_VDD_IO_2.7V
C607 :
CAM_VDD_SD_1.8V
4. TROUBLE SHOOTING
- 141 -
Check VGA_VDD_2.7,
VGA_VDD_1.8V
Camera is OK?
Check the camera & 30-pin conn.
And reconnect these connectors
(Main & FPCB connector)
Change the LDO (U600)
Camera is OK
Check the VGA_CAM_PCLK
Yes
NO
NO
Yes
(R718)
End
Yes
End
NO
VGA START
MSM6280 output signal check
(VGA_CAM_RESET_N, V
VGA_CAM_PWDN)
Yes
NO
Check master clock
(VGA_CAM_MCLK : R717)
Yes
Yes
Check the EMI/ESD filter Change the Filter (FL700, FL701)
NO
NO
Yes
NO
Change the camera
Yes
No
Change the Analog Switch (U604, U607)
NO
Change the slider FPCB
4. TROUBLE SHOOTING
- 142 -
VGA_CAM_PWDN
VGA_CAM_RESET_N
VGA_CAM_PCLK
VGA_CAM_PCLK
FL700, FL701 : EMI FILTER
VGA_VDD_2.7V
U604 U607
VGA_VDD_1.8V
4. TROUBLE SHOOTING
- 143 -
10 R719
VGA_VDD_2.7V
R725 10
10 R724
16
25
26
27
28
29
30
17
18
19
20
21
22
23
24
1
10
11
12
13
14
15
2
3
4
5
6
7
8
9
CN701
C711
0.1u 10p
C713
R718 10
E
V
L
C
1
8
S
0
2
0
1
5
V
A
7
1
5
R
7
2
9
NA
r
e
s
i
s
t
o
r
10p
C715
10
R717
V
A
7
1
4
I
C
V
L
0
5
1
8
1
0
0
Y
5
0
0
F
R
10 R720
C712
10p
E
V
L
C
1
8
S
0
2
0
1
5
V
A
7
1
3
C709
0.1u
VGA_VDD_1.8V
C714
10p 0.1u
C710
VGA_CAM_DATA[2]
VGA_CAM_DATA[3]
I2C_SDA
I2C_SCL
MMP_CAM_VSYNC
MMP_CAM_HSYNC
VGA_CAM_RESET_N
RCV+
RCV-
MOTOR+
MOTOR- x+
x-
Y+
Y-
VGA_CAM_DATA[6]
VGA_CAM_PWDN
VGA_CAM_DATA[5]
VGA_CAM_MCLK
MMP_CAM_PCLK
VGA_CAM_DATA[0]
VGA_CAM_DATA[1]
6
5
G
1
1
0
G
2
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
7
INOUT_B3
INOUT_B4
ICVE10184E070R100FR
FL701
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
7
INOUT_B3
INOUT_B4
6
FL700
ICVE10184E070R100FR
MMP_CAM_DATA[0]
MMP_CAM_DATA[1]
MMP_CAM_DATA[2]
MMP_CAM_DATA[3]
VGA_CAM_DATA[0]
VGA_CAM_DATA[1]
VGA_CAM_DATA[2]
VGA_CAM_DATA[3]
MMP_CAM_DATA[4]
MMP_CAM_DATA[5]
MMP_CAM_DATA[6]
MMP_CAM_DATA[7]
VGA_CAM_DATA[4]
VGA_CAM_DATA[5]
VGA_CAM_DATA[6]
VGA_CAM_DATA[7]
U604 NC7SB3157L6X
A
4
B0
3
1
B1
2
GND
6
S
5
VCC
0.1u
C622
NC7SB3157L6X U607
4
A
3
B0
B1
1
GND
2
S
6
VCC
5
0.1u
C621
+VPWR
+VPWR
5M_CAM_MCLK
CAM_MCLK VGA_CAM_MCLK
MMP_CAM_MCLK 5M_CAM_MCLK
CAM_SELECT_N
Schematic of VGA camera part
R717 : VGA_CAM_MCLK
VA713 : VGA_VDD_2.7V
VA713 : VGA_VDD_2.7V
FL700 FL701
U604
U607
VA713 : VGA_CAM_PWDN
C709 : VGA_VDD_1.8V
R718 : VGA_CAM_PCLK
4. TROUBLE SHOOTING
- 144 -
4.14 Main LCD trouble
Main LCD control signals are generated by MSM6280. Those signals path are :
MSM6280 Z ORAN (Multimedia Chip) -> 40-pin connector(CN300 in Main PCB) -> 40-pin connector
(in LCD Module)
The LCD works
START
Press END key
to turn the power on
Is the circuit powered?
Follow the Power ON
trouble shooting
LCD display OK?
Check LCD_VDD_2.8V, LCD_RESET_N,
LCD_DATA[0~15] in Main BD
No
Yes
Yes
No
Disconnect and reconnect
40-pin B to B connector
Change the Main BD
No
End
Yes
Display OK?
Yes
Change the LCD module
No
4. TROUBLE SHOOTING
- 145 -
Main BD
SUB BD
LCD_NRESET
LCD_VDD_2.8V
LCD_DATA[0~15]
- 146 -
4. TROUBLE SHOOTING
OTP Program Pin
ENBY0036001
1.0T, Socket
GB042-40S-H10-E3000
7
INOUT_B3
INOUT_B4
6
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
C
3
2
2
2
2
p
C
3
2
3
2
2
p
R315 51
2
2
p
C
3
2
5
VA300
ICVN0505X150FR
25
26
27
28
29
9
21
30
31
32
33
34
35
36
37
38
39
22
40
23
24
12
13
14
15
16
17
18
19
2
20
3
4
5
6
7
8
CN300
1
10
11
VA301
51 R314
NA
C320
C326
22p
G
2
1
INOUT_A1
INOUT_A2
2
3
INOUT_A3
INOUT_A4
4
INOUT_B1
9
8
INOUT_B2
INOUT_B3
7
6
INOUT_B4
5
G
1
1
0
51 R316
R318 0
5
G
1
1
0
G
2
1
INOUT_A1
INOUT_A2
2
3
INOUT_A3
INOUT_A4
4
INOUT_B1
9
8
INOUT_B2
INOUT_B3
7
6
INOUT_B4
51 R317
2
2
p
C
3
2
4
0.1u
C321
6
G
1
5
G
2
1
0
INOUT_A1
1
2
INOUT_A2
INOUT_A3
3
4
INOUT_A4
9
INOUT_B1
INOUT_B2
8
7
INOUT_B3
INOUT_B4
LCD_VDD_2.8V
LCD_VSYNC_OUT
LCD_MAKER_ID
MMP_LCD_WE_N
MMP_LCD_VSYNC_OUT
WLED_PWR
WLED_2
WLED_4
WLED_5
MMP_LCD_VSYNC_IN
LCD_IF_MODE
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[14]
LCD_DATA[15]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
LCD_DATA[12]
LCD_DATA[13]
WLED_1
WLED_3
MMP_LCD_ADS
MMP_LCD_CS_N
LCD_RESET_N
MMP_LCD_RD_N
MMP_LCD_DATA[9]
MMP_LCD_DATA[10]
MMP_LCD_DATA[11]
MMP_LCD_DATA[12]
MMP_LCD_DATA[13]
MMP_LCD_DATA[14]
MMP_LCD_DATA[15]
LCD_DATA[12]
LCD_DATA[13]
LCD_DATA[14]
LCD_DATA[15]
MMP_LCD_DATA[0]
MMP_LCD_DATA[1]
MMP_LCD_DATA[2]
MMP_LCD_DATA[3]
MMP_LCD_DATA[4]
MMP_LCD_DATA[5]
MMP_LCD_DATA[6]
MMP_LCD_DATA[7]
MMP_LCD_DATA[8]
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
Schematic of LCD part
C321 : LCD_VDD_2.8V
C326 : LCD_VDD_2.8V
FL300
FL301
FL302
FL303
- 147 -
4. TROUBLE SHOOTING
4.15 Bluetooth trouble
Bluetooth supplied voltages are generated by the PM6650.
Those signals path are : PM6650 VREG_MSMP_2.7V and VREG_BT_2.85V is asserted
TCXO_BT 19.2MHz is asserted Bluetooth ON BT_TX_RX_N is High BT serial interface
control is operated (SBST / SBCK / SBDT)
BLUETOOTH
LG INNOTEK
TP802
TP801
1
0
K
R
8
0
9
C804
1u
C802 1000p
0
R807
C803
1u
C800 NA
0
R
8
0
0
BT_ANT
C814
2.2u
C811
100p
C812
0.1u
G
N
D
3
G
N
D
4
1
5
1
7
P
G
N
D
1
P
G
N
D
2
1
8
1
9
P
G
N
D
3
P
G
N
D
4
2
0
RX_BB_TX_BB
13
SBCK
11
12
SBDT
SBST
4
5
SYNC_DET_TX_EN
3
VCC_OUT
14
VDD_BAT
VDD_INT
2
VDD_MSM
10
7
XTAL_IN
M800
LBRQ-2B43A
A
N
T
1
6
9
CLK_REF
1
G
N
D
1
G
N
D
2
6 8
BT_GND
100p
C813
C801
NA L800
1000p
VREG_BT_2.85V
VREG_MSMP_2.7V
TP800
1
0
K
R
8
0
8
BT_DATA
BT_CLK
BT_SBCK
BT_SBDT
BT_SBST
BT_TX_RX_N
TCXO_BT
TCXO
0.1u
C139
C147 1000p
100ohm R115
1000p
C145
0.01u
C141
8200p C148
1000p
C140
X100
2
GND OUT
3
VCC
4
VCONT
1
19.2MHz
R120 100K
TC7SH04FS
U102
C144 1000p
TCXO_BT
VREG_BT_2.85V
TCXO_PM
RTR6275_TCXO
Figure. Schematic of Bluetooth Interface
4.16 Bluetooth RF Test
TC-3000A (Bluetooth Tester)
1. Set phone to bluetooth test-mode.
- Enter Test Mode(3845#*990#) Module Test Set BT DUT BT DUT ON
2. Insert a phone in a TEMSELL (in case of radiation test)
3. Set discover after push menu button of the tester and select the link analyzer .
4. After set test mode, confirm the connection state.
5. Measure the power of full channel after hopping mode is selected to ON
6. You can select wanted test cases after getting an optimized power
- 148 -
4. TROUBLE SHOOTING
M800
BT_ANT
BT Antenna
TP800 TP801
TP802
BT_GND
R800
Set the bluet oot h ON
VREG_BT_2.85V
and
VREG_MSMP_2.7V
is asserted?
Check PMIC
(U501) Pin#64
XTAL_IN
is asserted?
Check Os ci llator
(X100)
And
Check Buffer
(U102)
CLK_REF
is asserted?
Check sol deri ng
of BT( M800)
No
No
No
Yes
Yes
Yes
SYNC_DET_TX_EN

is asserted?
Check sol deri ng
of BT( M800)
No
Yes
SBST/SBCK/SBDT
is asserted?
Check
TP800/TP801/ P802
No
Yes
Bluet oot h is work well?
Change
the main board
END
No
Yes
- 149 -
4. TROUBLE SHOOTING
4.17 Touch Screen trouble
Touch Initial sequence of KU990R is:
LCD_VDD_2.8V(C701) goes to 2.8V TOUCH_PENIRQ_N(R702),TOUCH_I2C_SCL(R703) &
TOUCH_I2C_SDA(R704) go to high Touch operation of KU990R is :
A finger is touching on the screen -> TOUCH_PENIRQ_N is low -> I2C is connected -> A finger is
took off from the Screen -> TOUCH_PENIRQ_N is high -> I2C is not connected.
Start
Work well?
Connector Is insert?
Replace the Main board
End
Insert Connector, again
Yes
No
YES
NO
Touchpad Calibration
Replace the Folder
Work well? End
Yes
No
R702 (TOUCH_PENIRQ_N)
R704(TOUCH_I2C_SDA)
U700
R703 (TOUCH_I2C_SCL)
C701 (LCD_VDD_2.8V) Touch Window Connector
VGA FPCB Connector
- 150 -
4. TROUBLE SHOOTING
4.18 Lens cover detection trouble
Lens cover initial sequence of KU990R is :
VREG_MSMP_2.7V(C384) goes to 2.7V CAM_COVER_DET(R318) go to high
Lens cover operation of KU990R is :
Lens cover is opened CAM_COVER_DET is low Camera is operated Lens cover is closed
CAM_COVER_DET is high Camera operation is stopped.
Start
Camera Is
operated
Connector Is insert?
Replace the rear case
End
Inser t Connector, again
Yes
No
YES
NO
Lens Cover i s opened
Replace t he Sub PCB
Work w ell? End
Yes
No
C318 (CAM_COVER_DET)
C348 (VREG_MSMP_2.7V)
CN801 (Connector)
U800
A3212EELLT-T
G1
G2 OUT
VDD
1
0
0
K
R
3
1
8
VREG_MSMP_2.7V
10p
C349 C348
0.1u
CAM_COVER_DET
- 151 -
5. DOWNLOAD
5. DOWNLOAD
5.1 Introduction
LGMDP is a LGE application that allow users to download images from PC to handset. LGMDP is a
download tool with capabilities to upload image files to the handset. LGMDP is designed to be simple
to use and easy enough for the beginner to upload executable images to the handset. LGMDP
supports Windows 2000/XP where the LG (Ver 4.6 or later) USB modem driver is installed.
Additionally, LGMDP allows multi downloading up to 9 handsets at the same time.
5.2 Downloading Procedure
Connect the phone to your desktop PC using the USB cable and run the LGMDP application. Before
getting started, set up LGMDP preferences from the Preferences of the file menu the way you want.
Click on the File menu and select Preferences.
Play a success sound
It will be played a .wav file when the download has been completed. To enable this simply check the
box.
Always on Top
Check if LGMDP always appears at the top of the window so that user can monitor it all the time.
Automatically run Select Port When LGMDP starts
When LGMDP starts, it will automatically select Select Port button to download new image file.
- 152 -
5. DOWNLOAD
5.2.1 Connecting to PC
Click on the Select Port and then Select Port window will be pop up. Check if state shows Enable for
the port to be connected for downloading images. Then click on the Connect button.
(The port number(COM7) shall be different from that of the port number in the snapshot.)
- 153 -
5. DOWNLOAD
The status Ready is displayed when the application is ready for downloading. While the images are
transmitted from PC to the handset, a progressive bar
(Red box) indicating the degree of transmission of data is displayed.
- 154 -
5. DOWNLOAD
1) Image Folder indicates loot path where all image files are placed. To change location of the default
image path, select Browse... button. The edit box shows the file path where images are located.
Please note that all images should be located in a selected folder.
2) Click on the Browse... button to select image files to be downloaded on the handset.
3) NV Backup/Restore: NV Backup/Restore always have to be done, and it is default selected option.
Backup the NV data and restore the backed up NV data automatically.
1)
2)
3)
6) 4)
5)
7)
- 155 -
5. DOWNLOAD
4) Reset database & Contents:
User related data including the setting data on the EFS is reset in the handset. The user contents in
the handset will be erased. If you want to reset all the user data back to the way they were before
you started downloading new images, check the option.
Erase_EFS:
The calibration data, user contents, media, and module are erased. Only calibration data is kept when
NV backup/restore is checked. The user contents and file system physically are wiped out.
Keep All Contents
Maintain user data including WAP, AD, DRM, E-mail, Play lists, and images when downloading a new
S/W images. User data stated above are maintained if this option is selected.
5) Additional Options:
Display Information is defaultly not selected and user cannot choose.
Override partition table is also also defaultly not selected and user cannot choose.
6) Clear: Clearing all directory paths of images in the dialog.
7) Start: Starting downloading the selected individual image.
5. DOWNLOAD
- 156 -
5.2.2 Choosing image files
Select the image folder, where all the image files are located, by clicking on the Browse....
(The folder name shall be different from that of the folder name in the snapshot. The folder name
indicates the path where the image files are located.)
5. DOWNLOAD
- 157 -
Select the path on the Image Folder by clicking on the Browse..., then the LGMDP will automatically
load images accordingly. Also you can select images by manually. For instance, select the path of
AMSS Modem Image file by clicking on the Browse... button. The selected AMSS image will be
downloaded to the handset from the path directory in the PC. Make sure that you have chosen
correct file. In case of wrong AMSS Modem file is selected, the phone may not work.
(The file name shall be different from that of the file name in the snapshot.)
5. DOWNLOAD
- 158 -
If NV restore is failed, then the NV Data(*.nv2) is erased permanently. In this case, choose the
desired NV file to be downloaded on the handset. To enable this simply check the box or select the
NV file from the LGMDP installation directory by clicking on the Browse... button.
5. DOWNLOAD
- 159 -
Click on the START button to start downloading. A summary of the selected images and option
information window will be displayed. Click on the No button if this is not the setting you are
downloading for. Otherwise click on the Yes button to continue downloading selected image file with
options.
No Yes
5. DOWNLOAD
- 160 -
This message box informs that a new file for
NV backup will be created in the displayed
file name in the LGMDP installation
directory.
Backing up NV data and backed up NV data
will be stored in the LGMDP installation
directory.
Erasing the existing directories and files
before the Module image is downloaded.
Downloading the AMSS modem image
5.2.3 Downloading
5. DOWNLOAD
- 161 -
Rebooting the handset and re-establishing
the connection
Restoring NV data which backed up in the
Backing up process. User can also restore
NV data using NV Default image selection.
Rebooting the handset and re-establishing
the connection
Erasing the existing directories and files
before downloading the selected Media
image
5. DOWNLOAD
- 162 -
Downloading Media image in progress
Downloading Module image in progress
Downloading process has completed
successfully
- 163 -
5. DOWNLOAD
5.2.4 Tools
Device Manager allows to monitor current hardware that is installed on your PC. Device Manager is
designed to monitor USB connectivity and check where the COM has been installed . Select Device
Manager from the Tools of the file menu.
- 164 -
5. DOWNLOAD
5.3 Troubleshooting Download Errors
5.3.1 When the phone does not work
Reboot the phone in the emergency mode (Simultaneously press 2, 5, and PWR red keys) and
then try to download all the images up to AMSS. In the emergency mode, you can not download
media or module image.
The phone supports a special mode called emergency mode. In this mode, minimum units for
downloading is running so that users can download the images again in case of emergency
situation. (AMSS modem, Media, and Module images can not be running in this mode.)
The below dialog shows parameters of Select Port when phone is booted in Emergency mode.
Click on the Connect button to continue.
- 165 -
5. DOWNLOAD
Choose Image file after clicking on the Browse... button. Make sure that you have chosen the right
image file. After choosing valid images, then click on the Start button to start downloading selected
images. The selected image will be downloaded to the handset from the path directory in the PC.
After downloading images successfully, it will boot to normal mode.
- 166 -
5. DOWNLOAD
5.3.2 NV Restore Error
Snapshot showing the NV Restore error. Next slide shows the remedial procedure to adopt.
- 167 -
5. DOWNLOAD
Connect the handset and Press the Connect button in the Select Port window.
(Enable state in the window indicates that the Phone has been detected and is ready to download.)
- 168 -
5. DOWNLOAD
Click on Browse... . Select the LGMDP installation directory and a list of NV Backup files(*.nv2) will
be shown. These nv files were saved every time NV Backup option was selected, and the name of
the nv file is determined based on the time when NV Backup was done. Choose the desired NV file
to be downloaded on the handset, and click on Start.
- 169 -
5. DOWNLOAD
5.4 Caution
1) Multi-downloading using the USB hub is not recommendable.
2) If you see the message cal mode after completing download, you must do NV restore and image
(media and module) download.
3) The NV data saved at LGMDP folder as following format.
4) Recommended that the Module and Media Image have to be downloaded at the same time.
5) Erase EFS option will erase everything (media, module, nv items, and user data) in the EFS area.
D:\LGMDP\004400-01-429926\_COM14_
LGMDP folder name
IMEI number
Port number
- 170 -
6. BLOCK DIAGRAM
6. BLOCK DIAGRAM
6.1 GSM & UMTS RF Block
[Figure 2.1] UMTS-2100 + EGSM-900/DCS-1800/PCS-1900 RF Functional Block Diagram
- 171 -
6. BLOCK DIAGRAM
[Table 2.1] RF Block Component
Block Ref. Name Part Name Function Comment
FL100 LSHS-M090UH Front End Module ASM+Rx Saw
SW100 KMS518 Test Connector Calibration, etc
X100 TG-5010LH_19_2M VCTCXO 19.2MHz
Common
U100 RTR6275 RF Transceiver IC TRX
M800 LBRQ-2B43A BT RF Transceiver BT TRX Bluetooth

FL103 SAYZ1G95EB0B00 Duplexer TRX
FL102 EFCH2140TDE1 RX SAW Filter RX
FL104 EFCH1950TDF1 TX SAW Filter TX
U105 AWT6277R TX PAM TX
UMTS
U104 CP0402A1950DNTR Coupler TX
U101 TQM7M5003 TX Dual PAM TX GSM
FL101 EFCH897MTDB1 Tx SAW Filter Tx
- 172 -
6. BLOCK DIAGRAM
6.2 Interface Diagram
[Figure 2.2] U990 Interface Diagram
- 173 -
6. BLOCK DIAGRAM
Main RF signal
Control signal
Main RF signal Description Comment
GSM 900 TX GSM 900 TX RF Signal
DCS TX DCS TX RF Signal
PCS TX PCS TX RF Signal
W- TX UMTS2100 TX RF Signal
GSM 900 RX GSM 900 RX RF Signal
DCS RX DCS RX RF Signal
PCS RX PCS RX RF Signal
W- RX UMTS2100 RX RF Signal
TX_I/Q I/Q for Tx of RF
RX_I/Q I/Q for Rx of RF
Control signal Description Comment
UMTS PA_CTL signal
PA_R1 UMTS Tx High/Low Power Control
PA_ON Power Amp. Enable
GSM PA_CTL signal
GSM_PA_BAND DCS or PCS /GSM Mode Selection
GSM_PA_EN Power Amp. Gain Control Enable
GSM_PA_RAMP Power Amp. Gain Control
RF Tranceiver_CTL signal
TX_ON RF Enable Signal
SSBDT_RTR Bidirectional SSBI Data
TX_AGC_ADJ UMTS Transmit Gain Control
FEM_CTL signal
ANT_SEL 0,1,2 Ant Switch Module Mode Selection
UMTS,
GSM900Tx/Rx,
DCS Tx/Rx,
PCS Tx/Rx
- 174 -
- 175 -
10 dB
LOW
HIGH
7
1
A
5 3
D
LOW
H
ANT_SEL0
12 7
1
3
GSM
6 8
C
GSM 1800/GSM 1900 TX
8 dB
HIGH
7
LOW
B
E
GSM
1 7
E
2
TCXO
PQ
PQ
PCS
HIGH
12 9
F
GSM
HIGH
H
3
D
Rev. 1.1
4
G
10
GSM_PA_BAND
6
(1%)
8
B
F F
VTUNE-Connected directly to GND
C C
LOW
LOW
F
4
5
4
DCS/PCS
B
GSM 850 RX
LOW
HIGH
8
E
2
H
5
LOW
11
LOW
10
WCDMA
GSM 850/GSM 900 TX
HIGH
H
MODE
D
WCDMA
ANTENNA SWITCH MODULE LOGIC
G
A
9
GSM 1900 RX
DCS
9
12 6
G
LOW
LOW
10
A
FM RADIO
HIGH
near to 48pin
6
11 10
Thermistor circuit deleted
B
HIGH
D
8
(1%)
11 12
4
LOW
E
LOW
3
PQ
PQ
2
LOW
9
2
HIGH
G
8 dB
1
ANT_SEL1 ANT_SEL2
5
A
11
SMPS circuit for RF
20dB
HIGH
C
GSM 900 RX
GSM 1800 RX
2
G1
3
G2
5
G3 1 IN
4
O1
R125
100
FL104
EFCH1950TDF1
2.7nH
L117
1nH
L115
C143
68p
L106 5.6nH
C130
22u
TP100
C164
1u
2.2p
C
156
L110
22nH
R104 5.1
100p
C166
C102
L101
15nH
22u
4.7nH
2
A
N
T
G
N
D
1
14
G
N
D
2
G
N
D
3
8
9
G
N
D
4
6
G
N
D
5
3
G
N
D
6
R
X
7
TX
5
C118
FL103
SAYZY1G95EB0B00
R111
68
22nH L111
ANT102
1000p
C116
12p
C144
180p
C107
C132
0.01u
180p
0.1u
C
120
C103
3.3nH
L124
L126
10K
8.2nH
5.6nH
R
121
L108
L105 5.6nH
0
R102
C106 6p
1u
C125
O2
R
122
100K
EFCH2140TDE1
FL102
2
G1
5
G2 1
IN
3
O1
4
22p
C126
C101 120p
56p
C154
C127
15 GND7 17 GND8
GND9 18
7 NC
22 PCS_RX1
21 PCS_RX2
PGND1 25
PGND2
26
UMTS_TX_RX 8
5 VC1
VC2 4
3 VC3 6 VDD
100p
FL100
10 ANT
13 DCS_PCS_TX
20 DCS_RX1
DCS_RX2 19
24
EGSM_RX1
EGSM_RX2 23
16 EGSM_TX
GND1 1
GND2 2
9 GND3
GND4 11
GND5
12
GND6 14
LSHS-M090UH
R103 NA
C114
47p
R101
680
L100
5.6p
12K
R100
C110
180p
TC7SH04FS
U102
4.7nH
L128
C157
TP101
0.1u
R123
68
C134
1000p
R120 100K
C158
0.5p
1u
C155
8.2p
C171
C159
C G1G2
56p
SW100
KMS-518
A
DCS_PCS_IN
15
D
C
S_PC
S_O
U
T
GND1 5
8 GND2
GND3 10
GND4 11
GND5 13
GND6 14
16
G
N
D
7
G
N
D
8
17
GSM_IN 7
GSM_OUT 9
TX_EN 3
4 VBATT
VCC 12
6 VRAMP
U101
TQM7M5003
BS 2
1
L109 22nH 2.7 R107
X100
19.2MHz
GND
2 3
OUT
4 VCC 1 VCONT
FL101
EFCH897MTDB1 G1
2
G2
3
G3
5
IN
1 O1
4
L107
C
119
0.1u
15nH
C152
3.9p
0.75p
C142
1nH
15nH
L112
L119
C148 8200p
56p
C161
1.8p
C170
C100
180p
O
U
T
1
TP103
SCDY0003403
U104
4
50O
H
M
C
O
U
P
3
IN
2
10p C146
1nH
L116
ANT100
100p
C131
C111
10
R
109
3300p
91
R113
0.1u
C129
C140
1000p
C108
51
5p
R114
L103 5.6nH
56p
ANT101
C153
VMODE
4
5 VREF
C137
1u
AWT6277R
3 GND1
6 GND2
GND3
7
GND4 9
11 GND5
RFIN 2
8 RFOUT
1 VCC1 VCC2 10
C167
U105
4.7nH
56p
L113
C169 5.6p
C113
47p
C
124
0.1u
R117 2.2K
100p
C163
R115 100ohm
22p
C128
19
20 VDDA8
VDDA9 28
17
VD
D
M
5 VTUNE1
VTUNE2 18
WLNA_IN 26
29
W
LN
A
_O
U
T
W
M
IX_IN
N
35 34
W
M
IX_IN
P
TX_IN
51 TX_IP
TX_QN 52
53 TX_QP
56 VCONTROL
VDDA1
4
41 VDDA10
VDDA11 45
47 VDDA12
VDDA13 48
49 VDDA14
VDDA2 6
8 VDDA3
VDDA4 9
15 VDDA5
VDDA6 16
VDDA7
HB_RF_OUT1 44 HB_RF_OUT2
LB_RF_OUT1 43
42 LB_RF_OUT2
57
PG
N
D
PWD_DET_IN 40
RF_ON 24
RX_IN 13
12 RX_IP
11 RX_QN
RX_QP
10 3
R_BIAS1 27 R_BIAS2
14 SBDT
TCXO 7
TEST 21
50
23 CAL_INN
CAL_INP 22
DAC_REF 54
39 DCS_INN
DCS_INP 38
33 EGSM_INN
EGSM_INP 32
ENV_LNN 1
2 ENV_LNP 55 ENV_OUT
30 GCELL_INN
31 GCELL_INP
G
N
D
25
37 GPCS_INN
GPCS_INP 36
46
U100
RTR6275
C109
47p
L127
100nH
C136 8p
22u
C160
1000p
C145
C173
TP102
100p
L102
NA
C150
56p
0.1u
2
4
5
3
1
C168
KRX102E
Q100
0.01u
C162
0.01u
C141
L118
C
121
1nH
15nH
0.1u
L123
C112 1000p
22p
C149
C115
47p
27p
C172
0.1u
C
122
1000p C147
R112
C
123
91
0.1u
1.5nH
L114
C117 22p
L120
47nH
L121
2.2nH
VCCVCO
D1 VDD
E3 VREFDIG
0.01u
C151
D3
C1 FREQIN
INTX B2
D5 ISS
A3 LO1
A4 LO2
A2 LOOPSW MPXOUT E4
C5 RFGND
B6 RFIN1
RFIN2 C6
B1 SWPORT
TMUTE D6
E5 VAFL
E6 VAFR
VCC A6
A5
TEA5766UK U103
AGND B5
BUSEN C2
CLOCK E2
CPOUT A1
DATA E1
DGND1 D2
DGND2
120
R118
R124
51
NA
L122
R126
100
C138
NA
C105 56p
C135
33u
C165
NA
C104
0.75p
C133
22p
L125
0.1u
1nH
15nH
C139
120
L104
TX_AGC_ADJ
DAC_REF
R119
WCDMA_MIX_IN_M
WLNA_OUT
RX_WCDMA_2100
VREG_MSMP_2.7V
VDD_RX
VREG_RF_SMPS
VREG_SYNTH_2.6V
VREG_RF_SMPS
TX_QP
TX_QM
TX_IP
TX_IM
RTR6275_TCXO
SSBDT_RTR
RX_QP
RX_QM
RX_IP
RX_IM
TX_ON
PWR_DET
VREG_RF_SMPS
ANT_SEL2
WCDMA_2100_TX_OUT
I2C_SDA
I2C_SCL
FM_INTX
SLEEP_CLK
GSM_PA_BAND
+VPWR
WCDMA_MIX_IN_P
PA_ON
VREG_TCXO_2.85V
+VPWR
WCDMA_2100_TX_OUT
DCS_PCS_TX
GSM_TX
DCS_PCS_TX
GSM_TX
PA_R1
WLNA_OUT
WCDMA_MIX_IN_M
WCDMA_MIX_IN_P
VDD_RX
ANT_SEL0
ANT_SEL1
TCXO_BT
VREG_BT_2.85V
TCXO_PM
RTR6275_TCXO
FM_ANT
VREG_MSMP_2.7V
VREG_MMC_3.0V
FM_BUSEN
FM_AUDIO_R
FM_AUDIO_L
RX_WCDMA_2100
PWR_DET
GSM_PA_RAMP
GSM_PA_EN
7. CIRCUIT DIAGRAM
- 176 -
11 12
E
C
w18 (Analog VSS guard ring for CODEC)
MSM pin W18
D12(VDDA1) and F12(DAC_REF)
D
6
MODE
E
10%
Place near
0
( Default Pull-Down)
1
D
Near to B18 (VDD_PLL)
PMIC_AUXIN[1]
5
11
4 7
5 6
F
Trusted boot
(VDD_DAC_REF)
A
this pin can be grounded as in MSM6275
E
1
MSM pin AD26
8
G
3 9 1 0
If you are not Qfuse (security),
B
C
PMIC_AUXIN[2] - PA_THERM
2
B
8-bit, NAND boot
D
A
10 12 2
H
Native, MSM JTAG
6 9
G
7
0 0 0
F
1 1
F
( +/- 2500ppm for USB Peripheral )
G
Normal boot
BOOT_MODE3
H
7
HKADC[0] - AMUX_OUT
9
(CODEC VSS)
4 3
7 2
2
8 4
1
10
9
4
A
for VSS_THERMAL
HKADC[3] - REMOTE_ADC
1%
Native, ARM JTAG
MODE2 MODE1 MODE0
(CAD : 10uF=>Input MSMA_2.6V)
BOOT_MODE2 BOOT_MODE
10%
(WCMDA 2100 PAM Enable)
3 5
8 12
B
0 1 0
12
1%
B
5
H
E
A
8
PCB_Rev_ADC
0 1
10
D
USB 48M CLK
X 0
HKADC[5] - VBATT_TEMP
11
F
NOR boot HKADC[4] - PCB_Rev_ADC
C
3
ADC
6
HKADC[1] - VBATT_SENSE
HKADC[2] - HDET1
16-bit, NAND boot
Place near
10%
1
G
11
C
(PLLOUT_TEST)
1
2200p cap => place between
H
R201
47K
0.01u
C214
C230
0.1u
4.7u
C239
0.1u
VREG_MSMA_2.6V
C238
R213
NA
0.01u 0.01u
C219 C220
C226
1000p
1000p
C217
51
R
207
0.1u
C215
VREG_MSMP_2.7V
VREG_MSMP_2.7V
C232
0.1u
VR
EG
_M
SM
P_2.7V
R202
150K
C225
1u
1M
R200
C228
0.1u
C
204
N
A
VREG_MSMP_2.7V
0.01u
VREG_MSMC_1.2V
C213
C
236
0.1u
33nF
C222
C223
2200p
R
205
51K
C216
0.1u
0.1u VR
EG
_M
SM
E_1.8V
R211 2K
C
235
C231
0.01u
R210 0
R
204
51K
2.2K
R217
100K
R
206
N
A
R
209
48MHz 1
3
2
X200 ICRT20S48M0X514CR
C210
0.01u
C229
0.1u
0.01u
C211 C212
0.1u
C218
1000p
0 R215
R
203
C
237
N
A
N
A
100nH
0.01u
L200
C221
R218
2.2K
U1
VSS_PAD1_4
VSS_PAD2_0
AF6
AF11
VSS_PAD2_1 AF15
VSS_PAD2_2
VSS_PAD3_0
R26
B17
VSS_PAD3_1
VSS_PAD3_2
A15
VSS_PAD3_3
A9
VREG_MSME_1.8V
VR
EG
_M
SM
P_2.7V
VSS_DIG_1
H1
A14
VSS_DIG_10
VSS_DIG_11
A11
VSS_DIG_12
A5
W1
VSS_DIG_2
VSS_DIG_3
AC1
VSS_DIG_4
AF8
VSS_DIG_5
AF16
VSS_DIG_6
T26
G26
VSS_DIG_7 D26
VSS_DIG_8 A24
VSS_DIG_9
VSS_PAD1_0
F1
VSS_PAD1_1
K1
M1
VSS_PAD1_2 R1
VSS_PAD1_3
VSSA11
AB26
AC16
VSSA12
VSSA13
AC26
AD25
VSSA14 AF23
VSSA15 AF24
VSSA16
VSSA2
A21
D13
VSSA3 D19
VSSA4
VSSA5
P26
VSSA6
U19
VSSA7
V26
W16
VSSA8 W18
VSSA9
VSS_DIG
AC23
VSS_DIG_0
C1
AC4
VSS41
VSS43
AE1
AE2
VSS44
VSS45
AE25
AE26
VSS46 AF1
VSS47 AF2
VSS48
VSS49
AF25
VSS5
B1
AF26
VSS50
B2
VSS6
VSS7
B25
B26
VSS8
VSS9
D4
A18
VSSA1
VSSA10
W26
VSS26
N15
P12
VSS27
VSS28
P13
P14
VSS29
VSS3
A25
P15
VSS30
R12
VSS31
VSS32
R13
R14
VSS33
VSS34
R15
T11
VSS35
VSS36
T16
W
8
VSS37
W
19
VSS38
VSS39
AA6
A26
VSS4
F6
VSS11
VSS12
F21
VSS13
H8
H19
VSS14
K10
VSS15
L11
VSS16
L16
VSS17
VSS18
M
11
M
12
VSS19
A2
VSS2
VSS20
M
13
M
14
VSS21
VSS22
M
15
N12
VSS23
VSS24
N13
N14
VSS25
F2
VD
D
_PA
D
1_0
K2
VD
D
_PA
D
1_1
VD
D
_PA
D
1_2
M
2
VD
D
_PA
D
1_3
R2
VD
D
_PA
D
1_4
U2AE6
VD
D
_PA
D
2_0
AE11
VD
D
_PA
D
2_1
AE15
VD
D
_PA
D
2_2
R25
VD
D
_PA
D
3_0
K25
VD
D
_PA
D
3_1
VD
D
_PA
D
3_2
B15
VD
D
_PA
D
3_3
B9
VD
D
_PA
D
4_0
A3B18
VD
D
_PLL
VSS1
A1
D23
VSS10
VD
D
A
8
AE24
VD
D
A
9
AA16
C2
VD
D
_D
IG
_0
H2
VD
D
_D
IG
_1
B14
VD
D
_D
IG
_10
B11
VD
D
_D
IG
_11
VD
D
_D
IG
_12
B5
VD
D
_D
IG
_2
W
2
VD
D
_D
IG
_3
AC2
VD
D
_D
IG
_4
AE8
VD
D
_D
IG
_5
AE16
T25
VD
D
_D
IG
_6
VD
D
_D
IG
_7
G25
VD
D
_D
IG
_8
D25
B24
VD
D
_D
IG
_9
VD
D
_M
D
D
I
B21
U200-2
MSM6280_B
AA21
NC
C26
RESERVED
VD
D
A
1
D12
AF17
VD
D
A
10
VD
D
A
2
P23
U25
VD
D
A
3
VD
D
A
4
U26
VD
D
A
5
Y26
VD
D
A
6
AA26
AE23
VD
D
A
7
XM
EM
1_C
S_N
0
W
6
AA1
XMEM1_CS_N1_GPIO76
Y4
XM
EM
1_C
S_N
2_SD
R
A
M
1_C
S_N
0
XMEM1_CS_N3_SDRAM1_CS_N1_GPIO77
Y6
XM
EM
1_H
W
A
IT_N
AA2
XM
EM
1_LW
A
IT_N
_SD
R
A
M
1_C
A
S_N
K8
XMEM2_CS_N0
W14
XMEM2_CS_N1
AC15
XMEM2_CS_N2_GPIO35
W15
AA15
XMEM2_CS_N3_GPIO36
M
21
U
A
R
T3_D
P_R
X_D
A
TA
_G
PIO
85
U
A
R
T3_D
P_TX_D
A
TA
_G
PIO
84
M
19
L25
UART3_RFR_N_GPIO87
U
B
1_N
_SD
R
A
M
1_D
Q
M
1
M
6
UB2_N
AF10
U
SB
_D
A
T_VP
N26
N25
U
SB
_O
E_TP_N
USB_RX_DATA_GPIO29
N19
U
SB
_SE0_VM
N23
U
SB
_XTA
L48_IN
A10
B10
U
SB
_XTA
L48_O
U
T
R16
VD
D
_EF_U
SE
AE17
W
D
O
G
_EN
WDOG_STB_SBCK1_GPIO0
H25
U8
W
E1_N
_SD
R
A
M
1_W
E_N
WE2_N
AF4
TDI
D15
TDO
A17
TMS
F15
TRK_LO_ADJ
L13
H15
TRST_N
H13
TX_AGC_ADJ
TX_ON_GRFC10
H12
P16
U
A
R
T1_C
TS_N
_G
PIO
97
U
A
R
T1_D
P_R
X_D
A
TA
_G
PIO
96
M
23
U
A
R
T1_D
P_TX_D
A
TA
_G
PIO
95
L26
P21
U
A
R
T1_R
FR
_N
_PA
_PO
W
ER
_C
TL_M
_G
PIO
98
G6
U
A
R
T2_C
TS_N
_G
PIO
90
H6
UART2_DP_RX_DATA_GPIO89
U
A
R
T2_D
P_TX_D
A
TA
_G
PIO
88
E4
U
A
R
T2_R
FR
_N
_G
PIO
91
F4
L23
U
A
R
T3_C
TS_N
_G
PIO
86
SDRAM1_D2
AB2
D1
SDRAM1_D3
AB4
SDRAM1_D4
J6
SDRAM1_D5
G2
SDRAM1_D6
SDRAM1_D7
H4
P4
SDRAM1_D8
SDRAM1_D9
J4
A16
SLEEP_XTA
L_IN
B16
SLEEP_XTA
L_O
U
T
F18
SYNTH0_GP_PDM0_GPIO92
SYN
TH
1_G
PIO
41
H23
B6
SYNTH2_GPIO65
TCK
D16
TC
XO
D18
TCXO_EN_GPIO94
F19
J23
SB
D
T
F26
SBDT1_GPIO1
H26
SB
ST
SBST1_GPIO93
H18
SDCC_DAT1_GPIO99
F25
M25
SDCC_DAT2_GPIO100
SDCC_DAT3_GPIO101
M26
N4
SD
R
A
M
1_C
LK
_EN
E2
SDRAM1_D0
D2
SDRAM1_D1
J2
SDRAM1_D10
K6
SDRAM1_D11
J1
SDRAM1_D12
SDRAM1_D13
K4
L8
SDRAM1_D14
SDRAM1_D15
L6
PA_ON1_GPIO2
H11
P25
PA
_PO
W
ER
_C
TL
AA25
Q_IM_CH0
Q_IM_CH1
W23
Y25
Q_IP_CH0
Q_IP_CH1
V23
B12
Q_OUT
A12
Q_OUT_N
R
ESIN
_N
F13
R
ESO
U
T_N
F11
AA4
R
ESO
U
T_N
_EB
I1
R
IN
G
ER
_G
PIO
18
L19
G1
R
O
M
1_A
D
V_N
_SD
R
A
M
1_R
A
S_N
AB1
R
O
M
1_C
LK
_SD
R
A
M
1_C
LK
RTCK
H16
L21
SB
C
K
AE3
MDP_VSYNC_SECONDA_GPIO104
M
IC
1N
AF20
M
IC
1P
AE20
AF21
M
IC
2N
AF22
M
IC
2P
M
IC
B
IA
S
T15
M
16
M
M
C
_C
LK
_SD
C
C
_C
LK
_G
PIO
31
M
M
C
_C
M
D
_G
PIO
30
H14
L14
M
M
C
_D
A
TA
_SD
C
C
_D
A
T0_G
PIO
32
M
O
D
E0
Y23
M
O
D
E1
U23
T21
M
O
D
E2
T14
NAND2_FLASH_READY_GPIO33
O
E1_N
V2
AF7
OE2_N
PA_ON0
F17
AE13
LCD_EN_GPIO37
LIN
E_L_IN
AC21
AC22
LIN
E_L_IP
AC18
LIN
E_O
N
LIN
E_O
P
AC17
AC20
LIN
E_R
_IN
LIN
E_R
_IP
AC19
MDDIC_DATN
A23
A22
MDDIC_DATP
MDDIC_STBN
B23 MDDIC_STBP
B22
M
D
D
IH
_D
A
TN
B19
B20
M
D
D
IH
_D
A
TP
M
D
D
IH
_STB
N
A19
A20
M
D
D
IH
_STB
P
MDP_VSYNC_PRIMARY_GPIO105
AD2
N16
I2C
_SC
L_G
PIO
27
K21
I2C
_SD
A
_G
PIO
26
AB25
I_IM_CH0
V25
I_IM_CH1
AC25
I_IP_CH0
I_IP_CH1
W25
I_OUT
B13 I_OUT_N
A13
R21
K
EYSEN
SE0_N
_G
PIO
62
K
EYSEN
SE1_N
_G
PIO
63
P19
K
EYSEN
SE2_N
_G
PIO
46
D14
K
EYSEN
SE3_N
_G
PIO
47
R23
U21
K
EYSEN
SE4_N
_G
PIO
48
LB
1_N
_SD
R
A
M
1_D
Q
M
0
L2
LB2_N_A2_0
AE10
LCD_CS_N_GPIO38
AF14
GRFC4_AUX_SBCK_GPIO7
H10
D11
GRFC5_AUX_SBST_GPIO8
GRFC7_GPIO10
T23
B4
GRFC8_GPIO11
D5
GRFC9_GPIO12
GRFX6_GPIO9
T19
G
SM
_PA
_D
A
C
_R
EF
AD26
H
K
A
IN
0
V21
H
K
A
IN
1
AA23
W
21
H
K
A
IN
2
H
K
A
IN
3
V19
Y21
H
K
A
IN
4
H
K
A
IN
5
AB23
H
PH
_L
W
17
AA17
H
PH
_R
H
PH
_VR
EF
AA19
F14
G
PIO
64
F8
GPIO66
GPIO_67
U6
V4
GPIO_68
GPIO_69
R11 GPIO_70
E1
Y1
GPIO_71
GPIO_72
Y2 GPIO_73
V6
W4
GPIO_74
GP_PDM1_PA_RAN_GE0
H17
D17
GP_PDM2_PA_RAN_GE1
B8
GRFC0_GPIO3
A8
GRFC1_AUX_SBDT_GPIO4
D9
GRFC2_GPIO5
GRFC3_GPIO6
F10
EA
R
1O
N
AE18
EA
R
1O
P
AF18
G
PIO
17
K26
G21
G
PIO
19
A6
GPIO28
G
PIO
39
F7
G
PIO
40
D6D7
G
PIO
42
H9
GPIO43
G
PIO
44
D8 A4
G
PIO
45
F9
G
PIO
49
G
PIO
50
B7
G
PIO
51
A7
G
PIO
52
D10
L12
G
PIO
53
AF3
D2_1
AC8
D2_10
AE7
D2_11
D2_12
AA9
W10
D2_13
D2_14
AC9 D2_15
AA10
D2_2
AE4
AC6
D2_3
AE5
D2_4
AA7
D2_5
D2_6
AF5 D2_7
AC7 D2_8
AA8 D2_9
W9
F12
DAC_REF
CAMCLK_PO_GP_MN_GPIO13
J21
C
A
M
IF_D
A
TA
0_G
PIO
83
J25
J26
C
A
M
IF_D
A
TA
1_G
PIO
81
C
A
M
IF_D
A
TA
2_A
U
X_TR
ST_N
_G
PIO
54
D21
C
A
M
IF_D
A
TA
3_A
U
X_TC
K
_G
PIO
55
C25
C
A
M
IF_D
A
TA
4_A
U
X_TM
S_G
PIO
56
D22
J19
C
A
M
IF_D
A
TA
5_A
U
X_TD
I_G
PIO
57
C
A
M
IF_D
A
TA
6_A
U
X_TD
O
_G
PIO
58
L15
C
A
M
IF_D
A
TA
7_G
PIO
59
D20
F16
C
A
M
IF_D
A
TA
8_G
PIO
60
F20
C
A
M
IF_D
A
TA
9_G
PIO
61
C
A
M
IF_H
SYN
C
_G
PIO
15
E23
C
A
M
IF_PC
LK
_G
PIO
82
K23
C
A
M
IF_VSYN
C
_G
PIO
16
B3
C
C
O
M
P
AA20
D2_0
AC5
AF19
A
U
XIN
AE19
A
U
XIP
A
U
XO
U
T
AA18
AUX_PCM_CLK_GRFC14_GPIO80
K19
N21
AUX_PCM_DIN_GRFC13_GPIO14 G4
AUX_PCM_DOUT_GRFC12_GPIO103
AUX_PCM_SYNC_GRFC11_GPIO102
J8
AE21
B
O
O
T_M
O
D
E
B
O
O
T_M
O
D
E2
AE22
AD1
B
O
O
T_M
O
D
E3
G23
BT_CLK_GPIO25
R19
BT_DATA_GPIO20
E26
BT_SBCK_GPIO23
BT_SBDT_GPIO22
E25
F23
BT_SBST_GPIO24
BT_TX_RX_N_GPIO21
H21
AA13
A2_13
A2_14
AC13 A2_15
W13 A2_16
AE14
AC14
A2_17
A2_18
T13 A2_19
AA14
AF9
A2_2
AF13
A2_20_GPIO34
A2_3
W11
AC10
A2_4
AA11
A2_5
A2_6
AC11
T12
A2_7
W12
A2_8
A2_9
AA12
A1_21
T6
T8
A1_22
U4
A
1_23_SD
R
A
M
1_D
Q
M
2_G
PIO
78
V1
A
1_24_G
PIO
79
V8
A
1_25_SD
R
A
M
1_D
Q
M
3_G
PIO
75
M
8
A
1_3
M
4
A
1_4
A
1_5
N11
N8
A
1_6
A
1_7
N6
A
1_8
N2N1
A
1_9
AE9
A2_1
AC12
A2_10
A2_11
AE12 A2_12
AF12
L1
A
1_1
P1
A
1_10
A
1_11
P2
A
1_12
P6P8
A
1_13
A
1_14
P11
R4
A1_15
A1_16
R6
T1
A1_17
A1_18
T2
R8
A1_19
L4
A
1_2
T4
A1_20
10u
U200-1
MSM6280_A
VREG_MSMA_2.6V
C233
1u
C224
100K
R
208
10p
C200 VR
EG
_M
SM
P_2.7V
C227
1000p
TP200
1u
C234
VG
A
_C
A
M
_PW
R
_EN
MMP_INT_N
H
P_R
H
P_L
C
A
M
_C
O
VER
_D
ET
N
A
C
203
MMP_LCD_BYPASS_CS_N
RMT_INT
R
M
T_A
D
C
W
H
EEL_SW
_R
W
H
EEL_SW
_L
CAM_MCLK
LCD_RESET_N
VGA_CAM_RESET_N
CAM_SELECT_N
MICROSD_DETECT
U
A
R
T_TXD
U
A
R
T_R
XD
VGA_CAM_PWDN
BT_DATA
BT_SBDT
BT_SBCK
BT_SBST
BT_TX_RX_N
BT_CLK
TO
U
C
H
_I2C
_SC
L
TO
U
C
H
_PEN
IR
Q
_N
MMP_HPCM_FSYNC
LCD_LDO_EN
MMP_HPCM_DI
MMP_HPCM_CLK
M
M
P_R
ESET_IN
_N
MMP_PWR_EN
C
O
D
EC
_I2C
_SC
L
C
O
D
EC
_I2C
_SD
A W
M
_EN
MMP_HPCM_DO
RX_IM
RX_IP
RX_QM
RX_QP
DAC_REF
PA_ON
TCXO_EN
TRK_LO_ADJ
TX_AGC_ADJ
LIN_INVERTER
HOOK_SENSE_N
LCD_VSYNC_OUT
LCD_IF_MODE
EBI2_ADDR[13]
EBI2_ADDR[14]
EBI2_ADDR[12]
EBI2_ADDR[11]
EA
R
_SEN
SE_N
LCD_MAKER_ID
TO
U
C
H
_I2C
_SD
A
MSM_MICROSD_DATA[3]
MSM_MICROSD_DATA[2]
MSM_MICROSD_DATA[1]
CAM_MODE1_N
CAM_MODE3_N
C
A
M
_M
O
D
E2_N
M
M
C
_SELEC
T_N
HP_AMP_EN
U
SB
_XTA
L_O
U
T
R
ESO
U
T_N
R
ESET_IN
_N
M
IC
1P
M
IC
1N
M
IC
2P
A
M
U
X_O
U
T
VB
A
T_TEM
P
VB
A
T_SEN
SE
R
C
V+
R
C
V-
M
IC
B
IA
S
SPK
_L
SPK
_R
TX_QM
TX_IM
GSM_PA_EN
TX_QP
TX_IP
ANT_SEL2
GSM_PA_BAND
FM_INTX
TX_ON
PA_R1
ANT_SEL0
ANT_SEL1
LIN
_PW
M
_FR
EQ
G
SM
_PA
_PW
R
_C
TL_R
EF
G
SM
_PA
_R
A
M
P
SDRAM_ADDR[0:14]
SD
R
A
M
_A
D
D
R
[0]
SD
R
A
M
_A
D
D
R
[1]
SD
R
A
M
_A
D
D
R
[2]
SD
R
A
M
_A
D
D
R
[3]
SD
R
A
M
_A
D
D
R
[4]
SD
R
A
M
_A
D
D
R
[5]
SD
R
A
M
_A
D
D
R
[6]
SD
R
A
M
_A
D
D
R
[7]
SD
R
A
M
_A
D
D
R
[8]
SD
R
A
M
_A
D
D
R
[9]
SD
R
A
M
_A
D
D
R
[10]
SD
R
A
M
_A
D
D
R
[11]
SD
R
A
M
_A
D
D
R
[12]
SD
R
A
M
_A
D
D
R
[13]
SD
R
A
M
_A
D
D
R
[14]
SD
R
A
M
_C
LK
SD
R
A
M
_R
A
S_N
SD
R
A
M
_C
LK
_EN
SD
R
A
M
_C
A
S_N
SD
R
A
M
_D
Q
M
[0]
SD
R
A
M
_D
Q
M
[1]
SD
R
A
M
_D
Q
M
[2]
SD
R
A
M
_W
E_N
SD
R
A
M
_D
Q
M
[3]
SD
R
A
M
_C
S_N
U
SB
_XTA
L_IN
SLEEP_C
LK
B
U
FF_TC
XO
U
SIM
_D
A
TA
K
EY_C
O
L[1]
PM
_IN
T_N
PS_H
O
LD
U
SIM
_C
LK
U
SIM
_R
ST_N
K
EY_C
O
L[0]
SSB
D
T_R
TR
I2C
_SC
L
I2C
_SD
A
SSB
D
T_PM
U
SB
_SE0
U
SB
_D
A
T
K
EY_R
O
W
[2]
K
EY_R
O
W
[1]
K
EY_R
O
W
[0]
U
SB
_O
E_N
M
SM
_M
IC
R
O
SD
_C
M
D
M
SM
_M
IC
R
O
SD
_D
A
TA
[0]
M
SM
_M
IC
R
O
SD
_C
LK
M
M
P_C
A
M
_D
A
TA
[6]
M
M
P_C
A
M
_D
A
TA
[2]
M
M
P_C
A
M
_VSYN
C
M
M
P_C
A
M
_D
A
TA
[4]
M
M
P_C
A
M
_D
A
TA
[1]
LC
D
_B
L_C
TR
L
M
M
P_C
A
M
_D
A
TA
[7]
M
M
P_C
A
M
_D
A
TA
[5]
M
M
P_C
A
M
_D
A
TA
[0]
M
M
P_C
A
M
_PC
LK
M
M
P_C
A
M
_H
SYN
C
M
M
P_C
A
M
_D
A
TA
[3]
SDRAM_DATA[7]
SDRAM_DATA[6]
SDRAM_DATA[5]
SDRAM_DATA[4]
SDRAM_DATA[3]
SDRAM_DATA[2]
SDRAM_DATA[1]
SDRAM_DATA[0]
EBI2_DATA[0:15]
EBI2_DATA[15]
EBI2_DATA[14]
EBI2_DATA[13]
EBI2_DATA[12]
EBI2_DATA[11]
EBI2_DATA[10]
EBI2_DATA[9]
EBI2_DATA[8]
EBI2_DATA[7]
EBI2_DATA[6]
EBI2_DATA[5]
EBI2_DATA[4]
EBI2_DATA[3]
EBI2_DATA[2]
EBI2_DATA[1]
EBI2_DATA[0]
NAND_ALE
NAND_READY
NAND_CLE
EBI2_WE_N
EBI2_OE_N
NAND_CS_N
MMP_CS_N
USB_XTAL_OUT
USB_XTAL_IN
DAC_REF
FM_BUSEN
USB_SELECT_N
LIN_PWM_MAG
LIN_MOTOR_EN
SDRAM_DATA[0:31]
SDRAM_DATA[31]
SDRAM_DATA[30]
SDRAM_DATA[29]
SDRAM_DATA[28]
SDRAM_DATA[27]
SDRAM_DATA[26]
SDRAM_DATA[25]
SDRAM_DATA[24]
SDRAM_DATA[23]
SDRAM_DATA[22]
SDRAM_DATA[21]
SDRAM_DATA[20]
SDRAM_DATA[19]
SDRAM_DATA[18]
SDRAM_DATA[17]
SDRAM_DATA[16]
SDRAM_DATA[15]
SDRAM_DATA[14]
SDRAM_DATA[13]
SDRAM_DATA[12]
SDRAM_DATA[11]
SDRAM_DATA[10]
SDRAM_DATA[9]
SDRAM_DATA[8]
7. CIRCUIT DIAGRAM
- 177 -
A
E
H
5 11
G
D
6 4
B
GB042-40S-H10-E3000
B
C
10
2
ENBY0036001
LCD connector change : 35pin ZIF -> 40pin BTB
6 11
LCD INTERFACE
5
9
C
27Mhz XTAL
3 4
A
1%
12 5
12
8
D
1.0T, Socket
C
2 9
SWITCH FOR USB2.0
7
D
8
E
10
F
1 2
OTP Program Pin
392ohm 1%
3
A
7
150mA
2
10
B
G
B
1 6
D
F
H
5
F
H
12
9
6
G
12
C
3 4
A
11 7 9
LCD LDO
10
1 8
F
H
3
E
1 11
4
LCD BACKLIGHT CHARGE PUMP
8
E
G
3.4K
7
VR
EG
_M
SM
P_2.7V
R309
NA
R317 51
U303 R1114D191D-TR-F
6 CE
GND1 2
GND2 5 NC 4
1 VDD VOUT 3
+VPWR
0 R335
R326 0
22p
0
R
301
C
324
C301
0.1u
0 R318
10u
C308
TP300
100K
R
331
VREG_MSMP_2.7V
33 R312
0.1u
C303
C309
10u
M
M
P_VD
D
_C
O
R
E_1.0V
0.1u
C312
1u
C338
MMP_VDD_1.9V
G1
5
G2
10
INOUT_A1 1
2 INOUT_A2
INOUT_A3 3
4 INOUT_A4
9 INOUT_B1
INOUT_B2 8
7 INOUT_B3
INOUT_B4 6
MMP_VDD_CORE_1.0V
C302
LC
D
_VD
D
_2.8V
0.1u
LCD_VDD_2.8V
L300
2.2uH
1u
C
319
R325 0
LCD_VDD_2.8V
0 R324
C321
0.1u
8p
C300
10u
C340
INOUT_B3 7
6 INOUT_B4
1K
R
322
5
G1
10
G2
1 INOUT_A1
INOUT_A2 2
3 INOUT_A3
INOUT_A4 4
INOUT_B1 9
8 INOUT_B2
1u
C332
10p
TP303
C311
8p
C339
75
R
338
MMP_VDD_1.9V
VREG_USB_3.3V
330p
C334
1u
C330 C329
VR
EG
_M
M
C
_3.0V
1u
FB300
C336
0.01u
G1
5
G2
10
INOUT_A1 1
2
INOUT_A2
INOUT_A3 3
4 INOUT_A4
9 INOUT_B1
INOUT_B2
8
7 INOUT_B3
INOUT_B4 6
VR
EG
_U
SB_3.3V
6 BGND 2 GND
SEL
5
STBY
1
VIN 3 VOUT 4
HSD1+ 1
HSD1- 7
HSD2+ 2
6 HSD2-
10 SEL
VCC 9
_OE 8
BH28PB1WHFV U300
U304 FSUSB30UMX
3 D+
5 D-
4 GND
C306
P13
VIDM L9
N13 VIDN M11 VIDO
VIDP M9
P12 VMCLK
VPCLK P10
K12 VVS
XTA
LIN
H
14
J14
XTA
LO
U
T
M
M
P_VD
D
_U
SB_3.3V
0.1u
D
10
VD
D
_SER
IA
L
G
4
VEN
B
YPIN
E13
E11
VEN
B
YPO
U
T
VHREF M12
VIDA P8
VIDB N8
VIDC P9
M10 VIDD
VIDE N10
VIDF N9
N11 VIDG P11 VIDH
VIDI N12
VIDJ N7
L8 VIDK
VIDL
P3
UID P6
M7 URSET
UVBUS
J4
D
8
VD
D
C
O
R
E1
F4
VD
D
C
O
R
E2
J11
VD
D
C
O
R
E3
L7
VD
D
C
O
R
E4
L6
VD
D
Q
1
D
7
VD
D
Q
2
M
8
VD
D
_C
IS
H
4
VD
D
_G
EN
ER
A
L
VD
D
_H
O
ST
D
9
VD
D
_LC
D
D
6
VD
D
_M
M
C
G
2
VD
D
_N
A
N
D
K
10
VD
D
_PM
U
SPIDI
L2 SPIDO
SWP G3
TC
K
D
11
TD
I
E12
TD
O
D
13
TEST
F14
TM
S
E14
TR
STN
D
14
G14 TVDATA F13 TVREF
L1
UARTCTS
M1 UARTRTS
N3 UARTRX
M4 UARTTX
P4 UDN
UDP
J13
ND7 H13
M14
NRBN
L11 NREN K13 NWEN
G
13
R
ESETN
N14 SCL
G1 SCLK
SCMD H2
P14 SDA
F1 SDAT0 F2 SDAT1 E5 SDAT2
SDAT3 F3
N2 SPICLK
SPICS K3
J3
A1
B2 LD9
LHS E4
D5 LRDN
LVS E3
LWRN C4
M13 NALE
NCLE L12
L13 NCSN
ND0 L14
ND1 L10
K11
ND15
J12 ND2
ND3
H12
K14 ND4
ND5 G12
ND6
LD0
LD1 A5
B1 LD10
LD11 B3
C1 LD12 C2
LD13
LD14 C5
C6 LD15
LD16 D3
D1 LD17
LD2 B6
B4 LD3
A4 LD4
LD5 C3
LD6 A3
A2 LD7
LD8
HD6
HD7 B13
HD8 A14
A13 HD9
A7 HGINTN
H3 HPCMCLK
J1
HPCMDI
HPCMDO J2
HPCMFS H1
HRDN B7
B9 HWRN
LA0
D4
E2 LACT
E1 LCK
LCS0N A6
D2 LCS1N
B5
C8
HA14 C7
B8 HCS0N A8 HCS1N
D12 HD0 C10 HD1
HD10 B12
HD11 A12
B11 HD12
HD13 A11
C9 HD14
HD15 B10
C12 HD2
HD3 C13
HD4 C14
B14 HD5 C11
G
7
G
8
G
N
D
7
G
N
D
8
G
9
G
N
D
9
H
6
P2
GPIO0
GPIO1 M3
P7 GPIO2
GPIO3 N1
P1 GPIO4 M5
GPIO5
GPIO6 N6
M6 GPIO7
GPIO8 P5
GPIO9 N5
HA11 A10
A9 HA12
HA13
A
VD
D
_U
SB
T
A
VD
D
_VD
A
C
I
H
11
A
VD
D
_VD
A
C
P
G
11
F11
A
VSS_PLL
G
N
D
1
F6
H
7
G
N
D
10
H
8
G
N
D
11
H
9
G
N
D
12
J6
G
N
D
13
G
N
D
14
J7
G
N
D
15
J8J9
G
N
D
16
G
N
D
2
F7
G
N
D
3
F8F9
G
N
D
4
G
6
G
N
D
5
G
N
D
6
ZR3453
U302
M2 ABCLK
L3 ADI
ADO
K1
K2 AFS
A
G
N
D
_U
SB
C
L5
A
G
N
D
_U
SB
T
K
5
A
G
N
D
_VD
A
C
F12
N4 AMCLK
E10
A
VD
D
_PLL
A
VD
D
_U
SB
C
L4 K
4
10p
C315
22p
C331
C
316
51 R315
R
345
0.1u
100K
R
320
100K
TP301
0 R311
R313 NA
C
A
M
_VD
D
_IO
_2.7V
C327
R316 51
TP302
1u
1u
C337
M
M
P_VD
D
_1.9V
22p
C
322
NA R333
22p
C326
10p
C307
0.1u
C305
R310
10K
1 INOUT_A1
INOUT_A2 2
3 INOUT_A3
INOUT_A4 4
INOUT_B1 9
8 INOUT_B2
INOUT_B3 7
6 INOUT_B4
R
321
1K
5
G1
10
G2
0.1u
C313
NA R327
+VPWR
1u
C328
C
A
M
_VD
D
_IO
_2.7V
C
AM
_VD
D
_IO
_2.7V
R314 51
C320
VREG_MMC_3.0V
390
R
339
C333
NA
1u
0.1u
33
R329
C304
C2- 8
11
D1
D2 12
13 D3 14 D4 1 D5 2
D6
EN_SET 3
10 GND
9 IN
OUTCP 6
PGND
15
AAT3169IFO-T1 U301
C1+ 4
5 C1-
C2+ 7
R
319
10K
FB301 LCD_VDD_2.8V
0.1u
C310
C335
330p
R
300
0
29
C
A
M
_VD
D
_IO
_2.7V
ICVN0505X150FR
VA300
33
34
35
36
37
38
39
22
40
23
24
25
26
27
28
17
18
19
2
20
3
4
5
6
7
8
9
21
30
31
32
CN300
1
10
11
12
13
14
15
16
VA301
3.3K
R
340
C
317
CAM_VDD_IO_2.7V
1u
4
R
308
0
FA-238_27MHz_9PF
X300
27MHz
1 2
3
0.1u
C
318
0.1u
C
325
C314
22p
R
336
100K
+VPWR
C
323
M
M
P_R
ESET_IN
_N
MMP_HPCM_DI
MMP_HPCM_CLK
MMP_HPCM_FSYNC
MMP_HPCM_DO
MMP_A_MCLK
WLED_1
MMP_CAM_INT
MMP_STROBE_READY
MMP_PWR_EN
VREG_MSMP_2.7V
22p
USB_SELECT_N
MMP_CS_N
LCD_VSYNC_OUT
MMP_CAM_MCLK
MMP_LCD_CS_N
MMP_LCD_ADS
MMP_LCD_RD_N
MMP_LCD_WE_N
LCD_MAKER_ID
WLED_2
WLED_3
WLED_4
WLED_5
LCD_BL_CTRL
WLED_PWR +VPWR
LCD_LDO_EN
MMP_LCD_WE_N
MMP_LCD_VSYNC_OUT
WLED_PWR
WLED_2
WLED_4
WLED_5
MMP_INT_N
MMP_I2C_SDA
MMP_I2C_SCL
MMP_STROBE_CHARGE
MMP_CAM_HSYNC
MMP_ADI_ADCDAT
MMP_ADO_DACDAT
MMP_A_BCLK
MMP_A_LRCLK
MMP_LCD_VSYNC_IN
MMP_LCD_VSYNC_OUT
MMP_LCD_VSYNC_IN MMP_LCD_BYPASS_CS_N
MICROSD_DETECT
MSM_USB_D-
MMP_USB_D-
USB_D+
USB_D-
MSM_USB_D+
MMP_USB_D+
TV_OUT
MMP_CAM_RESET_N
MMP_LCD_DATA[15]
NAND_ALE
MMP_CAM_PCLK
LCD_IF_MODE
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[14]
LCD_DATA[15]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
LCD_DATA[12]
LCD_DATA[13]
WLED_1
WLED_3
MMP_LCD_ADS
MMP_LCD_CS_N
LCD_RESET_N
MMP_LCD_RD_N
MMP_LCD_DATA[9]
MMP_LCD_DATA[10]
MMP_LCD_DATA[11]
MMP_LCD_DATA[12]
MMP_LCD_DATA[13]
MMP_LCD_DATA[14]
MMP_LCD_DATA[15]
MMP_CAM_VSYNC
MMP_CAM_DATA[7]
MMP_CAM_DATA[6]
MMP_CAM_DATA[5]
MMP_CAM_DATA[4]
MMP_CAM_DATA[3]
MMP_CAM_DATA[2]
MMP_CAM_DATA[1]
MMP_CAM_DATA[0]
MMP_CAM_PWR_EN
MMP_MICROSD_CLK
MMP_MICROSD_DATA[3]
MMP_MICROSD_DATA[2]
MMP_MICROSD_DATA[1]
MMP_MICROSD_DATA[0]
MMP_XTAL_IN
MMP_XTAL_OUT
M
M
P_XTA
L_IN
M
M
P_XTA
L_O
U
T
MMP_USB_D+
MMP_USB_D-
VREG_5V
LCD_DATA[12]
LCD_DATA[13]
LCD_DATA[14]
LCD_DATA[15]
EBI2_ADDR[11]
EBI2_ADDR[13]
EBI2_ADDR[14]
MMP_MICROSD_CMD
MMP_LCD_DATA[0]
MMP_LCD_DATA[1]
MMP_LCD_DATA[2]
MMP_LCD_DATA[3]
MMP_LCD_DATA[4]
MMP_LCD_DATA[5]
MMP_LCD_DATA[6]
MMP_LCD_DATA[7]
MMP_LCD_DATA[8]
MMP_LCD_DATA[9]
MMP_LCD_DATA[10]
MMP_LCD_DATA[11]
MMP_LCD_DATA[12]
MMP_LCD_DATA[13]
MMP_LCD_DATA[14]
MMP_LCD_DATA[0]
MMP_LCD_DATA[1]
MMP_LCD_DATA[2]
MMP_LCD_DATA[3]
MMP_LCD_DATA[4]
MMP_LCD_DATA[5]
MMP_LCD_DATA[6]
MMP_LCD_DATA[7]
MMP_LCD_DATA[8]
EBI2_DATA[0:15]
EBI2_DATA[15]
EBI2_DATA[14]
EBI2_DATA[13]
EBI2_DATA[12]
EBI2_DATA[11]
EBI2_DATA[10]
EBI2_DATA[9]
EBI2_DATA[8]
EBI2_DATA[7]
EBI2_DATA[6]
EBI2_DATA[5]
EBI2_DATA[4]
EBI2_DATA[3]
EBI2_DATA[2]
EBI2_DATA[1]
EBI2_DATA[0]
EBI2_ADDR[12]
EBI2_OE_N
EBI2_WE_N
LCD_DATA[0]
LCD_DATA[1]
LCD_DATA[2]
LCD_DATA[3]
LCD_DATA[4]
LCD_DATA[5]
LCD_DATA[6]
LCD_DATA[7]
LCD_DATA[8]
LCD_DATA[9]
LCD_DATA[10]
LCD_DATA[11]
7. CIRCUIT DIAGRAM
- 178 -
12
4
8
B
C
3
MICRO SD SELECT MSM AND MMP
1
4
A
7
USIM
B
8
7
10
10
C
4
3
MEMORY (2Gbit 70n NAND FLASH + 1Gbit SDRAM)
11
5
10 3
G
D
C
12
5
D
2
C
3 2
4 1
6
E
G
A
H
F
1
12 9
A
E
6
H H
E
8
A
F
7 11 10
9 5 6
D
9
D
5 11
G G
B
2
12
8
9
B
6
7
H
1
F
11
2
E
F
0.1u
C
404
VREG_USIM_3.0V
+VPWR
+VPWR
8
5
NC1
NC2 7
NO1 2
NO2 10 1 VCC
U400
SLAS4717EPMTR2G
3 COM1
9 COM2
6
GND
IN1 4
IN2
R400
15K
VREG_USIM_3.0V
0.01u
C410
0.01u
C413
C
403
VREG_MSME_1.8V
0.1u
3 4
5
6
PLR0504F
D400
1
2
1u
D6
_WEN K6
L6 _WP
C402
VSS11
VSS12 U13
VSS2 F7
VSS3 G2
VSS4 G13
VSS5 L13
VSS6 P2
P13 VSS7
VSS8 R8
U2 VSS9
_CAS E6
M9 _CE
_CS1 E5
D7 _CS2
_RAS D5
_RE M10
_WED
N
C
96
N
C
97
T2T3
N
C
98
T7
N
C
99
RY__BY M2
VCCD1 C7
D2 VCCD2 D13 VCCD3
VCCD4 V3
V8 VCCD5 V12 VCCD6
VCCN2 K12
V4 VCCQD1
VCCQD2 V9
VSS1 C6
U6 VSS10 U10
M6
N2 NC82
N
3
N
C
83
N
4
N
C
84
N
C
85
N
5
N
C
86
N
6
N
9
N
C
87
N
C
88
N
10
N
C
89
N
11
NC9 B1
N
12
N
C
90
N
C
91
N
13
P7
N
C
92
N
C
93
P8R
2
N
C
94
N
C
95
R
7
R
9
K3
K4
NC68
NC69 K5 NC7
A13
K10 NC70
NC71 K11
K13 NC72
NC73
K14
NC74 L1
L2 NC75 L3 NC76
NC77 L4
L5
NC78
NC79 L14
NC8 A14
M5 NC80
NC81
N
C
52
N
C
53
H
4
H
5
N
C
54
N
C
55
H
6J2
N
C
56
N
C
57
J3
N
C
58
J4J5
N
C
59
A12 NC6
J6
N
C
60
N
C
61
J10
J11
N
C
62
NC63
J12
J13 NC64 K1 NC65
NC66 K2
NC67
F9
F10
N
C
39
NC4 A4
N
C
40
F11
F12
N
C
41
N
C
42
F13
N
C
43
G
3
N
C
44
G
4
N
C
45
G
5
G
6
N
C
46
N
C
47
G
7
G
8
N
C
48
N
C
49
G
9
NC5 A11
G
10
N
C
50
N
C
51
H
2
H
3
N
C
23
N
C
24
E1
N
C
25
E7E8
N
C
26
N
C
27
E9
E10
N
C
28
N
C
29
E11
A3 NC3
E12
N
C
30
N
C
31
E13F2
N
C
32
N
C
33
F3F4
N
C
34
N
C
35
F5F6
N
C
36
F8
N
C
37
N
C
38
B4
Y11
N
C
120
N
C
121
Y12
Y13
N
C
122
N
C
123
Y14
NC13 B11
NC14 B12
B13 NC15
NC16 B14
C1
NC17
NC18 C2
NC19 C5
NC2
A2
NC20 C13
NC21 C14
N
C
22
D
1
D
14
N
C
105
V13
N
C
106
V14
N
C
107
N
C
108
W
1
N
C
109
W
2
NC11 B3
W
3
N
C
110
N
C
111
W
4
W
11
N
C
112
N
C
113
W
12
W
13
N
C
114
N
C
115
W
14
Y1
N
C
116
N
C
117
Y2
N
C
118
Y3
N
C
119
Y4
NC12
IO16
IO2 M13
IO3 L10
IO4 L12
IO5 J9
IO6 H12
IO7 H10
G12 IO8 M12 IO9
NC1 A1
NC10 B2
N
C
100
T13
N
C
101
U
1
U
3
N
C
102
N
C
103
U
14
N
C
104
V1V2
DQ5
DQ6 V6
DQ7
U7
T9 DQ8
DQ9 T10
DQM0 U8
T8 DQM1
DQM2 V7
DQM3 U9
IO1 M11
L9 IO10 L11 IO11 K9 IO12
IO13 H13
H11 IO14
H9 IO15 G11
R4
T5
DQ2
DQ20 P5
R5 DQ21
P6 DQ22
DQ23 R6
DQ24 P9
DQ25 P10
R10 DQ26
P11 DQ27 R11 DQ28
DQ29 P12
DQ3 V5
R12 DQ30
DQ31 R13
U5 DQ4 T6
C4
BA1 D4
CKE D8
CLE M4
CLK C8
U4 DQ0 T4 DQ1
V10 DQ10
DQ11 T11
U11
DQ12
DQ13 V11
T12 DQ14
DQ15 U12
P3 DQ16
R3 DQ17 P4 DQ18
DQ19
A0 C3
A1 D3
A10 E4
A11 D9
C9
A12
A2
E3
A3 E2
A4 D12
A5 C12
A6 D11
A7
C11
A8 D10
A9 C10
ALE M3
BA0
U402
TYA000BC00HOGG
100K
R401
R404
0
C401
33p
10K
VREG_MSMP_2.7V
R403
C
405
0.1u
C400
33p
C
407
0.1u
0.1u
C411
C
409
0.1u
J400
C1 1
C2 2
3 C3
C5 4
5 C6 6 C7 7
GND1
GND2 8 9 GND3
GND4
10
R402
COM4
6 GND
IN1_IN2 2
IN3_IN4 10
NC1 1
5 NC2
9 NC3
NC4 13
NO1 15
NO2 3
7 NO3
11 NO4
PGND 17
14 V+
100K
MAX4701ETE+T U401
COM1 16
4 COM2
COM3 8
12
C412
0.01u
C
406VREG_MSMP_2.7V
0.1u
C
408
MSM_MICROSD_DATA[0]
MMP_MICROSD_DATA[0]
MSM_MICROSD_DATA[1]
MMP_MICROSD_DATA[1]
MSM_MICROSD_DATA[2]
MMP_MICROSD_DATA[2] MICROSD_DATA[2]
USIM_P_RST_N
USIM_P_DATA USIM_P_CLK
MSM_MICROSD_CLK
MSM_MICROSD_CMD
NAND_READY
RESOUT_N
MMP_MICROSD_DATA[3]
MSM_MICROSD_DATA[3]
USIM_P_DATA
USIM_P_RST_N
USIM_P_CLK
0.1u
SDRAM_CLK
SDRAM_WE_N
SDRAM_ADDR[14]
SDRAM_ADDR[13]
SDRAM_CLK_EN
NAND_CLE
NAND_ALE
NAND_CS_N
EBI2_OE_N
EBI2_DATA[8]
EBI2_DATA[9]
EBI2_DATA[10]
EBI2_DATA[11]
EBI2_DATA[12]
EBI2_DATA[13]
EBI2_DATA[14]
EBI2_DATA[15] MMC_SELECT_N
MMP_MICROSD_CMD
MICROSD_CLK
MICROSD_CMD
MMP_MICROSD_CLK
MMC_SELECT_N
MICROSD_DATA[3]
MICROSD_DATA[1]
MICROSD_DATA[0]
SDRAM_DATA[26]
SDRAM_DATA[27]
SDRAM_DATA[29]
SDRAM_DATA[30]
SDRAM_DATA[31]
SDRAM_DATA[16]
SDRAM_DATA[17]
SDRAM_DATA[22]
SDRAM_DATA[18]
SDRAM_DATA[19]
SDRAM_DATA[23]
SDRAM_DATA[20]
SDRAM_DATA[21]
SDRAM_DATA[0:31]
SDRAM_ADDR[1]
SDRAM_ADDR[2]
SDRAM_ADDR[4]
SDRAM_ADDR[3]
SDRAM_ADDR[9]
SDRAM_ADDR[5]
SDRAM_ADDR[8]
SDRAM_ADDR[7]
SDRAM_ADDR[6]
SDRAM_ADDR[10]
SDRAM_ADDR[11]
SDRAM_ADDR[12]
SDRAM_ADDR[0]
SDRAM_ADDR[0:12]
SDRAM_CS_N
EBI2_WE_N
SDRAM_CAS_N
SDRAM_RAS_N
SDRAM_DQM[0]
SDRAM_DQM[1]
SDRAM_DQM[2]
SDRAM_DQM[3]
EBI2_DATA[0:15] EBI2_DATA[0]
EBI2_DATA[1]
EBI2_DATA[2]
EBI2_DATA[3]
EBI2_DATA[4]
EBI2_DATA[5]
EBI2_DATA[6]
EBI2_DATA[7]
SDRAM_DATA[1]
SDRAM_DATA[0]
SDRAM_DATA[6]
SDRAM_DATA[2]
SDRAM_DATA[8]
SDRAM_DATA[7]
SDRAM_DATA[3]
SDRAM_DATA[12]
SDRAM_DATA[10]
SDRAM_DATA[9]
SDRAM_DATA[5]
SDRAM_DATA[4]
SDRAM_DATA[13]
SDRAM_DATA[11]
SDRAM_DATA[15]
SDRAM_DATA[14]
SDRAM_DATA[24]
SDRAM_DATA[25]
SDRAM_DATA[28]
7. CIRCUIT DIAGRAM
- 179 -
E
2
VDD_MSM : 0.1uF
3 5
B
1
USB/REMOCON_SEL
PMIC
VDD_ANA : 0.1uF
--->> USB_VBUS , FLASH_DRV_N , KPD_DRV_N , KEY_ON_SW_N , MOT_PWR-
1
(1%)
9
H
F
B
F
A
VDD_MAIN : 0.1uF
10
F
4
H
8
C
OVP
D
10
10
7
VSW_5V : 4.7uF
6
1608
HEADPHONE AMP
VDD_PA : 4.7uF
2
Power Line --> Route carefully!!!!!
MIC
9
7
A
VDD_RUIM : 0.1uF
MMI 18Pin CONNECTOR
10
1608
Rev. 1.0
12
9
1608
VDD_WLAN : 0.1uF
A
8
2 7
A
8
3 4
G
CAM/HP MIC SEL
E
G
D
4
1608
9
4
8
H
5 1
Rev. 1.1
7
11
2012
11 3
CHARGING
3
G
H
6
AUDIO DAC/ADC, AMP etc. (WM8983)
PQ
PQ
11
E
1608
12 12
G
12
E
1608
VDD_MSMC : 4.7uF
F
C
VDD_MSME : 4.7uF
PMIC VPWR BYPASS
2 1
11
1608
Draw the Artwork_line thickly !!!!!
1608
VCC
U505 NUS3065MUTAG
CNTRL 3
4 DRAIN
DRAIN_THERMAL 9
GATE 6
2 GND
IN 1
7 OUT
5 SRC
8
2.2u
C
511
R524
68
EVLC
14S02050
C
504
+VPWR
VA
505
9 SVDD2
11 SVSS
16
_SH
D
N
4.7u
U504
MAX9722BETE
C1N 4
2 C1P
IN
L+
15
IN
L_
14
7
IN
R
+
IN
R
_
8
OUTL 12
OUTR 10 3 PGND
PVDD 1
5
PVSS
P_G
17
SG
N
D
6
13
SVD
D
1
R
504
R520 0
VREG_MSMP_2.7V
0.1
FB501
4.7u
C565
R505
VREG_MSMC_1.2V
470K
C555
10u
FB500
C577
1u
R
B
521S-30
D
501
FLSH_DRV_N 8
80
REF_OUT(M
PP8)
VREG_SYNT
81
AM
UX_OUT
82
VDD_M
AIN
83
VREG_TCXO
84
GND_SLUG
85
PON_RESET_N 9
AM
UX_IN2(M
PP2)
72
VREG_RFTX
73 74
SPKR_BYP
75
SPKR_OUT_P
SPKR_IN_P
76
VDD_SPKR
77
SPKR_IN_M
78
SPKR_OUT_M
7965
CBL1PW
R_N(M
PP4)
66
VREG_RFRX2
67
CBL0PW
R_N(M
PP3)
68 69
VREG_RFRX1
BAT_FET_N 7
AM
UX_IN1(M
PP1)
70
VDD_RF
71
58 MSM_INT_N 59
VBAT 6
VCOIN 60
61 REF_ISET
REF_GND 62 REF_BYP 63 VREG_W
LAN
64
VDD_W
LAN
50 SBST 51 VDD_MSM 52 TCXO_OUT 53
54 VDD_ANA
TCXO_EN 55
VREG_MSMA 56 PS_HOLD 57 TCXO_IN
43 XTAL_IN 44 SLEEP_CLK 45
46 XTAL_OUT
SBDT 47
VBACKUP 48 SBCK 49
ISNS_M 5
VREG_MSMP
36
VSW
_M
SM
E
37
RUIM
_CLK(M
PP10)
3839
VREG_M
M
C
CHG_CTL_N 4
RUIM
_M
_RST(M
PP5)
40
VDD_RUIM
41
VREG_RUIM
42
RUIM_RST(MPP6)
29
ISNS_P 3
RUIM
_M
_IO(M
PP11)
3031
VSW
_M
SM
C
VREG_M
SM
C
32
VDD_M
SM
C
33
RUIM
_M
_CLK(M
PP9)
34
VDD_M
SM
E
35
VREG_M
SM
E
21
LCD_DRV_N
22
KPD_DRV_N
2324
KPDPW
R_N
VIB_DRV_N
25
RUIM
_IO(M
PP12)
26
VSW
_PA
27
VREG_PA
28
VDD_PA
14
USB_CTL_N 15
USB_VBUS 16
USB_DAT 17
USB_D_P 18
19 USB_SE0
VCHG 2
USB_D_M 20
GP1_DRV_N(MPP7)
ADC_BYP 1
VREG_USB 10
11 USB_ID
VREG_5V 12
USB_OE_N 13
VSW_5V
U506 NC7SB3157L6X
A 4 B0 3
1 B1 2 GND
6 S 5 VCC
U501
PM6650-2M
SD
12T1G
D
502
VBATT
10u
C563
C550
NA
+VPWR
47p
121K
C580
R506
1u C529
4.7uH L503
0.1u
C514
C509
4.7u
68
+VPWR
C557
VREG_MSMA_2.6V
R525
1000p
C535
EVLC
14S02050
VA
504
1u
600 FB503
C532 1u
C
502VG
A
_VD
D
_1.8V
6
RIN 5
4 RIP
ROUT1 29
ROUT2 23
16 SCLK
SDIN 17
27 VMID
+VPWR
0.1u
10
DBVDD 14 DCVDD 13 12 DGND
L2_GPIO2 3
LIN 2
1 LIP
LOUT1 30
25 LOUT2
7 LRC
11 MCLK
MICBIAS 32
18
MODE
OUT3 22
21 OUT4
33 PGND
R2_GPIO3
ADCDAT 9
28 AGND1
24 AGND2
AUXL 19
AUXR 20
31 AVDD1
AVDD2 26
8 BCLK
15 CSB_GPIO1
DACDAT
4.7u
C520
WM8983 U502
C568 22n
C559
0.1u
FB502 600
C561
0.1u
C
540
4.7u
33u
C500
C533
4.7n
R511
18K
0.22u
R
507
C
578
3 COLLECTOR
DRAIN 5
1 EMITTER1
EMITTER2 2
6 GATE
9 P_COLLECTOR P_DRAIN 10
SOURCE 4
10K
32.768K
H
z
1
2
NUS3116MTR2G U500
BASE1 8
BASE2 7
R509
X500
VR
EG
_TC
XO
_2.85V
51
C
587
47p
2.2u
C
515
R533
0
R
522
15K
4.7u
C
508
VA
508
PR
SB
6.8CVA
501
U
LC
E0505C
015FR
C579
10u
C525
10u
C
503
0.1u
10p
C588
VREG_MSMP_2.7V
C572
VREG_5V
1u
C571
1u
4.7u
C538
C
506
4.7u
D+ 3
D- 5
GND 4
1 HSD1+
7 HSD1-
2 HSD2+
HSD2- 6
SEL 10
9 VCC
8 _OE
15K
R
529
FSUSB30UMX U507
VBATT
0.1u
C584
C
534
1u
VA
503
EVLC
14S02050
0.01u
C581
C528
MIDI_3.3V
C
507
4.7u
VR
EG
_B
T_2.85V
0.1u
10u
C513
1u
C570
VREG_USB_3.3V
4.7u
C558
R515
51K
1u
C512
NA
C569
C
510
1u
C537
4.7u
VR
EG
_SYN
TH
_2.6V
100K
R
519
smd_2520h1_6_r
4.7uH L500
4.7n
C542
NA
C531
4.7u
C560
C564
47p
C
505
0.1u
1K
R516
C
501
0.1u
VA
500
U
LC
E0505C
015FR
0.1u
C556
47K
R
514
17
18
19
2
20
21
22
3
4
5
6
7
8
9
CN500
1
10
11
12
13
14
15
16
R510
1K
+5V_PWR
1u C541
C549 1u
1u C548 10K
R518
C536 1u
TP500
4.7uH L502
2.2u
C553
C518
4.7u
R
528
100K
+VPWR
PR
SB
6.8C
C
574
VR
EG
_W
M
_2.7V
VA
502
EVLC
14S02050
C
590
2.2u
P
C
539
1u
SPM0204HE5-PB-3
MIC500
2 G1 3
G2
1 O
4
0
R508
D500
RB521S-30
C546
22p
C547
C575
12n
0.1u
33p
C524
+VPWR
0.1u
C
583
10p
C522
ind_2x1_6h1_r
0.1u
C
527
4.7uH
L501
C544
USB_VBUS
C576
+VPWR
NA
10p
VA
506
EVLC
14S02050
VBATT
0.1u
C519
PR
SB
6.8C
C
573
VBATT
+5V_PWR
C552 VREG_MSME_1.8V
USB_VBUS
VREG_USIM_3.0V
2.2u
C551
NA
C521
0.1u
C567 22n
+VPWR
VA
507
PR
SB
6.8C
U503
R1180D331B
CE_OR_NC 6
2 GND1 5 GND2
NC 4
VDD 1
VOUT 3
47p
C
586
NA
22p
C545
FB504
C543
0 R513
51K R512
2.2K
R
530
C
589
VREG_MSMP_2.7V
12n
33p1u
C530
C
585
18K
R517
2.2uH
L504
MMP_VDD_USB_3.3V
R
521
N
A
1u C523
1u
C566
VREG_MMC_3.0V
0.22u
C
562
VREG_5V
22u
C554
1u
C
526
C516
4.7u
C517
0.1u
MIDI_EAR_R
MIC_PWR
MID_MICP
WM_EN
MIC_PWR
TV_OUT
ICHARGE
EAR_MIC_P
RMT_PWR_ON_N
MMP_A_MCLK
EAR_SENSE_N CAM_MIC+
EAR_MIC_P
CODEC_I2C_SCL
CODEC_I2C_SDA
MICBIAS
HP_R
HP_L
MIDI_EAR_L
HP_EAR_L
MIC2P
HP_EAR_R
MID_MICP
SPK_L
SPK_R
FM_AUDIO_L
FM_AUDIO_R
MMP_A_BCLK
MMP_ADO_DACDAT
MMP_A_LRCLK
MMP_ADI_ADCDAT
SPK_OUT-
SPK_OUT+
VREG_5V
VREG_WM_2.7V
VREG_MSME_1.8V
MIDI_3.3V
RMT_INT-USB_D+
RMT_ADC-USB_D-
VBATT
+5V_PWR RMT_INT
RMT_ADC
EAR_SENSE_N
USB_D+
USB_D-
RMT_INT-USB_D+
RMT_ADC-USB_D-
FM_ANT
UART_TXD
MIDI_3.3V
HP_AMP_EN
HP_EAR_L
HP_EAR_R
GSM_PA_PWR_CTL_REF
AMUX_OUT
RESET_IN_N
BUFF_TCXO
PS_HOLD
FLSH_DRV_N
ICHARGEOUT
CHG_CNT_N
USB_CNT_N
BATT_FET_N
MIC1P
MIC1N
VREG_RF_SMPS
USB_VBUS
UART_RXD
MIDI_EAR_L
MIDI_EAR_R
EAR_SENSE_N
USB_OE_N
USB_CNT_N
USB_DAT
MSM_USB_D+
USB_SE0
MSM_USB_D-
KYPD_LED_EN
PM_ON_SW_N
USIM_P_DATA
ICHARGE
USIM_DATA
USIM_CLK
USIM_P_CLK
CHG_CNT_N
USIM_RST_N
USIM_P_RST_N
SLEEP_CLK
SSBDT_PM
ICHARGEOUT
TCXO_EN
JTAG_PS_HOLD
TCXO_PM
PM_INT_N
V_BACK_UP
RMT_PWR_ON_N
BATT_FET_N
7. CIRCUIT DIAGRAM
- 180 -
PWR
URXD
UTXD
3G 2.5G
GND
RX
TX
VCHAR
ON_SW
VBAT
G
12
8
3
F
C
MAIN - SUB B to B Conn.
F
C
D
9 6
5
2
G
12 9 3 1
4
5 4 10
E
G
LINEAR MOTOR DRIVER ( AUDIO AMP )
C
H
7
150mA
H
AXT410164
10
ESSY0004701
4
8
FOR NEST JIG
5
D
MODE1
PCB ARRAY TP
2
(BATTERY PAD 1.5 X 3.4)
H
5
8
D
5MP CAM LDO
6
7 3
D
Strobe(Xenon Lamp) Flash Interface
1
4
E
2
12
C
E
6
F
A
GB042-30S-H10-E3000
H
2
1
SWITCH FOR 5M VT CALL
MODE2
VGA CAM LDO
150mA
G
AXK740327G
8
A
10
F
9 1
11
11 11
7
MODE SWITCH
3
9
10
B
5M CAMERA INTERFACE
6 12
MODE3
11
E
7
1608
B
OUT608
100K R611
R615 100K
0.1u
C622
39
4
40
5
6
7
8
9
25
26
27
28
29
3
30
31
32
33
34
35
36
37
38
1
10
11
12
13
14
15
16
17
18
19
2
20 21
22
23
24
CAM_VDD_SA_2.7V
CN603
G1
G2
OJ602
0
R626
27
28
29
30
17
18
19
20
21
22
23
24
11
12
13
14
15
2
3
4
5
6
7
8
9
16
25
26
VREG_MSMP_2.7V
CN600
1
10
0.1u
C627
51K
R
612
5 VCC
OJ603
U604 NC7SB3157L6X
A 4 B0 3
1 B1 2 GND
6 S
C606
0.1u
5
G1
10
G2
1 INOUT_A1
INOUT_A2 2
3 INOUT_A3
INOUT_A4
4
9 INOUT_B1 8 INOUT_B2
INOUT_B3 7
6
INOUT_B4
U602 R1114D271D
CE_OR_NC
6
2 GND1 5 GND2
NC 4
VDD
1
VOUT 3
1u
C603
CAM_VDD_SA_2.7V
VR
EG
_M
M
C
_3.0V
CAM_VDD_IO_2.7V
10u
C625
1u
G4
P1 P2 P3 P4
C
608
SSP-132MHT
SW600
G1
G2
G3
R
613
51K
TP603
10p
C611
6
CE_OR_NC
GND1 2 GND2 5
4 NC
1
VDD
3 VOUT
VR
EG
_M
SM
P_2.7V
C605
CAM_VDD_AF_2.7V
R1114D271D U601
VBATT
0.1u
C615
1u
C602
1u
R602 10
R
614
51K
OUT611
1u
C
619
EVLC
14S02050
VA
604
10p
C610
1u
C618
C600
10u
100K
VR
EG
_B
T_2.85V
TP602
CAM_VDD_IO_2.7V
VREG_5V
R610
GND
3
2
IN_A
1
IN_B
4
OUT_Y
VCC
5
C623
0.1u
VREG_MMC_3.0V
U603 TC7SZ86FU
C613
10p
0.1u
R608 10
C
609
C612
10p
R601 10
0.1u
G1
5
G2
10
INOUT_A1 1
2 INOUT_A2
INOUT_A3 3
INOUT_A4 4
9 INOUT_B1
INOUT_B2 8
7 INOUT_B3
INOUT_B4 6
C626
IN_B
4
OUT_Y
VCC
5
VREG_MMC_3.0V
U605 TC7SZ86FU
GND
3
2
IN_A
1
1
680K
R623
TPA6205A1DRBR
2
BYPASS
7 GND
IN+ 3
4 IN-
9 PGND
VDD 6
5 VO+
8
VO-
_SHUTDOWN
GND 2 SEL 5 1 STBY
VIN 3 4 VOUT
U606
U600 BH28PB1WHFV
BGND 6
2200p C620
C624 2200p
EVLC
18S02015
VA
602
TP601
100K R619
470K
R621
+VPWR
VA
601
IC
VL0518100Y500FR
1u
4 A 3 B0
B1 1
GND 2 S 6
VCC 5
C616
C621
NC7SB3157L6X U607
0.1u
C614
VGA_VDD_2.7V
TP604
0.1u
C601
DSR
10
1
GND
NC1
4
7
NC2
NC3
8
9
NC4
5
ON_SW
11
RTS
RX
2
3
TX
VBAT
6
0.1u
8
9
G1 G2
G3 G4
+VPW
R
CN602
CTS
12
1 10
2
3
4
5 6
7
VA
605
EVLC
14S02050
CN601
+VPWR
R622
80.6K
VREG_MSMP_2.7V
OJ600
R607
33
1u
C617
C604
TP600
1u
VA
603
EVLC
14S02050
IC
VL0518100Y500FR
VA
600
OJ604
+VPWR
IN
STPA
R
0.1u
D
600
PSD
05-LF
R604 10
+VPWR
C607
CAM_VDD_SD_1.8V
10 R603
+VPWR
OUT614
CAM_COVER_DET
FLSH_DRV_N
CAM_VDD_CORE_1.2V
OJ601
5M_CAM_DATA[1]
5M_CAM_DATA[2]
5M_CAM_DATA[3]
MMP_CAM_DATA[4]
MMP_CAM_DATA[5]
MMP_CAM_DATA[6]
MMP_CAM_DATA[7]
5M_CAM_DATA[4]
5M_CAM_DATA[5]
5M_CAM_DATA[6]
5M_CAM_DATA[7]
VBATT
UART_TXD
UART_RXD
PM_ON_SW_N
MSM_USB_D+
MSM_USB_D-
USB_VBUS
MMP_CAM_PWR_EN
SPK_OUT+
SPK_OUT-
VBATT
HOOK_SENSE_N
EAR_MIC_P
VGA_CAM_PWR_EN
+5V_PWR
VGA_CAM_MCLK
STROBE_TRIGGER
PM_ON_SW_N
UART_RXD
UART_TXD
MMP_CAM_PCLK
MMP_CAM_HSYNC
MMP_CAM_VSYNC
MMP_I2C_SDA
MMP_I2C_SCL
5M_CAM_MCLK
VREG_MSMP_2.7V
CAM_MODE3_N
CAM_MODE2_N
CAM_MODE1_N
MMP_CAM_DATA[0]
MMP_CAM_DATA[1]
MMP_CAM_DATA[2]
MMP_CAM_DATA[3]
5M_CAM_DATA[0]
MICROSD_DATA[1]
MICROSD_DETECT
MICROSD_CLK
MICROSD_DATA[0]
MICROSD_CMD
CAM_VDD_AF_2.7V
CAM_MIC+
WHEEL_SW_L
WHEEL_SW_R
CAM_VDD_SD_1.8V
V_BACK_UP
MMP_CAM_MCLK 5M_CAM_MCLK STROBE_TRIGGER
VBAT_SENSE
VBAT_TEMP
CAM_SELECT_N 5M_CAM_MCLK
CAM_MCLK
LIN_PWM_MAG
LIN_INVERTER
LIN_PWM_FREQ
LIN_MOTOR_EN
MOTOR-
MOTOR+
TCXO_BT
BT_TX_RX_N
BT_SBST
BT_SBCK
BT_SBDT
BT_CLK
BT_DATA
MMP_STROBE_CHARGE
MMP_STROBE_READY
MMP_CAM_PWR_EN MMP_CAM_PWR_EN
+VPWR
MICROSD_DATA[3]
MICROSD_DATA[2]
7. CIRCUIT DIAGRAM
- 181 -
7
C
1
3
B
1 4
(GREEN)
6
10 5 8
D
Touch Driver IC change : TSC2003 -> TSC2007
4
9
8
B
1
E
G
E
G
H
5 7
G
1
5
D
7 11
SEND
6
CLR
H
6
E
10 3 9
2
3
C
ON_SW KEY
11
F
8
4
E
Rev. 1.1
(WHITE) (RED)
PQ
A
10
F
10
H
F
C
H
7 3 11
END
2
12
D
9 12
SIDE KEY
F
C
6
A
9 8
KEY PCB BACKLIGHT LEDs
G
D
2 4 5
12
2
TOUCH SCREEN DRIVER IC
12
11
KEY
LEG
G
-S14G
LD
705
47
R
716
10p
VGA_VDD_1.8V
EVLC
14S02050
VA
710
1
2
3
4
5
C712
CN700
1u
C700
56K
R
731
R707
L701
470
+VPWR
4.7uH
10p
+VPWR
VA
707
EVLC
14S02050
C715
E
V
LC
14S
02050
4.7u
V
A
706
EVLC
14S02050
C
707
VA
703
47
R
715
R
729
resistor
NA
A0 B2
C2 A1
AUX A1
D2 GND
B1 PENIRQ- SCL D1
SDA C1
A2 VDD_REF
X+ A3 X- C3
Y+ B3 Y- D3
E
V
LC
14S
02050
U700 TSC2007IYZGR
V
A
702
C
706
2.2u
R717
10
IC
VL0518100Y500FR
VA
714
VA
713
EVLC
18S020150.1u
C709
R
704
2.7K
MMP_VDD_CORE_1.0V
2.2u
C
708
V
A
705
E
V
LC
14S
02050
1 INOUT_A1
INOUT_A2 2
3 INOUT_A3
INOUT_A4 4
INOUT_B1 9
8 INOUT_B2
INOUT_B3 7
6 INOUT_B4
END
LD
703
ICVE10184E070R100FR
FL700 5
G1
10
G2
SSC
-FR
104-II1
VREG_MSMP_2.7V
R
714
200
51K
VGA_VDD_2.7V
R
701
200
EVLC
14S02050
VA
712
INOUT_B1 9
8 INOUT_B2
INOUT_B3 7
6 INOUT_B4
R
712
FL701
ICVE10184E070R100FR
G1
5
G2
10
1 INOUT_A1
INOUT_A2 2
3 INOUT_A3
INOUT_A4 4
0.1u
C711
2.7K
R
703
R726 39K
10p
C714
0.1u
1 EN1
EN2 4
FB1 2
5 FB2
3
G
N
D
1
G
N
D
2
6
11 LX1
LX2 8
7
PG
N
D
1
PG
N
D
2
10
VIN1 12
VIN2 9
C710
U701 AAT2510IWP-AA-T1
B
G
N
D
13
EVLC
18S02015
VA
715
E
V
LC
14S
02050
V
A
701
56K R728
LD
704
SSC
-TW
H
104-H
L
47
700
R
711
R709 470
470 R710
R708 470
SSC
-FR
104-II1
LD
701
R
700
0
R719 10
R
706
51K
L700 4.7uH
R
705
51K
LD
700
SSC
-TW
H
104-H
L
47
R
713
C703
4.7u
LD
702
R
702
N
A
R720 10
LEG
G
-S14G
10 R725
E
V
LC
14S
02050
V
A
704
100p C702
R724 10
VA
711
EVLC
14S02050
C704
701
100p
VA
709
EVLC
14S02050
10p
EVL14K02200
C713
V
A
700
E
V
L14K
02200
VA708
R718 10
R
730
56K
C
705
4.7u
C701
CAM_VDD_CORE_1.2V
23
24
LCD_VDD_2.8V
0.1u
7
8
9
16
25
26
27
28
29
30
17
18
19
20
21
22
CN701
1
10
11
12
13
14
15
2
3
4
5
6
X-
KEY_ROW[0]
KEY_ROW[1]
KEY_COL[1]
KEY_COL[0]
KYPD_LED_EN
VGA_CAM_DATA[2]
VGA_CAM_DATA[3]
I2C_SDA
I2C_SCL
MMP_CAM_VSYNC
MMP_CAM_HSYNC
VGA_CAM_RESET_N
RCV+
RCV-
MOTOR+
MOTOR- x+
x-
Y+
Y-
MMP_CAM_PWR_EN
MMP_PWR_EN
VGA_CAM_DATA[6]
Y-
Y+
X+
KEY_ROW[2]
PM_ON_SW_N
VREG_MSMP_2.7V
KEY_COL[0]
KEY_COL[1] TOUCH_PENIRQ_N TOUCH_I2C_SCL
TOUCH_I2C_SDA
MMP_CAM_DATA[0]
MMP_CAM_DATA[1]
MMP_CAM_DATA[2]
MMP_CAM_DATA[3]
VGA_CAM_DATA[0]
VGA_CAM_DATA[1]
VGA_CAM_DATA[2]
VGA_CAM_DATA[3]
MMP_CAM_DATA[4]
MMP_CAM_DATA[5]
MMP_CAM_DATA[6]
MMP_CAM_DATA[7]
VGA_CAM_DATA[4]
VGA_CAM_DATA[5]
VGA_CAM_DATA[6]
VGA_CAM_DATA[7]
VGA_CAM_PWDN
VGA_CAM_DATA[5]
VGA_CAM_MCLK
MMP_CAM_PCLK
VGA_CAM_DATA[0]
VGA_CAM_DATA[1]
7. CIRCUIT DIAGRAM
- 182 -
BB
A
11
CAMERA COVER DETECT
EE
2
B
F
9
E
11
3
5 10 8
8 5
WHEEL SWITCH DETECT
MAIN - SUB B to B Conn.
12
BLUETOOTH
LG INNOTEK
8
1 9
11 6
7 6 8 10
F
9
4
A
6
F
7
12
D
C
12
D
7
H
Header
B
11
SPEAKER PAD
AXK840225WG
10
D
C
9
Micro SD
SPEAKER +/-
G
D
5
12
A
C
E
F
10
4 7 3
H
1
A
2 6
C
5
G
TP802
+VPW
R
100K
R
802
C803
VR
EG
_M
SM
P_2.7V
VR
EG
_B
T_2.85V
1u
C
809
33p
TP800
U800
A3212EELLT-T
G1
G2 OUT
VDD
VR
EG
_M
M
C
_3.0V
100K
R
318
C804
1u
VR
EG
_M
SM
P_2.7V
100K
R
804
38
39
4
40
5
6
7
8
9
23
24
25
26
27
28
29
3
30
31
32
33
34
35
36
37
G2
1
10
11
12
13
14
15
16
17
18
19
2
20 21
22
C802
CN801
G1
1000p
10K
R
809
OUT801
10K
R
808
R
806
100K
0
R
800
BT_ANT
VREG_BT_2.85V
C814
2.2u
C906 C909
10p 0.1u
VREG_MSMP_2.7V
0.1u
C908
1u
C
807
C811
100p
R
803
100K
C812
0.1u
33p
VR
EG
_M
M
C
_3.0V
C
810
R807
BT_GND
0
100K
R
805
VREG_MSMP_2.7V
C800 NA
33p
R
811
CD_DAT3_CS
CLK_SCLK
CMD_DI
COMMON
DAT0_DO
DAT1_RSV
DAT2_RSV
DETECT
DUMMY1
DUMMY2
VDD
VSS
C813
S800 SCHA1B0102
100p
VREG_MSMP_2.7V
NA L800
C801
OUT800
TP801
1000p
C907
R
801
100K
VREG_MSMP_2.7V
10p
R
908
100KG1
G2 OUT
VDD
R
909
100KG1
G2 OUT
VDD
A3212EELLT-T
U904
A3212EELLT-T
U903
5 SYNC_DET_TX_EN
3 VCC_OUT
14
VDD_BAT
VDD_INT 2
VDD_MSM 10
7
XTAL_IN
R
810
33p
A
N
T
16
9 CLK_REF
1
G
N
D
1
G
N
D
2
6 8
G
N
D
3
G
N
D
4
15 17
PG
N
D
1
PG
N
D
2
18 19
PG
N
D
3
PG
N
D
4
20
RX_BB_TX_BB 13
SBCK 11
12 SBDT
SBST 4
M800 LBRQ-2B43A
C
805
33p
33p
C
806
C
808
33p
10p
C349 C348
0.1u
MMP_CAM_PWR_EN
WHEEL_SW_L
WHEEL_SW_R
CAM_MIC+
MICROSD_DATA[3]
MICROSD_DATA[2]
MICROSD_DATA[1]
MICROSD_DATA[0]
MICROSD_CMD
MICROSD_DETECT
MICROSD_CLK
SPK_OUT+
SPK_OUT-
HOOK_SENSE_N
EAR_MIC_P
CAM_COVER_DET
CAM_COVER_DET WHEEL_SW_L
WHEEL_SW_R
BT_CLK
MICROSD_DETECT
MICROSD_CLK
MICROSD_CMD
V_BACK_UP
CAM_VDD_SD_1.8V
CAM_VDD_AF_2.7V
BT_DATA
BT_CLK
BT_SBDT
BT_SBCK
BT_SBST
BT_TX_RX_N
TCXO_BT
SPK_OUT+
SPK_OUT-
MICROSD_DATA[2]
MICROSD_DATA[1]
MICROSD_DATA[0]
MICROSD_DATA[3]
BT_SBCK
BT_SBDT
BT_SBST
BT_TX_RX_N
TCXO_BT
BT_DATA
7. CIRCUIT DIAGRAM
- 183 - LGE Internal Use Only
12
E
2
4
B
E
150mA
7
D
H
1 8
4
12
6
3
7 6
9 7 11
F
5
H
10
C
A
11
G
2
G
1
B
5
4 3
C
12
C C
A
10
150mA
D
6
A
11
Headset Hook Switch
F
3
2 6
4 2
F
A
9
F
5
E
B
8
H
E
11
G
5
H
12
G
D
BACK_UP BATTERY
9
(VDD_SD)
D
9
B
1 3
7
1 8 10
5MP CAMERA POWER
10 8
CAM MIC
INSTPAR
PLW0501H-LF
ZD900
MIC900
SPOB-413S42-RC3310BC
1
2
+VPWR
BAT900
C900
1u
4 NC
1 VDD
3 VOUT
R1114D271D U901
6 CE_OR_NC
GND1 2 GND2 5
C904
1u
C903
1u 1u
CAM_VDD_SD_1.8V +VPWR
C901
R905
10K
VREG_MSMP_2.7V
R907
5.1K
100K
C905
0.1u
R
904
VIN+
VIN- 4
R
906
1M
U902
NCS2200SQ2T2G
2
GND
1
OUT
VCC
5
3
C902
1u
U900 R1114D181D
6 CE
GND1 2
GND2 5 NC 4
1
VDD VOUT
3
V_BACK_UP
CAM_MIC+
MMP_CAM_PWR_EN
MMP_CAM_PWR_EN
HOOK_SENSE_N
EAR_MIC_P
CAM_VDD_AF_2.7V
7. CIRCUIT DIAGRAM
Copyright 2008 LG Electronics. Inc. All right reserved.
- 184 - LGE Internal Use Only Copyright 2007 LG Electronics. Inc. All right reserved.
- 185 -
8. BGA IC PIN MAP
1. MSM6280
(Top View)
8. BGA IC PIN MAP
- 186 -
8. BGA IC PIN MAP
1. MSM6280
(Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not used
Used
- 187 -
8. BGA IC PIN MAP
2. MCP (Top View)
- 188 -
8. BGA IC PIN MAP
2. MCP (Top View)
Not used
Used
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
- 189 -
8. BGA IC PIN MAP
3. PM6650-2 (PMIC)
- 190 -
8. BGA IC PIN MAP
4. WM8983 (Audio codec)
- 191 -
8. BGA IC PIN MAP
5. FM RADIO
A
B
C
D
E
1 2 3 4 5 6
- 192 -
8. BGA IC PIN MAP
6. ZORAN(ZR3453)
A
B
C
D
E
F
G
H
J
K
L
M
N
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P
- 193 - LGE Internal Use Only
9. PCB LAYOUT
Copyright 2008 LG Electronics. Inc. All right reserved.
<LDO IC>
- 1.0V, 1.2V power supply
<Xtal>
- Check the frequency (27MHz)
<Multi media IC>
- Camcorder, Camera operation
<RF IC>
- GSM, WCDMA TX/RX operation
<UMTS RX SAW filter>
- WCDMA RX operation
<RF SW>
<Baseband and RF IC>
- Check the battery voltage and
Outputs of LDOs-Rx operation
<Charging IC>
- Check the TA and bettery
<Audio Codec>
- Headset, speaker operation
<Memory IC>- Check S/W
download
<Xtal>- Check the frequency
(19.2MHz)
<GSM900 TX SAW filter>
- GSM900 TX operation
<UMTS Duplexer>
- WCDMA RX,TX separation
<GSM PAM>- GSM TX
amplifier operation
<FEM>- RX, TX
switching selection
<PM IC>- Power management
9. PCB LAYOUT
<FM radio IC>
- FM radio operation
<Headphone AMP>
- Headset operation
<OVP IC>
- Over voltage protection
<Charge Pump>
- LCD backlight charge pump
9. PCB LAYOUT
9. PCB LAYOUT
10. Calibration
- 197 -
10. Calibration
10.1 Usage of Hot-Kimchi
10.1.1 RF Calibration
Procedure
1. Click SETTING in menu, and logic operation in sub-menu.
Choose 1 in LOGIC MODE (means calibration alone)
2. Select the model name which you want in list box.
3. Click Start button to calibrate a phone.
Model Name
Calibration Only
KU990R
- 198 -
10. Calibration
10.1.2 Basic Setting
Contents
- Click SETTING in menu, and logic operation in sub-menu.
- You can select how to control AT command, Test Set, and Power supply in DLL Operating Mode.
- You can set UART Port and logic mode. (mode 1 : Calibration alone)
- You can set Result Files name type. If you choose TIME, the saved files name is saved in a real-
time.
- You can run the multi mode. (S/B1,S/B2 : You can use S/B1 for only one port)
- You can set the path of HOTKIMCHI program.
- 199 -
10. Calibration
10.1.3 Log of RF Calibration and Test
Contents
- On Running, Log window is created in center area. It displays logs of command, and measurements
of Calibration or Test.
- The result files are saved in the directory C:\Jhangee\debug\Cal, C:\Jhangee\debug\Auto, or
C:\Jhangee\debug\CalAuto.
KU990R
- 200 -
- 201 -
1 2
4
5
8
9
10 11
12
6 17
18
22
21
31
20
24
26
27
28
32
33
34
39
35
40 41
42
43
44
45
38
82
80
86 79 78
68
67 66 65
64
87
88
81
73
83
72
71 70 69
63
74 75 76
77
62
60
61
58
57 56
59
52
54
50
46
37
36
84
85 30
29
25 19
16
15
14
13
7
3
55
53
51
49
48
47
23
11. EXPLODED VIEW & REPLACEMENT PART LIST
11.1 EXPLODED VIEW
A
B
C
D
ASS'Y EXPLODED VIEW
- 203 -
<Mechanic component>
Note: This Chapter is used for reference, Part order
is ordered by SBOM standard on GCSC
Level
Location
No.
Description Part Number Spec Color Remark
1 IMT,BAR/FLIP TIMT0000711 Black
2 AAAY00 ADDITION AAAY0260102 Without Color
3 WSAY00 SOFTWARE,APPLICATION WSAY0113601 ; , , ,WORLD WIDE , ,
3 MCCL00 CAP,BOX MCCL0001103 BOX, TW, , , , , Without Color
3 MCJZ00 COVER MCJZ0049101 BOX, TW, , , , , Without Color
3 MLAC00 LABEL,BARCODE MLAC0004501 Export(105*40) Without Color
3 MLAJ00 LABEL,MASTER BOX MLAJ0004401 LABEL,MASTER BOX(for C1300i NEW_CGR) Without Color
3 MLAP00 LABEL,UNIT MLAP0001115 Reliance Seal Label Without Color
3 MPAA00
PACKING,BLISTER(LOWE
R)
MPAA0002003 PRESS, PB, , , , , Without Color
3 MPAB00
PACKING,BLISTER(UPPER
)
MPAB0001603 PRESS, PB, , , , , Without Color
3 MPCY00 PALLET MPCY0011201 PALLET(for G5400 O2U 1200x1000_Wooden) Silver
2 APEY00 PHONE APEY0415111 Black
3 ACGK00 COVER ASSY,FRONT ACGK0093401 Without Color
4 ACGZ00 COVER ASSY ACGZ0013901 UPPER Without Color
5 MCJZ00 COVER MCJZ0046501 MOLD, PC LUPOY SC-1004A, , , , , Black 5
6 MICA01 INSERT,FRONT MICA0013901 2.2X4.0 Without Color 9
5 MFBB00 FILTER,RECEIVER MFBB0023201 COMPLEX, (empty), , , , , Without Color 4
5 MPBM00 PAD,RECEIVER MPBM0019201 COMPLEX, (empty), , , , , Without Color 7
5 MTAF TAPE,MOTOR MTAF0006001 Without Color 6
5 MTAK00 TAPE,CAMERA MTAK0002501 COMPLEX, (empty), , , , , Without Color 8
4 ACHA00 COVER SUB ASSY,FRONT ACHA0001801 Without Color
5 MBJL00 BUTTON,SIDE MBJL0042701 MOLD, ABS MP-211, , , , , Silver 27
5 MCCC00 CAP,EARPHONE JACK MCCC0045901 COMPLEX, (empty), , , , , Black `4
5 MCJK00 COVER,FRONT MCJK0073001 MOLD, PC LUPOY SC-1004A, , , , , Black 22
6 MICA00 INSERT,FRONT MICA0019901 M1.4 D2.2 L1.5 Gold 34
5 MDAG00 DECO,FRONT MDAG0028401 MOLD, PC LUPOY SC-1004A, , , , , Black 17
5 MKBZ00 KNOB MKBZ0002101 MOLD, PC LUPOY SC-1004A, , , , , Black 25
5 MLEA00 LOCKER,BATTERY MLEA0039301 MOLD, PC LUPOY SC-1004A, , , , , Black 18
5 MPBT00 PAD,CAMERA MPBT0044701 COMPLEX, (empty), , , , , Without Color 33
5 MSDC00 SPRING,LOCKER MSDC0010601 Without Color 19
5 MSIY00 SHAFT MSIY0001201 CUTTING, STS, , , , , Silver 29
5 MTAA00 TAPE,DECO MTAA0142501 COMPLEX, (empty), , , , , Without Color 23
- 204 -
Level
Location
No.
5 MTAB00 TAPE,PROTECTION MTAB0185401 COMPLEX, (empty), , , , , Without Color 28
5 MTAC00 TAPE,SHIELD MTAC0057901 COMPLEX, (empty), , , , , Without Color 32
5 MTAZ00 TAPE MTAZ0193901 COMPLEX, (empty), , , , , Black 11
5 MTAZ01 TAPE MTAZ0195701 COMPLEX, (empty), , , , , Without Color 12
4 MKAG00 KEYPAD,MAIN MKAG0000901 MOLD, PC LUPOY SC-1004A, , , , , Black 35
4 MLAZ00 LABEL MLAZ0038303 PRINTING, (empty), , , , , White
4 MPBG00 PAD,LCD MPBG0065101 COMPLEX, (empty), , , , , Black
4 MPBG01 PAD,LCD MPBG0068901 COMPLEX, (empty), , , , , Without Color
4 MPBT00 PAD,CAMERA MPBT0044901 COMPLEX, (empty), , , , , Without Color 38
4 MPBZ00 PAD MPBZ0193801 COMPLEX, (empty), , , , , Without Color
4 MTAC00 TAPE,SHIELD MTAC0058201 COMPLEX, (empty), , , , , Without Color
4 MTAD00 TAPE,WINDOW MTAD0072001 COMPLEX, (empty), , , , , Without Color
4 MWAC00 WINDOW,LCD MWAC0083101 COMPLEX, (empty), , , , , Without Color
4 SACY00 PCB ASSY,FLEXIBLE SACY0063001
5 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0057301
6 SACC00
PCB ASSY,FLEXIBLE,SMT
BOTTOM
SACC0036101
7 ENBY00
CONNECTOR,BOARD TO
BOARD
ENBY0018601 10 PIN,.4 mm,STRAIGHT , ,H=0.9, SOCKET
6 SACD00
TOP
SACD0047101
7 ENBY00
CONNECTOR,BOARD TO
BOARD
ENBY0019501 20 PIN,.4 mm,ETC , ,H=1.5, Socket
7 ENBY01
CONNECTOR,BOARD TO
BOARD
ENBY0040601
30 PIN,0.4 mm,ETC , ,H=1.0 ,; , ,0.40MM ,STRAIGHT
,MALE ,SMD ,R/TP , ,
6 SPCY00 PCB,FLEXIBLE SPCY0106101 POLYI ,0.4 mm,Mutil-5,VGA-CAM ,; , , , , , , , , ,
4 SJMY00 VIBRATOR,MOTOR SJMY0008502
3 V,1.0 A,10*3.6T ,2.0Vrms 175HZ linear motor 1.5G ,;
,3V , , ,1.5G , , , ,
36
4 SURY00 RECEIVER SURY0012801 37
4 SVCY00 CAMERA SVCY0014601 CMOS ,MEGA ,5M AF, Sony 1/2.8", HPCB 39
4 SVCY01 CAMERA SVCY0014001 CMOS ,VGA ,5.5x11.4x3.2t, Magna 1/7.4"
- 205 -
Level
Location
No.
4 SVLM00 LCD MODULE SVLM0025501
MAIN ,240*400 ,45.08*75*2.2 ,262k ,TFT ,TM ,DAC
IC(Sharp) ,
10
3 ACGM00 COVER ASSY,REAR ACGM0094701 Without Color
4 ENZY00 CONNECTOR,ETC ENZY0019901 3 PIN,3 mm,STRAIGHT , , 70
4 ESQY00 SWITCH,ROTARY ESQY0001201
6 V,0.005 A,HORIZONTAL ,0.04 G,KU990 Wheel Switch
,; ,2C2P ,6VDC ,0.5MA ,HORIZONTAL ,
81
4 MCJN00 COVER,REAR MCJN0069201 MOLD, PC LUPOY SC-1004A, , , , , Black 75
4 MDAD00 DECO,CAMERA MDAD0032801 PRESS, Al, 0.3, , , , Black 80
4 MFBC00 FILTER,SPEAKER MFBC0033001 COMPLEX, (empty), , , , , Without Color 64
4 MFBD00 FILTER,MIKE MFBD0025301 COMPLEX, (empty), , , , , Without Color 74
4 MFBD01 FILTER,MIKE MFBD0025401 COMPLEX, (empty), , , , , Black 62
4 MLAB00 LABEL,A/S MLAB0001102 C2000 USASV DIA 4.0 White
4 MPBH00 PAD,MIKE MPBH0032201 COMPLEX, (empty), , , , , Without Color 57,71
4 MPBH01 PAD,MIKE MPBH0032301 COMPLEX, (empty), , , , , Without Color
4 MPBH02 PAD,MIKE MPBH0032401 COMPLEX, (empty), , , , , Without Color 72
4 MPBM00 PAD,RECEIVER MPBM0019401 COMPLEX, (empty), , , , , Without Color 59
4 MPBT00 PAD,CAMERA MPBT0044801 COMPLEX, (empty), , , , , Without Color
4 MPBU00 PAD,CONNECTOR MPBU0007601 COMPLEX, (empty), , , , , Without Color 56
4 MPBZ00 PAD MPBZ0187301 COMPLEX, (empty), , , , , Without Color 76
4 MPFZ01 PLATE MPFZ0029901 COMPLEX, (empty), , , , , Without Color 82
4 MSDD00 SPRING,PLATE MSDD0006701 PRESS, Bs, 0.15, , , , Gold 66
4 MSDD01 SPRING,PLATE MSDD0006901 PRESS, Bs, , , , , Gold 63
4 MTAD00 TAPE,WINDOW MTAD0072101 COMPLEX, (empty), , , , , Without Color 77
4 MTAJ00 TAPE,FLEXIBLE PCB MTAJ0001701 COMPLEX, (empty), , , , , Without Color 60
4 MTAZ01 TAPE MTAZ0197401 COMPLEX, (empty), 0.1, , , , Without Color 65
4 MWAE00 WINDOW,CAMERA MWAE0028001 CUTTING, Quartz Glass, , , , , Without Color 78
4 MWAE01 WINDOW,CAMERA MWAE0026401 MOLD, Polyarylamide IXEF 1032, , , , , Without Color 67
3 MLAK00 LABEL,MODEL MLAK0006901
5 MLAZ00 LABEL MLAZ0038301 PID Label 4 Array Without Color
- 206 -
Level
Location
No.
4 SNGF00 ANTENNA,GSM,FIXED SNGF0027102
3.0 ,-2.0 dBd, ,EGSM+DCS+PCS+W-BAND I, INTERNAL
,; ,QUAD ,-2.0 ,50 ,3.0
58,73
4 SNGF01 ANTENNA,GSM,FIXED SNGF0027201
3.0 ,-2.0 dBd, ,BLUETOOTH, INTERNAL ,; ,SINGLE ,-2.0
,50 ,3.0
3 GMEY00 SCREW MACHINE,BIND GMEY0010601 1.4 mm,2.5 mm,MSWR3(BK) ,N ,+ ,NYLOK Black 84
3 SACY00 PCB ASSY,FLEXIBLE SACY0063003
4 SACE00 PCB ASSY,FLEXIBLE,SMT SACE0057302
5 SACD00
TOP
SACD0047102
6 CN601
CONNECTOR,BOARD TO
BOARD
ENBY0041601
28 PIN,0.4 mm,ETC , ,B to B ,; , ,0.40MM ,[empty] ,MALE
,SMD ,BK , ,
6 ENBY01
CONNECTOR,BOARD TO
BOARD
ENBY0040601
30 PIN,0.4 mm,ETC , ,H=1.0 ,; , ,0.40MM ,STRAIGHT
,MALE ,SMD ,R/TP , ,
5 SPCY00 PCB,FLEXIBLE SPCY0103601 POLYI ,0.2 mm,DOUBLE ,5M-F-CAM ,; , , , , , , , , ,
3 SAFY00 PCB ASSY,MAIN SAFY0203411 44
4 SAFB00 PCB ASSY,MAIN,INSERT SAFB0075601
5 ADCA00 DOME ASSY,METAL ADCA0069301 Without Color 43
5 SPKY00 PCB,SIDEKEY SPKY0049301 POLYI ,0.2 mm,DOUBLE , ,; , , , , , , , , ,
4 SAFF00 PCB ASSY,MAIN,SMT SAFF0124311
5 SAFC00
PCB ASSY,MAIN,SMT
BOTTOM
SAFC0091501
6 C100 CAP,CERAMIC,CHIP ECCH0001002 180 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C101 CAP,CERAMIC,CHIP ECCH0000129 120 pF,50V,J,NP0,TC,1005,R/TP
6 C102 INDUCTOR,CHIP ELCH0001401 15 nH,J ,1005 ,R/TP ,Pb Free
6 C104 CAP,CERAMIC,CHIP ECCH0000196 0.75 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C105 CAP,CHIP,MAKER ECZH0000841 56 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 C106 CAP,CERAMIC,CHIP ECCH0000107 6 pF,50V,D,NP0,TC,1005,R/TP
6 C108 CAP,CHIP,MAKER ECZH0000806 5 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C111 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP
6 C112 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP
6 C118 CAP,CERAMIC,CHIP ECCH0000393 22 uF,6.3V ,M ,X5R ,HD ,2012 ,R/TP
<Main component>
- 207 -
Level
Location
No.
6 C119 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP
6 C125 CAP,CERAMIC,CHIP ECCH0004904 1 uF,6.3V ,K ,X5R ,TC ,1005 ,R/TP
6 C135 CAP,TANTAL,CHIP ECTH0005501
33 uF,10V ,M ,L_ESR ,2012 ,R/TP ,; , ,[empty] ,[empty] ,
,-55TO+125C , ,[empty] ,[empty] ,[empty] ,[empty]
6 C148 CAP,CHIP,MAKER ECZH0001105 8200 pF,16V ,K ,X7R ,HD ,1005 ,R/TP
6 C155 CAP,CERAMIC,CHIP ECCH0000101 .5 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 C159 CAP,CHIP,MAKER ECZH0000846 8.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
- 208 -
Level
Location
No.
6 C160 CAP,TANTAL,CHIP ECTH0004101 22 uF,6.3V ,M ,STD ,1608 ,R/TP
6 C170 CAP,CERAMIC,CHIP ECCH0000178 1.8 pF,50V ,D ,NP0 ,TC ,1005 ,R/TP
6 C233 CAP,TANTAL,CHIP ECTH0003701 10 uF,6.3V ,M ,L_ESR ,1608 ,R/TP
6 C239 CAP,TANTAL,CHIP,MAKER ECTZ0004701 4.7 uF,6.3V ,M ,STD ,1608 ,R/TP
- 209 -
Level
Location
No.
33 uF,10V ,M ,L_ESR ,2012 ,R/TP ,; , ,[empty] ,[empty] ,
,-55TO+125C , ,[empty] ,[empty] ,[empty] ,[empty]
6 C504 CAP,CERAMIC,CHIP ECCH0006201 4.7 uF,6.3V ,K ,X5R ,TC ,1608 ,R/TP
6 C511 CAP,CHIP,MAKER ECZH0001421 2.2 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
6 C512 CAP,CHIP,MAKER ECZH0003501 1 uF,6.3V ,K ,X5R ,HD ,1608 ,R/TP
10 uF,10V ,M ,STD ,1608 ,R/TP ,; , ,[empty] ,[empty] , ,-
55TO+125C , ,[empty] ,[empty] ,[empty] ,[empty]
6 C515 CAP,CERAMIC,CHIP ECCH0000198 2.2 uF,6.3V ,M ,X5R ,TC ,1005 ,R/TP
6 C518 CAP,CERAMIC,CHIP ECCH0007801 4.7 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP
10 uF,10V ,M ,STD ,1608 ,R/TP ,; , ,[empty] ,[empty] , ,-
55TO+125C , ,[empty] ,[empty] ,[empty] ,[empty]
- 210 -
Level
Location
No.
6 C530 CAP,CERAMIC,CHIP ECCH0000199 12 nF,16V ,K ,X7R ,HD ,1005 ,R/TP
6 C555 CAP,CERAMIC,CHIP ECCH0005604 10 uF,6.3V ,M ,X5R ,TC ,1608 ,R/TP
6 C590 CAP,CERAMIC,CHIP ECCH0000198 2.2 uF,6.3V ,M ,X5R ,TC ,1005 ,R/TP
- 211 -
Level
Location
No.
6 CN300
CONNECTOR,BOARD TO
BOARD
ENBY0036001 40 PIN,0.4 mm,ETC , ,H=1.0, Socket
6 CN500 CONNECTOR,I/O ENRY0006401 18 PIN,0.4 mm,ANGLE , ,H=2.5, Reverse Type
6 CN600
CONNECTOR,BOARD TO
BOARD
ENBY0040701
30 PIN, mm,ETC , , ,; , ,0.40MM ,STRAIGHT ,FEMALE
,SMD ,R/TP ,1.0 ,
6 CN601
CONNECTOR,BOARD TO
BOARD
6 CN603
CONNECTOR,BOARD TO
BOARD
6 CN701
CONNECTOR,BOARD TO
BOARD
ENBY0040701
30 PIN, mm,ETC , , ,; , ,0.40MM ,STRAIGHT ,FEMALE
,SMD ,R/TP ,1.0 ,
6 D400 DIODE,TVS EDTY0008607 SC70-6L ,6 V,200 W,R/TP ,PB-FREE
6 D501 DIODE,SWITCHING EDSY0011901
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,
IR=30uA(VR=10V)
6 D502 DIODE,TVS EDTY0007401 SMD ,12 V,350 W,R/TP ,
6 D600 DIODE,TVS EDTY0008601 SOD-323 ,6 V,400 W,R/TP ,PB-FREE
6 FB500 FILTER,BEAD,CHIP SFBH0001501 120 ohm,1608 ,
6 FB504 FILTER,BEAD,CHIP SFBH0008103
1000 ohm,1005 ,chip bead, 200mA,DCR0.9ohm ,; , ,
,SMD ,R/TP
6 FL100 FILTER,SEPERATOR SFAY0010002
900,1800 ,1900.2100 , dB, dB, dB, dB,ETC ,GSM
TRIPLE, WCDMA2100 FEM, 5X4X1.3
6 FL101 FILTER,SAW SFSY0030201
897.5 MHz,1.4*1.1*0.6 ,SMD ,Pb-
free_SAW_GSM900_Tx
2140 MHz,1.4*1.1*0.62 ,SMD ,2110M~2170M, IL 2.0,
5pin, U-B, 50-100_10, WCDMA BAND I Rx ,; ,2140
,1.4*1.1*0.62 ,SMD ,R/TP
6 FL103 DUPLEXER,IMT SDMY0001202
1950 MHz,2140 MHz,1.8 dB,2.4 dB,43 dB,45
dB,3.0*2.5*1.1 ,SMD ,SAW DUPLEXER ,; ,2140 ,45
,1950 ,43 ,2.4 ,1.8 ,3.0*2.5*1.1 ,DUAL ,SMD ,R/TP
- 212 -
Level
Location
No.
1950 MHz,1.4*1.1*0.62 ,SMD ,RF Filter for WCDMA
2Ghz ,; ,1950 ,1.4*1.1*0.62 ,SMD ,P/TR
6 FL300 FILTER,EMI/POWER SFEY0011601 SMD ,SMD ,18 V,4ch. EMI_ESD Filter (50 Ohm,15pF)
6 J400 CONN,SOCKET ENSY0018701 6 PIN,ETC , ,2.54 mm,H=1.8
6 L100 CAP,CERAMIC,CHIP ECCH0000185 5.6 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP
6 L101 INDUCTOR,CHIP ELCH0001035 4.7 nH,S ,1005 ,R/TP ,PBFREE
6 L104 INDUCTOR,CHIP ELCH0001031 15 nH,J ,1005 ,R/TP ,PBFREE
6 L106 INDUCTOR,CHIP ELCH0005014 5.6 nH,S ,1005 ,R/TP ,
6 L107 INDUCTOR,CHIP ELCH0001031 15 nH,J ,1005 ,R/TP ,PBFREE
6 L109 INDUCTOR,CHIP ELCH0005004 22 nH,J ,1005 ,R/TP ,
6 L115 INDUCTOR,CHIP ELCH0004703 1 nH,S ,1005 ,R/TP ,
6 L126 INDUCTOR,CHIP ELCH0004705 8.2 nH,J ,1005 ,R/TP ,
6 L500 INDUCTOR,SMD,POWER ELCP0008001 4.7 uH,M ,2.5*2.0*1.0 ,R/TP ,
6 L501 INDUCTOR,SMD,POWER ELCP0008004
4.7 uH,M ,1 ,R/TP , ,; , ,0.3NH , , , , , ,NON SHIELD
,2.5X2X1MM ,11MM ,R/TP
- 213 -
Level
Location
No.
6 MIC500 MICROPHONE SUMY0010603
PIN ,42 dB,4.72*3.76*1.25 ,MEMS MIC , , , ,OMNI
,1.5TO5V , ,SMD
6 Q100 TR,BJT,ARRAY EQBA0000602
TESV ,200 mW,R/TP ,EPITAXIAL PLANAR NPN/PNP
TRANSISTOR
6 R100 RES,CHIP,MAKER ERHZ0000212 12 Kohm,1/16W ,F ,1005 ,R/TP
6 R101 RES,CHIP,MAKER ERHZ0000310 680 ohm,1/16W ,F ,1005 ,R/TP
6 R104 RES,CHIP,MAKER ERHZ0003801 5.1 ohm,1/16W ,J ,1005 ,R/TP
6 R107 RES,CHIP ERHY0013101 2.7 ohm,1/16W ,J ,1005 ,R/TP
6 R109 RES,CHIP,MAKER ERHZ0000402 10 ohm,1/16W ,J ,1005 ,R/TP
6 R115 RES,CHIP ERHY0003301 100 ohm,1/16W ,J ,1005 ,R/TP
6 R120 RES,CHIP,MAKER ERHZ0000406 100 Kohm,1/16W ,J ,1005 ,R/TP
- 214 -
Level
Location
No.
6 R504 RES,CHIP,MAKER ERHZ0003901
0.1 ohm,1/4W ,F ,2012 ,R/TP ,; ,0.1 ,1% ,1/4W ,2012
,R/TP
6 R622 RES,CHIP,MAKER ERHZ0000318 80.6 Kohm,1/16W ,F ,1005 ,R/TP
- 215 -
Level
Location
No.
6 R728 RES,CHIP ERHY0000147 56K ohm,1/16W,F,1005,R/TP
6 SW100 CONN,RF SWITCH ENWY0005301
,SMD , dB,H=1.85 ,; ,3.00MM ,STRAIGHT ,RF ADAPTER
,SMD ,R/TP ,AU , ,
6 SW600 SWITCH,SLIDE ESSY0004701
4 V,300 mA,HORIZONTAL , G,Slide Switch ,; ,1C3P
,[empty] ,[empty] ,[empty] ,1.5N , ,TP
6 U100 IC EUSY0300502
QFN ,56 PIN,R/TP ,chartered,GSM, WCDMA Single RF
Transceiver, 8X8X0.9 ,; ,IC,Tx/Rx
6 U101 PAM SMPY0013501 35 dBm,51 %, A, dBc, dB,7x7x1.1 ,SMD ,Polar Edge
6 U102 IC EUSY0278501 SON5-P-0.50 ,5 PIN,R/TP ,INVERTER GATE, Pb Free
6 U104
COUPLER,RF
DIRECTIONAL
SCDY0003403
-18 dB,-.25 dB,-33 dB,1.0*0.58*0.35 ,SMD ,1920M ~
1980M, 4pin, Pb Free , ,[empty] , , ,SMD ,R/TP
6 U105 PAM SMPY0013301
dBm,43 %, A,-40 dBc,26 dB,4x4x1.1 ,SMD ,2.1GHz,
HSDPA
6 U200 IC EUSY0295601
CSP ,409 PIN,R/TP ,WCDMA/GSM/GPRS/EDGE/HSDPA
Base Band
6 U302 IC EUSY0330701
FPBGA ,180 PIN,R/TP ,5M Camera,VGA30,Multi audio
codec
6 U402 IC EUSY0333402
FBGA ,225 PIN,ETC ,2G(LB/128Mx16/2.7V)
NAND+1G(8Mx4x32) SDRAM ,; ,IC,MCP
6 U500 IC EUSY0332901
WDFN ,8 PIN,R/TP ,-12V, 6.3A, Single P-MOSFET &
DUAL Transistor
6 U501 IC EUSY0306302 BCCS ,84 PIN,R/TP ,7x7, MSMC(1.2V), pbfree
6 U502 IC EUSY0342001
QFN ,32 PIN,R/TP ,CODEC,3D, 5band equalizer,Stereo
HP AMP, Stereo SPKAMP ,; ,IC,Audio Codec
6 U603 IC EUSY0140901 SSOP5-P-0.65 ,5 PIN,R/TP ,XOR GATE, Pb Free
6 U605 IC EUSY0140901 SSOP5-P-0.65 ,5 PIN,R/TP ,XOR GATE, Pb Free
6 U606 IC EUSY0335701 QFN ,8 PIN,R/TP ,1.2W, Mono, Differencial Audio AMP
6 U701 IC EUSY0251501
DFN33-12 ,12 PIN,R/TP
,DUALDCDC_DMBpower,400mA,600mA,1Mhz
6 VA300 VARISTOR SEVY0004101 5.6 V, ,SMD ,360pF, 1005
6 VA301 DIODE,TVS EDTY0009401
VMN2 ,5 V,10 W,R/TP ,1.0*0.6*0.4 ,; , ,7.82V , , ,100mW
,[empty] ,[empty] ,2P ,1
6 VA500 VARISTOR SEVY0007301 5 V,<0.5pF ,SMD ,
6 VA501 VARISTOR SEVY0007301 5 V,<0.5pF ,SMD ,
6 VA502 VARISTOR SEVY0001001 14 V, ,SMD ,50pF, 1005
6 VA507 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE
- 216 -
Level
Location
No.
6 VA508 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE
6 X100 VCTCXO EXSK0007802
19.2 MHz,1.5 PPM,10 pF,SMD ,3.3*2.5*1.0 , ,; , ,2PPM
,2.8V , , , , ,SMD ,P/TP
6 X200 RESONATOR EXRY0002401
48 MHz,.5 %,14 pF,SMD ,2.0*1.2*0.65 ,Outgoing
Tolerance 0.2%, 0.05% at -40'C ~ +85C, Built-In Cap
6 X300 X-TAL EXXY0023301
27 MHz,50 PPM,9 pF,50 ohm,SMD ,3.2*2.5*0.7 ,30ppm
at -20'C ~ +70'C, Pb Free
6 X500 X-TAL EXXY0018701
32.768 KHz,20 PPM,12.5 pF,70 Kohm,SMD ,3.2*1.5*0.9
,
5 SAFD00 PCB ASSY,MAIN,SMT TOP SAFD0091001
- 217 -
Level
Location
No.
6 C334 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
6 C335 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP
- 218 -
Level
Location
No.
6 C562 CAP,CERAMIC,CHIP ECCH0002004 0.22 uF,10V ,K ,B ,TC ,1005 ,R/TP
6 C573 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE
6 C574 DIODE,TVS EDTY0008606 DFN-2 ,7.82 V,150 mW,R/TP ,PB-FREE
6 C578 CAP,CERAMIC,CHIP ECCH0002004 0.22 uF,10V ,K ,B ,TC ,1005 ,R/TP
6 C585 CAP,CHIP,MAKER ECZH0001215 1 uF,10V ,K ,X5R ,TC ,1005 ,R/TP
- 219 -
Level
Location
No.
6 D500 DIODE,SWITCHING EDSY0011901
EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,
IR=30uA(VR=10V)
6 FL600 FILTER,EMI/POWER SFEY0011701 SMD ,SMD ,18 V,4ch. EMI_ESD Filter (10 Ohm,7.5pF)
6 L127 INDUCTOR,CHIP ELCH0009114 100 nH,J ,1005 ,R/TP ,coil
6 L300 INDUCTOR,CHIP ELCH0010401 2.2 uH,M ,1005 ,R/TP ,
6 L504 INDUCTOR,CHIP ELCH0010401 2.2 uH,M ,1005 ,R/TP ,
6 LD700 DIODE,LED,CHIP EDLH0011901 WHITE ,1608 ,R/TP ,PB-FREE(ZENER)
6 LD701 DIODE,LED,CHIP EDLH0007901 RED ,1608 ,R/TP ,Indicator,0.4T Red LED
6 LD702 DIODE,LED,CHIP EDLH0014501
GREEN ,1608 ,R/TP , ,; ,[empty] ,2.85~3.25 , , , , ,[empty]
,[empty] ,2P
6 LD703 DIODE,LED,CHIP EDLH0007901 RED ,1608 ,R/TP ,Indicator,0.4T Red LED
6 LD704 DIODE,LED,CHIP EDLH0011901 WHITE ,1608 ,R/TP ,PB-FREE(ZENER)
6 LD705 DIODE,LED,CHIP EDLH0014501
GREEN ,1608 ,R/TP , ,; ,[empty] ,2.85~3.25 , , , , ,[empty]
,[empty] ,2P
- 220 -
Level
Location
No.
6 R339 RES,CHIP ERHY0000170 390 ohm,1/16W ,F ,1005 ,R/TP
- 221 -
Level
Location
No.
6 SPFY00 PCB,MAIN SPFY0151801 FR-4 ,0.8 mm,STAGGERED-10 , ,; , , , , , , , , ,
6 U103 IC EUSY0335301
WLCSP(Coated) ,25 PIN,R/TP ,FM Tuner(RDS),
3.35*3.3, Pb Free
6 U300 IC EUSY0290701
HVSOF5 ,5 PIN,R/TP ,150mA, 2.8V, Auto Power Save
LDO
6 U301 IC EUSY0336502 , PIN,R/TP , ,; ,IC,Charge Pump
6 U303 IC EUSY0346001
SON1612 ,6 PIN,R/TP ,1.9V 150mA Single LDO ,;
,IC,LDO Voltage Regulator
6 U304 IC EUSY0338301
uMLP ,10 PIN,R/TP ,High Speed USB Siwitch 2.0 3.7pF
6.5ohm 1.4X1.8
6 U400 IC EUSY0317101 WQFN ,10 PIN,R/TP ,1.8*1.4*0.75
6 U401 IC EUSY0271201 TQFN ,16 PIN,R/TP ,Quad Analog switch, Pb Free
6 U503 IC EUSY0333001
SON1612 ,6 PIN,R/TP ,3.3V, 150mA LDO Pb-Free,
Active High
6 U504 IC EUSY0303901
QFN,130mW Capless Stereo Headphone Driver ,16
PIN,R/TP ,Capless hp amp
6 U505 IC EUSY0333701 TLLGA ,8 PIN,R/TP ,OVP
6 U506 IC EUSY0175301
MICROPAK ,6 PIN,R/TP ,SPDT ANALOG SWITCH / 2:1
MUX/DEMUX, Pb Free
6 U507 IC EUSY0338301
uMLP ,10 PIN,R/TP ,High Speed USB Siwitch 2.0 3.7pF
6.5ohm 1.4X1.8
6 U600 IC EUSY0290701
HVSOF5 ,5 PIN,R/TP ,150mA, 2.8V, Auto Power Save
LDO
6 U601 IC EUSY0338701 SON1612-6 ,6 PIN,R/TP ,2.7V 150mA LDO Pb-Free
6 U604 IC EUSY0175301
MUX/DEMUX, Pb Free
6 U607 IC EUSY0175301
MUX/DEMUX, Pb Free
6 U700 IC EUSY0337101
CSP ,12 PIN,R/TP ,Touchscreen Controller IC , ,IC,A/D
Converter
6 VA602 VARISTOR SEVY0003801 18 V, ,SMD ,
6 VA700 VARISTOR SEVY0000702 14 V,10% ,SMD ,
6 VA708 VARISTOR SEVY0000702 14 V,10% ,SMD ,
- 222 -
Level
Location
No.
5 WSYY00 SOFTWARE WSYY0636510
3 SAJY00 PCB ASSY,SUB SAJY0024902 52
4 SAJB00 PCB ASSY,SUB,INSERT SAJB0012001
5 AFBA00 FRAME ASSY,SHIELD AFBA0007701 Without Color
6 MFEA00 FRAME,SHIELD MFEA0015601 MOLD, ABS MP-211, , , , , Without Color 50
6 MPBJ00 PAD,MOTOR MPBJ0045901 COMPLEX, (empty), , , , , Without Color 45
6 MPBZ00 PAD MPBZ0190001 COMPLEX, (empty), , , , , Without Color
5 MPBZ00 PAD MPBZ0187201 COMPLEX, (empty), , , , , Without Color 46
5 SMZY00 MODULE,ETC SMZY0016801 55
5 SUSY00 SPEAKER SUSY0026002
UNIT ,8 ohm,83 dB,16 mm,19.85*18.75*6.1 Module SPK
,; , , , , , , ,[empty]
4 SAJE00 PCB ASSY,SUB,SMT SAJE0019001
5 SAJC00
PCB ASSY,SUB,SMT
BOTTOM
SAJC0017301
6 CN800 CONNECTOR,ETC ENZY0015301 4 PIN,2.2 mm,ETC , ,H=2.3
6 MIC900 MICROPHONE SUMY0010507 UNIT ,42 dB,4*1.35 ,SMD
6 R907 RES,CHIP,MAKER ERHZ0000530 5.1 Kohm,1/16W ,J ,1005 ,R/TP
6 S800 CONN,SOCKET ENSY0015801 8 PIN,ETC , ,1.1 mm,H=1.9, Detect Pin
- 223 -
Level
Location
No.
6 U902 IC EUSY0250501
SC70 ,5 PIN,R/TP ,Comparator, pin compatible to
EUSY0077701
6 ZD900 DIODE,TVS EDTY0008610 SOD-523 ,5 V,250 W,R/TP ,PB-FREE
5 SAJD00 PCB ASSY,SUB,SMT TOP SAJD0019601
6 BAT900 BATTERY,CELL,LITHIUM SBCL0001701
2 V,0.5 mAh,CYLINDER ,Reflow type BB, Max T 1.67,
phi 4.8, Pb-Free
6 CN801
CONNECTOR,BOARD TO
BOARD
ENBY0029401 40 PIN,0.4 mm,ETC , ,H=3.0
6 M800 MODULE,ETC SMZY0012601 4.5x3.2x1.2 Bluetooth RF Module
6 R810 CAP,CHIP,MAKER ECZH0000830 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
6 R811 CAP,CHIP,MAKER ECZH0000830 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP
5 SPJY00 PCB,SUB SPJY0042101 FR-4 ,0.5 mm,BUILD-UP 4 , ,; , , , , , , , , ,
- 224 -
11.3 Accessory
Level
Location
No.
5 MCHZ00 COMPACT DISK MCHZ0040301 COMPLEX, (empty), , , , ,
SILVER
SNOW
3 MCJA00 COVER,BATTERY MCJA0047601 PRESS, Al, , , , , Black 85
3 MHBY00 HANDSTRAP MHBY0004310 COMPLEX, (empty), , , , , Without Color
3 MPHY00 PROTECTOR MPHY0011301 COMPLEX, (empty), 0.1, , , , Without Color
3 SBPL00 BATTERY PACK,LI-ION SBPL0091101
3.7 V,1000 mAh,1 CELL,PRISMATIC ,KU990(NYX)
BATT, Europe Label, Pb-Free ,; ,3.7 ,1000 ,0.2C
,PRISMATIC ,46x34x55 , ,BLACK ,Innerpack
,Europe(Reverse insert OK)
Black
3 SGDY00 DATA CABLE SGDY0010908
; ,[empty] ,[empty] ,[empty] ,18pin 6.2mm. NYX Box
Package ,BLACK , ,N
3 SGEY00
EAR PHONE/EAR MIKE
SET
SGEY0005546
; ,10mW ,16ohm ,111dB ,20HZ ,20HZ ,[empty] ,BLACK
,18P MMI CONNECTOR ,Plug Mold( Abnormal)
,Earphone,Stereo
3 SSAD00 ADAPTOR,AC-DC SSAD0025003
100-240V ,5060 Hz,5.1 V,.7 A,CE ,England, 18pin plug,
Nyx packing ,; , , , , , ,WALL 2P ,I/O CONNECTOR ,
Note
Note

En - ku990r Svc Eng - 080611 Не Нужные Водяные Знаки

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En - ku990r Svc Eng - 080611 Не Нужные Водяные Знаки

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Date: June, 2008 / Issue 1.

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