ECE/CS 5720/6720

Layout Assignment 2 Op-Amp Layout

In this assignment, you will draw composite layout for a CMOS op-amp with bias
generator and use LVS (Layout Vs. Schematic) to verify that your layout matches a
drawn schematic.

Enter the schematic of the op-amp and bias generator shown below:


Q
3
v
OUT
v
+
v
-
V
SS

V
DD
Q
4
Q
1
Q
2
Q
7

Q
11

Q
5
Q
6

Q
8

Q
9
Q
10
C
C
Q
12

Q
13

Q
14

Q
15
Q
16

R
BIAS



device width (m) length (m)
Q1 96 0.6
Q2 96 0.6
Q3 48 1.2
Q4 48 1.2
Q5 96 1.2
Q6 96 1.2
Q7 96 1.2
Q8 144 1.2
Q9 144 0.6
Q10 24 1.2
Q11 96 1.2
Q12 96 1.2
Q13 48 1.2
Q14 12 1.2
Q15 48 1.2
Q16 12 1.2

R
BIAS
=15 k C
C
=2.0 pF
Complete the layout of this circuit, observing the following points:

Q1 and Q2 should be drawn with common-centroid geometry. You should use
the multi-fingered gate common-centroid layout as shown below (though you may
use different numbers of fingers, and your widths and lengths will be different
than in the figure). Do not use the common-centroid technique from the book.

active
poly
G1
Q
1

15/1
M =4
Q
2

15/1
M =4
D2 D1
S
G2
D1
S
G1
S
D2
S
G2
D2
S
S
D1
G2
G1
S


Q15 should have exactly four times the width of Q16 (same with Q13 to Q14) to
ensure an accurate ratio. (See equation 5.107 in the book to see why this ratio is
important for setting an accurate bias.) You should use 4 multiple transistors in
parallel to achieve this.
Due to the finite lambda resolution in layout, you may not be able to draw the
exact widths listed above. Come as close as you can.
Use high-resistance poly2 (electrode) for R
BIAS
. Assume a resistance of 1.24 k
per square. Make the resistor no narrower than 10 (3m).
Use a poly/poly2 capacitor for C
C
. Assume a capacitance of 800 aF/m
2
.
Connect the poly2 side to Q10 so that the parasitic poly-substrate capacitance
ends up at the drain of Q6/Q7. Your capacitance should be at least 2.0 pF. (For
example, 1.999 pF is not acceptable, but 2.01 pF is acceptable.)
All pMOS devices should have their wells connected to V
DD
except for Q9, which
must be in its own well.
You must include at least one substrate tie connected to V
SS
.
If you decide to draw a multi-fingered gate for a transistor, remember to change
the width and M multiplier in your schematic. For example, W =100, M =1 can
be split into W =50, M =2, or W =25, M =4, etc.
Your complete op-amp layout must be approximately square. If your layout is not
exactly square, its area will be calculated by squaring its longest dimension
(horizontal or vertical).
Your layout must fit within a square 125 x 125 microns.
Your layout must contain zero DRC errors.
You must enable the following options in LVS verification when checking your
layout:
o Select Compare FET Parameters
o Select Compare Capacitor Parameters
o Select Compare Resistor Parameters
o De-select Ignore FET Body Terminal (All other options should be
selected.)

Turn in the following:
A printout of the circuit schematic that you drew in the Cadence Virtuoso
schematic editor.
A printout of the layout. (Zoom in so your layout occupies the entire screen.)
On this printout, label the following items by hand in ink:
o vin+, vin-, and vout (These should be metal wires connected to the
appropriate transistors.)
o R
BIAS

o C
C

o Q
1
/Q
2

o The horizontal and vertical dimensions of your op-amp layout, in
microns.
A printout of the layout, zoomed in on Q1 and Q2. With ink, mark the four
parts of the common-centroid layout as Q1a, Q1b, Q2a, and Q2b.
A printout of the LVS output file showing that the layout exactly matches the
schematic.

The five smallest layouts in 6720 and the three smallest layouts in 5720 will receive
bonus points.

We may ask to check your layout. This means we may ask you to show us your layout
passing LVS and DRC in the Cade lab. If your layout fails to pass LVS and DRC and
you have claimed otherwise in the assignment you turned in, you will receive a zero on
the assignment.