TI MSP430 Learning Materials

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Lecture 2
MSP430 Architecture
MSP430 Teaching Materials
Texas Instruments Incorporated
University of Beira Interior (PT)
Pedro Dinis Gaspar, Antnio Esprito Santo, Bruno Ribeiro, Humberto Santos
University of Beira Interior, Electromechanical Engineering Department
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Copyright 2009 Texas Instruments
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Contents (1/3)
MSP430 architecture:
Main characteristics
Architecture topology
Address space
Interrupt vector table
Central Processing Unit (MSP430 CPU)
Central Processing Unit (MSP430X CPU)
Addressing modes
Instructions set
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Contents (2/3)
Exploring the addressing modes of the MSP430
architecture:
Instruction format:
Instruction format I: Double operand
Instruction format II: Single operand
Jump instructions format
Emulated instructions
Addressing modes:
Register mode
Indexed mode
Symbolic mode
Absolute mode
Indirect register mode
Indirect auto-increment mode
Immediate mode
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Contents (3/3)
Exploring the addressing modes of the MSP430X
architecture:
Instruction format in the MSP430X CPU
Exceptions to the representation of the extended Format II
instructions
Extended emulated instructions
MSP430X address instructions
MSP430X CPU addressing modes
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Introduction
A comprehensive description of the MSP430 architecture,
covering its:
Main characteristics;
Device architecture;
Address space;
Interrupt vector table;
Central Processing Unit (MSP430 CPU and MSP430X CPU);
7 seven addressing modes and instruction set composed of:
27 base opcodes;
24 emulated instructions.
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Microcontroller characteristics
Integration: Able to implement a whole design onto a single
chip.
Cost: Are usually low-cost devices (a few $ each);
Clock frequency: Compared with other devices
(microprocessors and DSPs), MCUs use a low clock frequency:
MCUs today run up to 100 MHz/100 MIPS (Million
Instructions Per Second).
Power consumption: Low power (battery operation);
Bits: 4 bits (older devices) to 32 bits devices;
Memory: Limited available memory, usually less than 1 MByte;
Input/Output (I/O): Low to high (8 to 150) pin-out count.
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MSP430 main characteristics (1/3)
Low power consumption:
0.1 A for RAM data retention;
0.8 A for real-time clock mode operation;
250 A/MIPS during active operation.
Low operation voltage (from 1.8 V to 3.6 V);
< 1 s clock start-up;
< 50 nA port leakage;
Zero-power Brown-Out Reset (BOR).
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On-chip analogue features:
10/12/16-bit Analogue-to-Digital Converter (ADC);
12-bit dual Digital-to-Analogue Converter (DAC);
Comparator-gated timers;
Operational Amplifiers (Op Amps);
Supply Voltage Supervisor (SVS).
16 bit RISC CPU:
Compact core design reduces power consumption and cost;
16-bit data bus;
27 core instructions;
7 addressing modes;
Extensive vectored-interrupt capability.
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Flexibility:
Up to 256 kByte Flash;
Up to 100 pins;
USART, I2C, Timers;
LCD driver;
Embedded emulation;
And many more peripherals modules
Microcontroller performance:
Instruction processing on either bits, bytes or words
Reduced instructions set;
Compiler efficient;
Wide range of peripherals;
Flexible clock system.
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MSP430 Architecture
Block diagram:
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Address Space
Mapped into a single, contiguous address space:
Flash/ROM: All code, tables, and hard-coded constants
reside in this memory space.
Information memory: Variables needed for the next
power up can be stored here during power down. It can also
be used as code memory.
Boot memory: The bootstrap loader performs some of the
same functions as the JTAG interface.
RAM: RAM is used for both code and data.
Peripheral Modules: Peripheral modules consist of all on-
chip peripheral registers that are mapped into the address
space.
Special Function Registers (SFRs): Some peripheral
functions are mapped into memory with special dedicated
functions.
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Memory Map
Memory Address Description Access
End: 0FFFFh
Start: 0FFE0h
Interrupt Vector Table
Word/Byte
End: 0FFDFh

Flash/ROM
0F800h
Start *:
01100h
Word/Byte

010FFh
End *:
0107Fh Information Memory
Start: 01000h (Flash devices only)
Word/Byte
End: 0FFFh
Start: 0C00h
Boot Memory
(Flash devices only)
Word/Byte

09FFh
End *:
027Fh RAM
Start: 0200h
Word/Byte
End: 01FFh
Start: 0100h
16-bit Peripheral modules Word
End: 00FFh
Start: 0010h
8-bit Peripheral modules Byte
End: 000Fh
Start: 0000h
Special Function Registers Byte
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Interrupt vector table
Mapped at the very end of memory space (upper 16
words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);
Priority of the interrupt vector increases with the word
address.
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Central Processing Unit (MSP430 CPU) (1/7)
RISC (Reduced Instructions Set Computing) architecture:
Instructions are reduced to the basic ones (short set):
27 physical instructions;
24 emulated instructions.
This provides simpler and faster instruction decoding;
Interconnect by a using a common memory address bus
(MAB) and memory data bus (MDB) - Von Neumann
architecture:
Makes use of only one storage structure for data and
instructions sets.
The separation of the storage processing unit is implicit;
Instructions are treated as data (programmable).
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RISC (Reduced Instructions Set Computing) type
architecture:
Uses a 3-stage instruction pipeline containing:
Instruction decoding;
16 bit ALU;
4 dedicated-use registers;
12 working registers.
Address bus has 16 bit so it can address 64 kB (including
RAM + Flash + Registers);
Arithmetic Logic Unit (ALU):
Addition, subtraction, comparison and logical (AND, OR,
XOR) operations;
Operations can affect the overflow, zero, negative, and carry
flags of the SR (Status Register).
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Incorporates sixteen 16-bit registers:
4 registers (R0, R1, R2 and R3) have dedicated functions;
12 register are working registers (R4 to R15) for general
use.
R0: Program Counter (PC):
Points to the next instruction to be read from memory and
executed by the CPU.
R1: Stack Pointer (SP):
1st: stack can be used by user to store data for later use
(instructions: store by PUSH, retrieve by POP);
2nd: stack can be used by user or by compiler for subroutine
parameters (PUSH, POP in calling routine; addressed via offset
calculation on stack pointer (SP) in called subroutine);
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R1: Stack Pointer (SP) (continued):
3rd: used by subroutine calls to store the program counter
value for return at subroutine's end (RET);
4th: used by interrupt - system stores the actual PC value
first, then the actual status register content (on top of stack)
on return from interrupt (RETI) the system get the same
status as just before the interrupt happened (as long as none
has changed the value on TOS) and the same program
counter value from stack.
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R2: Status Register (SR):
Stores status and control bits;
System flags are changed automatically by the CPU;
Reserved bits are used to support the constant generator.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C
Bit Description
8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.
7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK
6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK
4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.
3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.
2 N Negative flag. N = 1 result of a byte or word operation is negative.
1 Z Zero flag. Z = 1 result of a byte or word operation is 0.
0 C Carry flag. C = 1 result of a byte or word operation produced a carry.
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R2/R3: Constant Generator Registers (CG1/CG2):
Depending of the source-register addressing modes (As)
value, six constants can be generated without code word or
code memory access to retrieve them.
This is a very powerful feature which allows the
implementation of emulated instructions, for example,
instead of implement a core instruction for an increment the
constant generator is used.
Register As Constant Remarks
R2
00
-
Register mode
R2
01
(0)
Absolute mode
R2 10 00004h +4, bit processing
R2
11
00008h
+8, bit processing
R3
00
00000h
0, word processing
R3 01 00001h +1
R3 11 0FFFFh -1, word processing
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R4 - R15: GeneralPurpose Registers:
These general-purpose registers are adequate to store data
registers, address pointers, or index values and can be
accessed with byte or word instructions.
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(1/10)
Main features of the MSP430X CPU architecture:
The MSP430X CPU extends the addressing capabilities of the
MSP430 family beyond 64 kB to 1 MB;
To achieve this, some changes have been made to the
addressing modes and two new types of instructions have
been added;
One instruction type allows access to the entire address
space, and the other is designed for address calculations;
The MSP430X CPU address bus has 20 bits, although the
data bus still has 16 bits. Memory accesses to 8-bit, 16-bit
and 20-bit data are supported;
Despite these changes, the MSP430X CPU remains
compatible with the MSP430 CPU, having a similar number
of registers.
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Organization of the MSP430X CPU:
Although the MSP430X CPU structure is
similar to that of the MSP430 CPU, there
are some differences that will now be
highlighted;
With the exception of the status register
SR, all MSP430X registers are 20 bits;
The CPU can now process 20-bit or 16-
bit data.
(2/10)
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(3/10)
The MSP430X CPU has 16 registers, some of which have
special use:
R0 (PC) Program Counter:
Has the same function as the MSP430 CPU, although now it
has 20 bits.
R1 (SP) Stack Pointer:
Has the same function as the MSP430 CPU, although now it
has 20 bits.
R2 (SR) Status Register:
Has the same function as the MSP430 CPU, but it still has 16
bits.
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(4/10)
R2 (SR) Status Register:
Description of the SR bits:
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(5/10)
R2 (SR/CG1) and R3 (CG2) Constant Generators:
Registers R2 and R3 can be used to generate six different
constants commonly used in programming, without adding
an additional 16-bit word to the instruction;
The constants are fixed and are selected by the (As) bits of
the instruction. (As) selects the addressing mode.
Values of constants
generated:
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R2 (SR/CG1) and R3 (CG2) Constant Generators:
Whenever the operand is one of the six constants, the
registers are selected automatically;
Therefore, when used in constant mode, registers R2 and R3
cannot be used as source registers.
R4-R15 General-purpose registers:
Have the same function as in the MSP430 CPU, although
they now have 20 bits;
These registers can process 8-bit, 16-bit or 20-bit data;
If a byte is written to one of these registers it takes bits 7:0,
the bits 19:8 are filled with zeroes. If a word is written to
one of these registers it takes bits 15:0, the bits 19:16 are
filled with zeroes.
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(7/10)
Handling byte data (8 bits) using the suffix . B:
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(8/10)
Handling word data (16 bits) using the suffix . W:
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Manipulation of a 20-bit address using the suffix . A:
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Addressing modes
7 addressing modes for the source operand:
4 addressing modes for the destination operand:
Register mode; Indexed mode; Symbolic mode; Absolute
mode.
For the destination operand, two additional addressing
modes can be emulated.
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Instruction set
27 core instructions;
24 emulated instructions;
The instruction set is orthogonal;
The core instructions have unique opcodes decoded by
the CPU, while the emulated ones need assemblers and
compilers for their mnemonics;
There are three core-instruction formats:
Double operand;
Single operand;
Program flow control - Jump.
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Exploring the addressing modes of the
MSP430 architecture (1/11)
The MSP430 architecture:
The MSP430 CPU incorporates features specifically designed
to allow the use of modern programming techniques, such
as:
The computation of jump addresses;
Data processing in tables;
The use of high-level languages such as C.
The whole memory space can be addressed by the MSP430
CPU, without needing paging, using seven different
addressing modes.
The MSP430 CPU has a set of 27 instructions that can be
used with any of the addressing modes.
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Organization of the MSP430 CPU:
16-bit address bus (MAB) and 16-bit
data bus (MDB).
Both registers and memory can be
accessed either in word format or in byte
format.
Allows the direct transfer of data
between memory, without passing
through the registers.
The 16-bit registers can be accessed
directly through the instructions, some
of which run in a single clock cycle.
Some of the constants most used in
programming can be obtained from the
constant generator.

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Organization of the MSP430 CPU
(continued):
The architecture has a 16 bit Arithmetic
Logic Unit (ALU).
Carrying out operations affects the state
of the following flags:
Zero (Z);
Carry (C);
Overflow (V);
Negative (N).
The MCLK (Master) clock signal drives
the CPU.

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The MSP430 CPU has 16 registers, some of which are
dedicated to special use:
R0 (PC) (Program Counter):
This register always points to the next instruction to be
fetched;
Each instruction occupies an even number of bytes.
Therefore, the least significant bit (LSB) of the PC register is
always zero;
After fetch of an instruction, the PC register is incremented
to point to the next instruction.
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R1 (SP) Stack Pointer:
This register is used by the MSP430 CPU to store the return
address of routines or interrupts;
Each time the data stack is accessed, the SP is incremented
or decremented automatically;
The user should be careful to initialise the SP register with
the valid address of the data stack in RAM;
The stack pointer SP always points to an even address, so
its LSB is always zero.
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R2 SR/CG1 & R3 CG2 (Status Register):
The status of the MSP430 CPU is defined by a set of bits
contained in register R2 (SR) (status register);
This register can only be accessed through register
addressing mode;
All other addressing modes are reserved to support the
constants generator;
The organization of the individual bits of register R2 is
shown in the following figure:
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R2 SR/CG1 & R3 CG2 (Status Register):
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C
Bit Description
8 V Overflow bit.
V = 1 Result of an arithmetic operation overflows the signed-variable range.
7 SCG1 System clock generator 1.
SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK
6 SCG0 System clock generator 0.
SCG0 = 1 FLL+ loop control is turned off
5 OSCOFF Oscillator Off.
OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK
4 CPUOFF CPU off.
CPUOFF = 1 disable CPU core.
3 GIE General Interrupt Enable.
GIE = 1 enables maskable interrupts.
2 N Negative flag.
N = 1 result of a byte or word operation is negative.
1 Z Zero flag.
Z = 1 result of a byte or word operation is 0.
0 C Carry flag.
C = 1 result of a byte or word operation produced a carry.
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R2 SR/CG1 & R3 CG2 (Constant Generators):
Six different constants commonly used in programming can
be generated using the registers R2 and R3, without the
need to add a 16-bit word of code to the instruction;
The constants are fixed and are selected by the instruction
bits (As). These control the addressing mode.
Register As Constant Remarks
R2 00 - Register mode
R2 01 (0) Absolute mode
R3 00 00000h 0, word processing
R3 01 00001h +1
R3 11 0FFFFh -1, word processing
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R4-R15: General-purpose registers:
The general purpose registers R4 to
R15 can be used as data registers,
data pointers and indices. They can
be accessed either as a byte or as a
word;
These registers support operations
on words or bytes;
In the example to the right, the
contents of the least significant byte
of register R5 (0x8F) is added to the
contents of the memory address
pointed to by the register R6 (0x12h);

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The contents of the memory address
is updated with the result of the
operation (0xA1);
The status flags of the CPU in the SR
are updated after the execution of
the instruction.

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The contents of the memory address
pointed to by R6 (0x5F) is added to
the contents of the least significant
byte of register R5 (0x02);
The result of the operation (0x61) is
stored in the least significant byte of
register R5;
Meanwhile, the most significant byte
of register R5 is set to zero;
The system flags in SR are updated
in accordance with the result.

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Instructions format (1/4)
In addition to the 27 instructions of the CPU there are 24
emulated instructions;
The CPU coding is unique;
The emulated instructions make reading and writing
code more easy, but do not have their own op-codes;
Emulated instructions are replaced automatically by
instructions from the CPU;
There are no penalties for using emulated instructions.
There are three formats used to encode instructions for
processing by the CPU core:
Double operand;
Single operand;
Jumps.
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The instructions for double and single operands, depend
on the suffix used, (. W) word or (. B) byte.
These suffixes allow word or byte data access;
If the suffix is ignored, the instruction processes word
data by default.
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The source and destination of the data operated by an
instruction are defined by the following fields:
src: source operand address, as defined in As and S-reg;
dst: destination operand address, as defined in Ad and D-reg;
As: addressing bits used to define the addressing mode used
by the source operand;
S-reg: register used by the source operand;
Ad: Addressing bits used to define the addressing mode used
by the destination operand;
D-reg: register used by the destination operand;
B/W: word or byte access definition bit.
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While all addresses within the address space are valid, it
is the responsibility of the user to check that the type of
access is valid.
Example: the contents of the flash memory can be used
as a source operand, but can only be written to in certain
conditions.
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Instruction format I: Double operand
Organization of instructions with two operands:
Double operand instructions:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-code S-Reg Ad B/W As D-Reg
Mnemonic Operation Description
Arithmetic instructions
ADD( . B or . W) sr c, dst src+dstdst Add source to destination
ADDC( . B or . W) sr c, dst src+dst+Cdst Add source and carry to destination
DADD( . B or . W) sr c, dst src+dst+Cdst (dec) Decimal add source and carry to destination
SUB( . B or . W) sr c, dst dst+.not.src+1dst Subtract source from destination
SUBC( . B or . W) sr c, dst dst+.not.src+Cdst Subtract source and not carry from destination
Logical and register control instructions
AND( . B or . W) sr c, dst src.and.dstdst AND source with destination
BI C( . B or . W) sr c, dst .not.src.and.dstdst Clear bits in destination
BI S( . B or . W) sr c, dst src.or.dstdst Set bits in destination
BI T( . B or . W) sr c, dst src.and.dst Test bits in destination
XOR( . B or . W) sr c, dst src.xor.dstdst XOR source with destination
Data instructions
CMP( . B or . W) sr c, dst dst-src Compare source to destination
MOV( . B or . W) sr c, dst srcdst Move source to destination
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Examples: double operand (1/3)
Move the contents of register R5 to register R4:
MOV R5, R4
Instruction code: 0x4504
This instruction uses 1 word;
The instruction coding specifies that the CPU must perform a
16-bit data MOV instruction, with the contents of register R5
as the source and with register R4 as the destination.
Op-code S-reg Ad B/W As D-reg
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
MOV R5 Register 16-Bits Register R4
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Move the contents of register R5 to the address in
memory TONI:
MOV R5, TONI
This instruction uses 2 words;
16-bit data MOV instruction using the contents of register R5
to the memory address pointed to by X1 + PC;
The word X1 is stored in the word following the instruction.
0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0
MOV R5 Symbolic 16 Bits Register PC
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Move the contents between the memory addresses EDEN
and TONI:
MOV EDEN, TONI
16-bit data MOV instruction using the contents of the EDEN
memory address pointed to by X1 + PC to the TONI memory
address pointed to by X2 + PC;
The word X1 followed by the word X2 are stored after the
instruction.
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
MOV PC Symbolic 16-Bits Symbolic PC
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Instruction format II: Single operand
The instructions with one operand are coded using the
following structure:
Single operand instructions:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-code B/W Ad D/S-Reg
Mnemonic Operation Description
RRA( . B or . W) dst
MSBMSBLSBC Roll destination right
RRC( . B or . W) dst
CMSBLSBC Roll destination right through (from) carry
SWPB( or . W) dst
Swap bytes Swap bytes in destination
SXT dst
bit 7bit 8bit 15 Sign extend destination
PUSH( . B or . W) sr c
SP-2SP, src@SP Push source on stack
Program flow control instructions
CALL( . B or . W) dst
SP-2SP, PC+2@SP
dstPC
Subroutine call to destination
RETI
TOSSR, SP+2SP
TOSPC, SP+2SP
Return from interrupt
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Examples: single operand (1/2)
Move the contents of register R5 to the right with carry
flag:
RRC R5
16-bit data RRC instruction using the contents of register R5.
Op-code B/W Ad D-reg
0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1
RRC 16 bits Register R5
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Examples: single operand (2/2)
Rotate the contents of memory TONI to the right with
carry flag:
RRC TONI
16-bit data RRC instruction pointed to by X1 + PC;
Word X1 is stored in the word following the instruction.
Op-code B/W Ad D-reg
0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0
RRC 16 bits Symbolic PC
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Jump instructions format (1/3)
These instructions are used to direct program flow to
another part of the program.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Op-code C 10 bit PC offset
Mnemonic Description
Program flow control instructions
JEQ/JZ label Jump to label if zero flag is set
JNE/JNZ label Jump to label if zero flag is reset
JC label Jump to label if carry flag is set
JNC label Jump to label if carry flag is reset
JN label Jump to label if negative flag is set
JGE label Jump to label if greater than or equal
JL label Jump to label if less than
JMP label Jump to label unconditionally
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The op-code always takes the value 001b, indicating that
it is a jump instruction;
The condition on which a jump occurs depends on the C
field consisting of 3 bits, and may take the following
values:
000b: jump if not equal;
001b: jump if equal;
010b: jump if carry flag equal to zero;
011b: jump if carry flag equal to one;
100b: jump if negative (N = 1);
101b: jump if greater than or equal (N=V or (N OR V=0));
110b: jump if lower (N! = V or (V XOR N = 1));
111b: unconditional jump.
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The jumps are executed based on the PC contents, are
controlled by the status bits, but do not affect the status
bits;
The jump off-set is represented by a signed 10-bit value:
The range of the jump can be between -511 to +512
words, in relation to the PC position.
2 2
offset old new
PC PC PC
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Examples: jump format (1/2)
Continue execution at the label mai n if the carry flag is
active:
J C mai n
Instruction code: 0x2FE4
The instruction coding specifies that the PC must be loaded
with the value resulting from the offset - 0x1C being applied
to the previous expression.
Op-code C 10-Bit PC offset
0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0
JC Carry = 1 0x1C
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Examples: jump format (2/2)
Continue to unconditionally execute code at the label
mai n:
J MP mai n
Instruction code: 0x3FE3
The instruction coding specifies that the PC must be loaded
with the value resulting from the offset - 0x1D being applied
to the previous expression.
Op-code C 10-Bit PC offset
0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1
JMP unconditional 0x1D
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Emulated instructions (1/3)
In addition to the 27 CPU instructions, the following 24
emulated instructions can also be used:
Mnemonic Operation Emulation Description
Arithmetic instructions
ADC(.B or .W) dst dst+Cdst ADDC(.B or .W) #0,dst Add carry to destination
DADC(.B or .W) dst dst+Cdst (decimally) DADD(.B or .W) #0,dst Decimal add carry to
destination
DEC(.B or .W) dst dst-1dst SUB(.B or .W) #1,dst Decrement destination
DECD(.B or .W) dst dst-2dst SUB(.B or .W) #2,dst Decrement destination twice
INC(.B or .W) dst dst+1dst ADD(.B or .W) #1,dst Increment destination
INCD(.B or .W) dst dst+2dst ADD(.B or .W) #2,dst Increment destination twice
SBC(.B or .W) dst dst+0FFFFh+Cdst
dst+0FFhdst
SUBC(.B or .W) #0,dst Subtract source and borrow
/.NOT. carry from dest.
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emulated instructions can also be used (continued):
INV(.B or .W) dst .NOT.dstdst XOR(.B or .W) #0(FF)FFh,dst Invert bits in destination
RLA(.B or .W) dst CMSBMSB-
1LSB+1LSB0
ADD(.B or .W) dst,dst Rotate left arithmetically
RLC(.B or .W) dst CMSBMSB-
1LSB+1LSBC
ADDC(.B or .W) dst,dst Rotate left through carry
Program flow control
BR dst dstPC MOV dst,PC Branch to destination
DINT 0GIE BIC #8,SR Disable (general)
interrupts
EINT 1GIE BIS #8,SR Enable (general) interrupts
NOP None MOV #0,R3 No operation
RET @SPPC
SP+2SP
MOV @SP+,PC Return from subroutine
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emulated instructions can also be used (continued):
Data instructions
CLR(.B or .W) dst 0dst MOV(.B or .W) #0,dst Clear destination
CLRC 0C BIC #1,SR Clear carry flag
CLRN 0N BIC #4,SR Clear negative flag
CLRZ 0Z BIC #2,SR Clear zero flag
POP(.B or .W) dst @SPtemp
SP+2SP
tempdst
MOV(.B or .W) @SP+,dst Pop byte/word from stack
to destination
SETC 1C BIS #1,SR Set carry flag
SETN 1N BIS #4,SR Set negative flag
SETZ 1Z BIS #2,SR Set zero flag
TST(.B or .W) dst dst + 0FFFFh + 1
dst + 0FFh + 1
CMP(.B or .W) #0,dst Test destination
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Examples: Emulated instructions (1/6)
Clear the contents of register R5:
CLR R5
This instruction is equivalent to using MOV R3, R5 where R3
takes the value #0.
0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1
MOV R3 Register 16 Bits Register R5
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Increment the content of register R5:
I NC R5
This instruction is equivalent to having ADD 0( R3) , R5 where
R3 takes the value #1.
0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1
ADD R3 Register 16 Bits Indexed R5
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Decrement the contents of register R5:
DEC R5
This instruction is equivalent to using SUB 0( R3) , R5 where
R3 takes the value #1.
1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1
SUB R3 Register 16 Bits Indexed R5
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Decrement by two the contents of register R5:
DECD R5
This instruction is equivalent to using SUB @R3, R5 where R3
points to the value #2.
1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1
SUB R3 Register 16 Bits Indirect R5
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Do not carry out any operation:
NOP
This instruction is equivalent to using MOV R3, R3 and
therefore the contents of R3 are moved to itself.
0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1
MOV R3 Register 16 Bits Register R3
UBI
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Add the carry flag to the register R5:
ADC R5
This instruction is equivalent to using ADDC R3, R5 where R3
takes the value #0.
0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1
ADDC R3 Register 16 Bits Register R5
UBI
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Addressing modes (1/2)
There are seven addressing modes that take a source
operand and four of these addressing modes also take a
destination operand;
The operands can be located in any memory space
address, but the user needs to be aware of the effects
that their accesses may have;
The addressing modes are selected by the As and Ad
fields that make up the instruction;
The following table summarizes the seven addressing
modes:
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Addressing modes (2/2)
Operands (single-operand instructions)
Source operands (double-operand instructions) Destination operands (double-operand instructions)
Addressing mode As S-reg Addressing mode Ad D-reg
Register mode 0 0 0 0 0 0 to 1 1 1 1 Register mode 0 0 0 0 0 to 1 1 1 1
Indexed mode 0 1 0 0 0 1, 0 0 1 1 to 1 1 1 1 Indexed mode 1 0 0 0 1, 0 0 1 1 to 1 1 1 1
Symbolic mode 0 1 0 0 0 0 Symbolic mode 1 0 0 0 0
Absolute mode 0 1 0 0 1 0 Absolute mode 1 0 0 1 0
Indirect register
mode
1 0 0 0 0 0 to 1 1 1 1
Indirect auto
increment mode
1 1 0 0 0 1 to 1 1 1 1
Immediate mode 1 1 0 0 0 0
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Register mode (1/3)
In Register addressing mode, the contents of a register
is used as the operand;
This type of addressing mode can be used both with
source and destination operands.
MOV R5,R4
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
MOV R5 Register 16-bit Register R4
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Register mode (2/3)
Move the contents of register R5 to register R4
MOV R5,R4
The 16-bit contents (B/ W= 0) of register R5 (S-reg) are
transferred to the register R4 (D-reg);
After the instruction fetch, the PC is incremented by 2 and
points to the next instruction to be executed;
The addressing mode used for the source and destination
operands is determined by As = 00 (Register mode) and
Ad = 0 (Register mode), respectively.
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
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Register mode (3/3)
Move the contents of register R5 to register R4 (cont.):
MOV R5,R4
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
UBI
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Indexed mode (1/4)
In indexed mode, whether used to indicate the source
address or the destination address, the sum of the
register contents and the signed offset point to the
location in memory;
The offset value is stored in the word following the
instruction;
After the execution of the instruction, the contents of
registers are not affected and the PC is incremented to
point to the next instruction to be executed;
This addressing mode is useful to access data stored in
tables. Apart from the registers PC and SR, all other
registers can be used as an index in indexed mode.
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Indexed mode (2/4)
Move the byte pointed to by (R5 + 4) to the byte pointed
to by (R4 + 1):
MOV.B 4(R5),1(R4)
Instruction code: 0x45D4
The instruction coding specifies that the byte (B/ W= 1)
pointed to by the sum of the contents of register R5
(S- r eg = 0101) and the word X1 should be moved to the
memory address pointed to by the sum of register R4
(D- r eg = 0100) and the contents of the word X2;
0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 0
MOV R5 Indexed 8-bit Indexed R4
UBI
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Indexed mode (3/4)
to by (R4 + 1) (continued):
MOV.B 4(R5),1(R4)
Instruction code: 0x45D4
The words X1 and X2 are located in the memory addresses
following the instruction;
operands is controlled by the bits Ad = 1 (Indexed mode)
and As = 01 (Indexed mode), because (D- r eg = 0100) and
(S- r eg = 0101) respectively.
0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 0
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Indexed mode (4/4)
to by (R4 + 1) (continued):
MOV.B 4(R5),1(R4)
UBI
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Symbolic mode (1/5)
In symbolic addressing mode, for either the source or
destination operands, the memory address is determined
by adding an offset to the program counter (PC) register;
The offset value is obtained by determining the code
position in the memory, then calculating the difference
between the offset address and the memory position that
should be achieved;
The assembler determines the offset value and puts it in
the word following to the instruction;
After the execution of the instruction, the program
counter (PC) register is incremented in order to point to
the next instruction.
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Symbolic mode (2/5)
Although this mode of address is similar to register mode
it request more cycles, but in this case, the program
counter (PC) is used to point to the data;
This addressing mode can be used to determine either
the source or the destination of the data.
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Symbolic mode (3/5)
Move the word pointed to by EDEN to the word pointed to
by TONI:
MOV EDEN,TONI
The instruction coding specifies that the value pointed to by
the sum of the PC register contents (S- r eg = 0) and the
word X1 should be moved to the memory address pointed to
by the sum of register PC contents (D- r eg = 0) and the
word X2;
The words X1 and X2 are stored in the memory addresses
following the instruction.
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
MOV PC Symbolic 16-bit Symbolic PC
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Symbolic mode (4/5)
by TONI (continued):
MOV EDEN,TONI
operands is controlled by the bits Ad = 1 (Symbolic mode)
and As = 01 (Symbolic mode) because (D- r eg = 0000) and
(S- r eg = 0000), respectively.
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
UBI
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Symbolic mode (5/5)
by TONI:
MOV EDEN,TONI
UBI
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Absolute mode (1/4)
In Absolute mode, the data memory address is placed
after the instruction;
The difference between this addressing mode and
Indexed mode is that the register R2 is now used as an
index, using the constants generator to generate the
value zero;
This addressing mode can be used to define either the
source address or the destination address.
UBI
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Absolute mode (2/4)
by TONI:
MOV &EDEN,&TONI
From the instruction coding it can be seen that the register
R2 has (S- r eg = 0010) and (D- r eg = 0010). Register R2 is
used as an addresses index, in which the constant generator
loads the value zero;
When the contents of this register is added to the offset
value X1 or X2, the source and destination addresses are
obtained;
following the instruction.
0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0
MOV R2/CG1 Absolute 16-bit Absolute R2/CG1
UBI
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Absolute mode (3/4)
MOV &EDEN,&TONI
operands is specified by the bits Ad = 1 (Absolute mode)
and As = 01 (Absolute mode) because (D- r eg = 0010) and
(S- r eg = 0010), respectively.
0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0
MOV R2/CG1 Absolute 16-bit Absolute R2/CG1
UBI
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Absolute mode (4/4)
MOV &EDEN,&TONI
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Indirect register mode (1/3)
In Indirect register mode, any of the 16 CPU registers
can be used. If R2 or R3 are used then a constant value
is used as an operand, #0x04 for R2 and #0x02 for R3;
A restriction arises from the fact that this addressing
mode can only be used to specify the source operand
address in dual-operand instructions;
An alternative way to avoid this restriction is to use
indexed mode to specify the destination operand address,
with a zero offset.
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Move the word pointed to by R5 to the word pointed to by
R4:
MOV @R5,0(R4)
Instruction code: 0x45A4
The instruction coding specifies that register R5
(S- r eg = 0101) uses the source address (As = 10);
The destination address is pointed to in Indexed mode
(Ad = 1) by R4 (D- r eg = 0100), using a zero value offset.
0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0
MOV R5 Indexed 16-bit Indirect R4
UBI
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Move the word pointed to by R5 to the word pointed to
by R4 (continued):
MOV @R5,0(R4)
UBI
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Indirect auto-increment mode (1/3)
This addressing mode is similar to the previous one;
The contents of source register is incremented according
to the data type processed;
If the data value is byte, the source register is
incremented by 1;
If the data value is a word, the source register is
incremented by 2;
Note that this addressing mode can only be used to
specify the source operand in dual-operand instructions.
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by R4, and increment the source pointer:
MOV @R5+,0(R4)
Instruction code: 0x45B4
The instruction coding specifies that the register R5
(S- r eg = 0101) contains the source address (As = 11);
The destination address is pointed to in indexed mode by R4
(D- r eg = 0100), using a zero value offset;
The execution of the instruction increments the contents of
register R5 by 2.
0 1 0 0 0 1 0 1 1 0 1 1 0 1 0 0
MOV R5 Indexed 16-bit Ind. aut. inc. R4
UBI
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by R4, and increment the source pointer (continued):
MOV @R5+,0(R4)
UBI
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Immediate mode (1/2)
The Immediate addressing mode allows values to be
loaded directly into registers or memory addresses. It
can only be used with source operands.
Move the value 0x0200 to R5:
MOV #0x0200,R5
The instruction coding specifies that the register PC
(S- r eg = 0000) is used to define the address of the word in
memory that loads the register R5 (D- r eg = 0101)
with (As = 11).
0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1
MOV PC Register 16-bit Immediate R5
UBI
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Immediate mode (2/2)
Move the value 0x0200 to R5 (continued):
MOV 0x0200,R5
UBI
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Instruction format in the MSP430X CPU
(1/2)
There are three possibilities to choose between the
instructions of the MSP430 CPU and MSP430X CPU:
Use only the MSP430 CPU instructions. The following
rules must be followed, with the exception of the
instructions CALLA/RETA, BRA:
Put all the data in memory below 64 kB and access
the data using 16-bit pointers;
Place the routines at an address within the range
PC 32 kB;
No 20-bits data.
Use only the MSP430X CPU instructions. This causes a
reduction in the application execution speed and an
increase in the memory space occupied by the program;
Use an appropriate selection of the instruction types.
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Instruction format in the MSP430X CPU (2/2)
The MSP430X CPU supports all functions of the MSP430
CPU;
It also offers a set of instructions that provide full access
to the 20-bit addressing space;
An additional op-code word is added to some of the
instructions. Therefore all addresses, indexes and
immediate numbers have 20 bits.
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Extension word for register addressing
mode (1/2)
In register mode, the
extension word of an
instruction of format type I
(two operands) or format
type II (single operand) is
coded as:
The description of each field:
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Extension word for register addressing
mode (1/2)
Unlike the MSP430, the MSP430X CPU supports the
repeated execution of the same instruction, provided
that the operands are of the register type;
The repetition is set by placing the repeat RPT instruction
before the instruction to be executed;
The assembler incorporates information in the extension
word in the fields # (bit 7) and in the repetition counter
(bits 3:0);
An example of this feature will be provided later.
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Extension word for the other addressing
modes
In a non-register
addressing mode, the
extension word of an
instruction, whether
format I (double
operands) or format II
(single operand), is
coded as:
The description of each
field:
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Extended format I -Double operand-
instructions
There are twelve extended instructions that use two
operands:
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Examples: Extended double operand
instructions (1/7)
MOVX R5,R4
Instruction code: 0x1840 0x4504
The instruction coding specifies that the CPU must perform
the 16-bit data function MOVX, using the contents of the
source register R5 and the destination register R4.
0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn
0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0
MOVX R5 Register 16-bit Register R4
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instructions (2/7)
Move the contents of the register R5 to the memory
address TONI:
MOVX R5,TONI
Instruction code: 0x184F 0x4580
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1
0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0
MOVX R5 Symbolic 16-bits Register PC
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instructions (3/7)
Move the contents of the register R5 to the memory
address TONI (continued):
MOVX R5,TONI
the 16-bit data function MOVX, the source being the contents
of register R5 and the destination being the memory address
pointed to by (dst 19: 16: X1 + PC);
The bits dst 19: 16 is stored in the extension word and the
value X1 is stored in the word following.
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1
0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0
MOVX R5 Symbolic 16-bits Register PC
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instructions (4/7)
Move the contents of the memory address TONI to
register R5:
MOVX TONI,R5
Instruction code: 0x1FC0 0x4015
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1
MOVX PC Register 16-bit Symbolic R5
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instructions (5/7)
Move the contents of the memory address TONI to
register R5 (continued):
MOVX TONI,R5
The coding specifies that the CPU must perform the 16-bit
data function MOVX, the source being the contents of memory
address pointed to by (sr c 19: 16: X1 + PC) and the
destination being register R5;
The bits dst 19: 16 are stored in the extension word and the
value X1 is stored in the word following.
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1
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instructions (6/7)
Move the contents of the memory address TONI to the
memory address EDEN:
MOVX TONI,EDEN
Instruction code: 0x1FCF 0x4090
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
MOVX PC Symbolic 16-Bit Symbolic PC
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instructions (7/7)
Move the contents of the memory address TONI to the
address memory EDEN:
MOVX TONI,EDEN
The coding specifies that the CPU must perform the 16-bit
data function MOVX, the source being the contents of the
memory address pointed to by (sr c 19: 16: X1 + PC) and
the destination being the contents of the memory address
The bits sr c 19: 16 and dst 19: 16 are stored in the
extension word and the words X1 and X2 are stored in the
words following.
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
MOVX PC Symbolic 16-Bit Symbolic PC
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Extended format II - single operand-
instructions (1/2)
Extended instructions using format II are:
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Extended format II - single operand-
instructions (2/2)
The MSP430X CPU has some additional capabilities in
addition to those of the MSP430 CPU:
The ability to push/pop several registers on/off the data
stack using only a single instruction;
The ability to rotate the contents of a register several times
during the execution of a single instruction.
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Examples: Extended single operand
instructions (1/4)
Rotate right the 20-bit contents of register R5 with the
carry flag:
RRCX.A R5
The coding specifies that the CPU must perform the function
RRCX using the 20-bit data contents of register R5.
0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
Op-code B/W Ad D/S-reg
0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1
RRCX 20-bit Register R5
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instructions (2/4)
Rotate right the 20-bit contents of the memory address
TONI with carry flag:
RRCX.A TONI
RRCX using the 20-bit data contents of the memory address
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0
RRCX 20-bit Symbolic PC
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instructions (3/4)
TONI with carry flag (continued):
RRCX.A TONI
The bits dst 19: 16 are stored in the extension word and the
value X1 is stored in the word following;
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0
RRCX 20-bit Symbolic PC
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instructions (4/4)
TONI with carry flag (continued):
RRCX.A TONI
Because the instruction operand is located in memory rather
than in a CPU register, two words are used to store the
operand. The format is shown in the figure below:
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Exceptions to the representation of the
extended Format II instructions (1/7)
Store the 20-bit registers R10, R9, R8:
PUSHM.A #3,R10
The instructions PUSHMand POPMare coded according to the
structure given in the figure below:
Instruction code: 0x142A
PUSHMof the 20-bit registers R10 to R8.
Op-code n - 1 D-reg
0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0
PUSHM.A #3 R10
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Rotate right three times the contents of the 20-bit register
R5 with the carry flag:
RRCM.A #3,R5
The instructions RRCM, RRAM, RRUMand RLAMare coded
according to the structure given in the figure below:
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Rotate right three times the content of the 20-bit register
R5 with the carry flag (continued):
RRCM.A #3,R5
RRCMusing the contents of the 20-bit register R5 a total of 3
times.
C n-1 Op-code R-reg
0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1
#3 RRCM R5
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Perform a branch in the program flow:
BRA R5
This type of instruction can be coded in three different
formats, as shown in the figure below:
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Perform a branch in the program flow (continued):
BRA R5
Instruction code: 0x05C0
The coding specifies that the PC must be loaded with the
value in register R5.
C R-reg Op-code 0(PC)
0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0
R5 BRA PC
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Call a routine:
CALLA R5
This type of instruction can be coded in three different
formats, as shown in the figure below:
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Call a routine (continued):
CALLA R5
The coding specifies that the PC must be loaded with the
value in register R5;
The execution of this instruction saves the PC on the data
stack, so the function can return at the end of execution of
the routine.
Op-code D-reg
0 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1
CALLA R5
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Extended emulated instructions
The constant generator provide a set of extended
emulated instructions, as shown in the following table:
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MSP430X address instructions
Address instructions support 20-bit operands, but they
have restrictions on the addressing modes they can use;
List of extended address instructions:
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MSP430X CPU addressing modes
As with the MSP430 CPU, the MSP430X CPU supports
seven addressing modes for the source operand and four
addressing modes for the destination operand;
Both the MSP430 CPU and MSP430X CPU instructions can
be used throughout the 1 MB address space;
In the following sections we will explore the different
addressing modes available to the MSP430X CPU.
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Register mode (1/3)
This addressing mode is identical to that of the MSP430
CPU;
There are three different types of access to the registers:
8-bit access (Byte operation);
16-bit access (Word operation);
20-bit access (Address-word).
The instruction SXT is the only exception, as the sign of
the value is extended to the other bits of the register.
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Register mode (2/3)
Move the 20-bit contents of register R5 to register R4:
MOVX. A R5, R4
The instruction uses 2 words.
The 20-bit contents (B/ W= 1 and A/ L = 0) of register R5
(S- r eg = 0101) is transferred to register R4
(D- r eg = 0100);
0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 1 0 1 0 1 0 0 0 1 0 0
MOVX R5 Register 20-bit Register R4
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Register mode (3/3)
Move the 20-bit contents of register R5 to register R4
(continued):
MOVX. A R5, R4
After the execution of the instruction, the PC is incremented
by 4 and pointed to the next instruction;
operands is specified by Ad = 0 (Register mode) and
As = 00 (Register mode).

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Indexed mode
Indexed mode can be used in three different situations:
Indexed mode in the memory address space below 64 kB;
Indexed mode in the memory address space above 64 kB;
Indexed mode using a MSP430X CPU instruction.
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Indexed mode: below 64 kB (1/4)
Indexed mode in the memory address space below 64 kB:
If the CPU register Rn points to a memory address located
below 64 kB, the address resulting from the sum of the index
and the register Rn has the value zero in bits 19:16.
This ensures that the address is always located in memory
below 64 kB.
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Move the word pointed to by (R5 0x30) to the word
pointed to by (R4 + 2):
MOV 0XFFD0( R5) , 2( R4)
The instruction coding specifies that the word (B/ W= 0)
pointed to by the sum of register R5 contents (S- r eg = 0101)
and the word X1 should be moved to the memory address
pointed to by the sum of the register R4 contents
(D- r eg = 0100) and the word X2;
0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 0
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pointed to by (R4 + 2) (continued):
MOV 0XFFD0( R5) , 2( R4)
The words X1 and X2 are located in the memory addresses
operands is specified by the bits Ad = 1 (Indexed mode) and
As = 01 (Indexed mode), because D- r eg = 0100 and
S- r eg = 0101 respectively;
In this example, bits 19:16 are set to zero when the operand
addresses are calculated.
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MOV 0XFFD0( R5) , 2( R4)
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Indexed mode: above 64 kB (1/2)
Indexed mode in the memory address space above 64 kB:
If the CPU register Rn points to a memory address above 64
kB, bits 19:16 are used to calculate the operand of the
address;
A prerequisite is that the operand must be located in the
range Rn 32KB, because the index is a signed 16-bit value;
Outside this range, the operand address can overflow or
underflow the memory address space below or above the
64 kB.
If the registers now point to a memory address space above
64 kB, bits 19:16 are used to determine the address in the
operands.
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Indexed mode: above 64 kB (2/2)
Indexed mode in the memory address space above 64 kB
(continued):
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Indexed mode: MSP430X CPU (1/4)
Indexed mode using a MSP430X CPU instruction:
When a MSP430X CPU instruction is used in indexed mode,
the operand can reside anywhere in the range of addresses
Rn 19 bits;
The operand address is calculated from the sum of the 20-bit
contents of the register Rn and the signed 20-bit index.
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Indexed mode: MSP430X (2/4)
pointed to by (R4 + 2):
MOVX 0xFFFD0( R5) , 2( R4)
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
1 0 0 0 0 1 0 1 1 0 0 1 0 1 0 0
MOVX R5 Indexed 16-bit Indexed R4
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The instruction coding specifies that the word (B/ W= 0 and
A/ L = 1) pointed to by the sum of register R5 contents
memory address pointed to by the sum of the register R4
contents (D- r eg = 0100) and the word X2;
The four MSB indices are placed in the extension word of the
instruction and the other 16 bits are placed in the words
operands is specified by the bits Ad = 1 (Indexed mode) and
As = 01 (Indexed mode), because D- r eg = 0100 and
S- r eg = 0101 respectively.
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Data
CPU Registers
Before After
0x03110 PC 0x03118 PC
0x00200 R4 R4 0x00200
0x101D0 R5 0x101D0 R5
Address Space
0x101D0
0xFFFD0
0x101A0
0x1234 0x1234
X1(R5) 0x101A0 0x101A0
X1(R5)
0x00200
0x00002
0x00202
0xXXXX 0x00202 0x1234 0x00202 X2(R4)
X2(R4)
0xFFD0
0x4594
0x1FC0 PC
0xDDF0
0x4594
0x1FC0
PC
Before After
Code
X1
X2
X1
X2
Destination Address
Source Address
(R4)
(X2)
(R5)
(X1)
0x0002 0x0002
0x03110
0x03112
0x03114
0x03116
0x03118
0x03110
0x03112
0x03114
0x03116
0x03118
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Symbolic mode
The symbolic addressing mode uses the register PC to
determine the location of the operand based on an index;
Similar to the previous addressing mode, there are three
different ways to use symbolic mode with the MSP30X
CPU.
Symbolic mode in the memory address space below 64 kB;
Symbolic mode in the memory address space above 64 kB;
Symbolic mode using a MSP430X CPU instruction.
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Symbolic mode: below 64 kB (1/3)
As in the indexed addressing mode, if the PC register
points to a memory address below 64 kB, the bits 19:16
of the address calculated from the sum of the PC register
and the signed 16-bit index are set to zero.
Move the contents of the address EDEN located at
0x00200 to the address TONI located at 0x00202:
MOV EDEN, TONI
0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0
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0x00200 to the address TONI located at 0x00202 (cont.):
MOV EDEN, TONI
The instruction decoding specifies that the word (B/ W= 0)
pointed to by the sum of the register PC contents
memory address pointed to by the sum of the register PC
contents (D- r eg = 0000) and the word X2;
operands is specified by the bits Ad = 1 (Symbolic mode)
and As = 01 (Symbolic mode), because D- r eg = 0000 and
S- r eg = 0000, respectively.
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Move the contents of address the EDEN located at
MOV EDEN, TONI
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Symbolic mode: above 64 kB (1/4)
If the PC register points to a memory address above 64
kB, bits 19:16 of the PC are used to calculate the operand
address;
The operand must be located in the memory range
PC 32 kB, because the index is a signed 16-bit value;
If outside this range, there may be an overflow or
underflow in the address space corresponding to memory
below 64 kB.
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0x10200 to register R5:
MOV EDEN, R5
The instruction coding specifies that the word (B/ W= 0)
pointed to by the sum of the register PC contents
register R5 (D- r eg = 0101);
0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1
MOV PC Register 16-bit Symbolic R5
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0x10200 to register R5 (continued):
MOV EDEN, R5
The word X1 is in the memory address following the
instruction;
operands is specified by the bits Ad = 0 (Register mode) and
As = 01 (Symbolic mode), because D- r eg = 0101 and
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MOV EDEN, R5

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Symbolic mode: MSP430X CPU (1/4)
When a MSP430X CPU instruction is used in symbolic
mode, the operand can be located anywhere in the range
of the addresses PC 19 bits;
The operand address is calculated from the sum of the
20-bit contents of the PC register and the signed 20-bit
index.
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0x00200 to register R5:
MOVX EDEN, R5
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1
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MOVX EDEN, R5
the function MOVX of the 16-bit data (B/ W= 0 and A/ L = 1),
from the memory address contents pointed to by
(sr c 19: 16: X1 + PC) to register R5;
The bits (sr c 19: 16) are stored in the extension word and
the word X1 is stored in the word following the instruction;
As = 01 (Symbolic mode), because D- r eg = 0000 and
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MOVX EDEN, R5
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Absolute mode
Absolute mode uses the word contents following the
instruction as the operand address;
There are two different ways to use absolute mode with
the MSP30X CPU.
Absolute mode in the memory address space below 64 kB:
In memory space below 64 kB, this instruction operates
in the same way as the MSP430 CPU.
Absolute mode using a MSP430X CPU instruction.
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Absolute mode: MSP430X CPU (1/4)
If a MSP430X CPU instruction is used with an address in
absolute mode, the 20-bit absolute address of the
operand is used with an index of zero (generated by the
constant generators) to point to the operand;
The four MSBs of the indices are placed in the extension
word of the instruction and the other 16 bits are placed
in the words following the instruction.
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0x00200 to the address TONI located at 0x00202:
MOVX &EDEN, &TONI
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0
MOVX SR/CG1 Absolute 16-bit Absolute SR/CG1
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Absolute mode MSP430X CPU (3/4)
MOVX &EDEN, &TONI
the function MOVX of 16-bit data (B/ W= 0 and A/ L = 1) from
the memory address contents pointed to by (sr c 19: 16: X1)
to the memory address contents pointed to by
(dst 19: 16: X2);
The bits sr c 19: 16 and dst 19: 16 are stored in the
extension word;
The words X1 and X2 are stored following the instruction;
and As = 01 (Absolute mode), because D- r eg = 0010 and
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MOVX &EDEN, &TONI
Data
CPU Registers
Before After
0x03110 PC 0x03118 PC
Address Space
0x1234 0x1234
EDEN 0x00200 0x00200
EDEN
0xXXXX 0x00202 0x1234 0x00202 TONI
TONI
0x0200
0x4292
0x1840 PC
PC
Before After
Code
X1
X2
X1
X2
Destination Address
Source Address
0x0202
0x03110
0x03112
0x03114
0x03116
0x03118
0x03110
0x03112
0x03114
0x03116
0x03118
0x0200
0x4292
0x1840
0x0202
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Indirect addressing mode uses the contents of register
Rn to point to the 20-bit operand;
It can only be used to point to the source operand.

Move the operand pointed to by the contents of register
R5 to the memory address TONI located at 0x00202:
MOVX @R5, &TONI
Instruction code: 0x1840 0x45A2
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 1 1 0 1 0 0 0 1 0
MOVX R5 Absolute 16-bit Indirect SR/CG1
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MOVX @R5, &TONI
the function MOVX of 16-bit data (B/ W= 0 and A/ L = 1),
from the memory address contents pointed to by the register
R5 to the memory address contents pointed to by
(dst 19: 16: X1);
The bits dst 19: 16 are stored in the extension word;
The words X1 is stored following the instruction;
and As = 10 (Indirect mode), because D- r eg = 0010 and
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MOVX @R5, &TONI
Data
CPU Registers
Before After
0x00200 R5 0x00200 R5
Address Space
0x1234 0x1234
EDEN 0x00200 0x00200
EDEN
0xXXXX 0x00202 0x1234 0x00202 TONI
TONI
0x0202
0x45A2
0x1840 PC
PC
Before After
Code
X1 X1
Destination Address
Source Address
0x03110
0x03112
0x03114
0x03116
0x03110
0x03112
0x03114
0x03116
0x0202
0x45A2
0x1840
0x03110 PC 0x03116 PC
@R5 @R5
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This addressing mode uses the contents of register Rn to
point to the 20-bit source operand;
The register Rn is automatically incremented by 1 for a
byte operand, by 2 for a word operand and by 4 for an
address operand.
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Move the word pointed to by register R5 to the memory
address TONI located at 0x00202:
MOVX @R5+, &TONI
Instruction code: 0x1840 0x45B2
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 0
MOVX R5 Absolute 16-bit Ind. aut. inc. SR/CG1
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address TONI located at 0x00202 (continued):
MOVX @R5+, &TONI
the function MOVX of the 16-bit data (B/ W= 0 and A/ L = 1),
from the memory address contents pointed to by the register
R5 to the memory address contents pointed to by
(dst 19: 16: X1);
The bits dst 19: 16 are stored in the extension word;
The word X1 is stored following the instruction;
The addressing modes used for the source and destination
operands are specified by the bits Ad = 1 (Absolute mode)
and As = 11 (Indirect auto-increment mode), because
D- r eg = 0010 and S- r eg = 0101, respectively.
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address TONI located at 0x00202 (continued):
MOVX @R5+, &TONI
@R5 @R5
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Immediate mode
The immediate addressing mode allows constants to be
placed after the instruction and use them as source
operands;
There are two ways to use immediate mode:
A 8-bit or 16-bit constant with a MSP430 CPU instruction:
The operation in this situation is similar to that of the
MSP430 CPU.
A 20-bit constant with a MSP430X CPU instruction:
If a MSP430X CPU instruction is used in immediate
addressing mode, the constant has a 20-bit value;
The bits 19: 16 are stored in the extension word and the
remaining bits are stored following the instruction.
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Immediate mode: MSP430X CPU (1/3)
Move the constant #0x12345 to register R5:
MOVX. A #0x12345, R5
0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16
0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 1 1 1 0 1 0 1
MOVX PC Register 20-bit Immediate R5
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Move the constant #0x12345 to register R5 (continued):
MOV. A #0x12345, R5
the function MOVX using 20-bit data (B/ W= 1 and A/ L = 0),
from the location sr c 19: 16: X1 to register R5;
The bits sr c 19: 16 are stored in the extension word;
The word X1 is stored following the instruction;
As = 11 (Immediate mode), because D- r eg = 0101 and
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Move the constant #0x12345 to register R5 (continued):
MOV #0x12345, R5

CPU Registers
Before After
0xXXXXX R5 0x12345 R5
Address Space
0x2345
0x4075
0x1880 PC
PC
Before After
Code
X1 X1
0x03110
0x03112
0x03114
0x03116
0x03110
0x03112
0x03114
0x03116
0x2345
0x4075
0x1880
0x03110 PC 0x03116 PC

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It can only be used to point to the source operand.

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