Lecture 4 ECE 425

Lecture 4 -- Fabrication
Lecture 4 ECE 425
Outline
Fabrication
Concepts
Description of Process
Design rules
Lecture 4 ECE 425
Making Chips
It all starts with silicon
Lecture 4 ECE 425
Wafers
Ingots get cut into wafers, which are 1-2mm thick, and up
to 12 in diameter
Entire wafers are processed, and then cut into chips when
done
Lecture 4 ECE 425
Processing Wafers
Relatively small number of things we can do to wafers
Add atoms other than silicon
Ion bombardment
Diffusion
Expose oxygen to grow SiO
2
Deposit metal or silicon to form wires
Deposit SiO
2
Want to create very small structures, order 0.1 micron in size
Cant just steer oxygen/metal/boron to the places we want it
Instead, expose whole wafer, block parts that we dont want to be
affected
Lecture 4 ECE 425
How Do We Do That? -- Photolithography
Photoresists are compounds whose solubility in a particular
solvent changes when exposed to light
Lecture 4 ECE 425
Photolithography
Photoresist prevents ion bombardment or etching from
reaching regions of the chip
Can then remove excess photoresist and start with
next layer
Lecture 4 ECE 425
Photolithography
Use masks to define the regions that get exposed to light
at each stage
Mask set for a chip can exceed $1M to produce
Masks created by electron-beam cutting of materials
(usually)
Lecture 4 ECE 425
Typical Processes
Lecture 4 ECE 425
Other Processes
Lecture 4 ECE 425
Substrate Contacts
Need for both P- and N-FETs
P-FET substrate should be connected to V
dd
N-FET should connect to ground (V
ss
)
Get this backward, and youll turn on substrate-drain or
substrate-source junctions and fry the chip
Lecture 4 ECE 425
Building Chips
Putting a gate over diffusion (N or P) creates a transistor
Highly-doped contacts improve performance
Two types of wires to connect devices
Polysilicon (silicon formed of many crystals)
Metal
Used to be aluminum, copper now used in many
processes
Parameters of fabrication processes
Feature size (0.09 micron seems to be state-of-art)
Size of smallest structure that can be defined
Number of metal layers (7-9 in some processes)
Number of polysilicon layers (few in logic processes,
more in memory)
Lecture 4 ECE 425
Vias
Each type of structure (wire, poly, gate, etc.) is typically
constructed as a separate layer of material
Insulating glass deposited between layers
A via is a connection that punches through the glass to
electrically connect components on two layers
Some processes allow stacked vias, others dont
Lecture 4 ECE 425
Design Rules
Fabrication processes have limits about how close parts of a circuit
can be together, minimum size of wires, transistors, etc.
Driven by equipment precision, alignment between steps
Define Design Rules that tell the designer what is allowed by the
process
Significant tradeoffs involved in creating design rules for a process
Conservative rules give high yield
Aggressive rules can improve performance, density
Design rules specified in either microns (process-specific) or !
(process-independent)
! is defined as 1/2 the minimum dimension of a fabricated
structure
Using !-based rules can allow designs to be fabricated in multiple
processes, at the cost of being conservative
This approach is also becoming less effective in deep-
submicron processes
Lecture 4 ECE 425
Design Rules
Are not a guarantee of functionality
Designs that follow the rules will still have chips that dont
work
Designs that break the rules may still get chips that work
Chip designers sometimes negotiate exceptions to the
rules to improve performance at the cost of yield
However, following the design rules maximizes the
chance that chips will work, and yield when you fabricate
many copies of a chip
For this class, well treat design rules as absolutes that
must be obeyed
Lecture 4 ECE 425
Putting it all Together -- NAND Gate Layout
Lecture 4 ECE 425
N-Diffusion Mask
Lecture 4 ECE 425
P-Diffusion Mask
Lecture 4 ECE 425
Metal and Contacts
Lecture 4 ECE 425
The Full Gate
Lecture 4 ECE 425
Wrapping Up
Reading: 3.1-3.3 in your book, remainder of Chapter 3 if
youre interested in more detail about modern fabrication
Next time: Layout of gates