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Maquina moore

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pm is
Port ( sel : in STD_LOGIC;
sal : out STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC);
end pm;

architecture Behavioral of pm is
type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal edo_prox, edo_pres: estados;

begin
secuencial: process(clk)
begin
if(clk'event and clk='1')then
if(reset= '0') then
edo_pres<= s0;
else
edo_pres <= edo_prox;
end if;
end if;
end process secuencial;

comb1: process (sel, edo_pres)
begin
case edo_pres is
when s0=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s2;
end if;
when s1=>
edo_prox <= s3;
when s2=>
edo_prox <= s4;
when s3=>
edo_prox <= s7;
when s4=>
edo_prox <= s5;
when s5=>
edo_prox <= s6;
when s6=>
edo_prox <= s8;
when s8=>
if(sel ='0') then
edo_prox <= s1;
else
edo_prox <= s2;
end if;
when others =>
if(sel='0') then
edo_prox <= s1;
else
edo_prox <=s2;
end if;
end case;
end process comb1;

comb2: process(edo_pres)
begin
case edo_pres is
when s7=>
sal <= '1';
when s8=>
sal <= '1';
when others =>
sal <= '0';
end case;
end process comb2;


end Behavioral;



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pm2 is
Port ( sel : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
sal : out STD_LOGIC);
end pm2;

architecture Behavioral of pm2 is

type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal edo_prox, edo_pres: estados;

begin
secuencial: process(clk)
begin
if(clk'event and clk='1')then
if(reset= '0') then
edo_pres<= s0;
else
edo_pres <= edo_prox;
end if;
end if;
end process secuencial;

comb1: process (sel, edo_pres)
begin
case edo_pres is
when s0=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s2;
end if;

when s1=>
if(sel = '0') then
edo_prox <= s3;
else
edo_prox <= s2;
end if;

when s2=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s4;
end if;

when s3=>
if(sel = '0') then
edo_prox <= s7;
else
edo_prox <= s2;
end if;

when s4=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s5;
end if;

when s5=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s6;
end if;

when s6=>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s8;
end if;

when s7 =>
if(sel = '0') then
edo_prox <= s1;
else
edo_prox <= s2;
end if;

when s8=>
if(sel ='0') then
edo_prox <= s1;
else
edo_prox <= s2;
end if;

when others =>
if(sel='0') then
edo_prox <= s1;
else
edo_prox <=s2;
end if;
end case;
end process comb1;

comb2: process(edo_pres)
begin
case edo_pres is
when s7=>
sal <= '1';
when s8=>
sal <= '1';
when others =>
sal <= '0';
end case;
end process comb2;

end Behavioral;

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