Layout Rules:

Q: Do we use lambda rule or micron rule?

o For the NCSU design kit the units o! the rules are in lambda" Lambda is
de!ined as #"$%the minimum length" &he grid unit is lambda"
o 'ou can ad(ust the grid s)acing by modi!ying the editor )ro)erties
*+)tions,-Dis)lay"""."
Q: /hat are the minimum transistor width and length?
o For the NCSU design kit the minimum length is #"0 um and the minimum
width is #"1 um"
Q: 2ow do 3 reco4er cell4iews i! ic!b crashes?
Cadence kee)s a tem)orary co)y o! the cell4iew that you are currently
working on *called the )anic cell4iew." 3! cadence crashes you can retrie4e the
)anic cell4iew by ty)ing db+)en5anicCell6iew *7libname7 7cellname7
74iewname7. in the C3/" 2ere libname is the library name cellname is the name
o! your cell4iew and 4iewname is either layout schematic"""
+)en your cell4iew a!ter restoring the )anic cell" D+ N+& try to reo)en the
cell4iew be!ore doing the db+)en5anicCell6iew call or you84e lost the )anic cell"
Q: /here can we !ind design rules !or layout?
o &he technology !ile contains an outline o! the DRC rules" &he rule !ile
di4aDRC"rul is the !ile that is e9ecuted when the DRC o)eration is
)er!ormed"
Q: 2ow can 3 create contacts and wires?
'ou can create contacts using the Create,-Contact" For wires use Create,-5ath
*the de!ault si:e o! the wire is the minimum width o! the layer you ha4e chosen in
LS/ or the last si:e you set."
Q: 2ow do 3 gi4e the contact !or / ; #"< um when the contact width is #"= um?
&he width o! a transistor is the distance in the y,direction *in layout 4iew. o! the
channel *where the )oly o4erla)s the acti4e region." &hus the y,distance o! the
contact area need not be the same as the y,distance *width. o! the channel"
Q: DRC 6iolation Question: )oly> endca) ? #"$#
'ou need to e9tend the )oly to #"$um )ast the acti4e@di!!usion area"
Q: DRC 6iolation Question: need )ohmic within $um o!
NA+S@ndi!!R@nwellR@5N54ertical
'ou need a substrate@well contact within $um o! the FB& otherwise the contact
resistance is too large"
Q: DRC 6iolation Question: ndi!! s)acing to hot nwell ? C"0#D substrate so!t
connected
&here should be a 6SSE@6DDE )in connected to the substrate@well contact"
Q: DRC 6iolation Question: o!!,grid errors
&his error most o!ten occurs when the grid resolution is too low" &he error means
that the end coordinates o! the layers are not on a grid" Check to see i! the grid,
settings *+)tions,-Dis)lay""". are correct"
Q: 2ow to )rint"
5rinting in Cadence
+)en u) your cell4iew"
goto the Design menu
,,,-)lot
,,,,,,,-submit
&hen click the 8)lot o)tions8 button"
'ou )robably want to click the center )lot and !it to )age buttons"
Down near the bottom check the button near 7send )lot only to !ile7 and ty)e in a
!ilename in the bo9 ne9t to it"" ie" schematic")s
Uncheck the 7mail log to7 button
&hen click +F and click +F on the submit )lot )age"
Now o)en u) an 9term and change directory to the directory where your cadence
!iles are" your schematic")s !ile should be there"
ty)e l) schematic")s
*where schematic")s is the !ile name o! your schematic.
3t should now )rint