SAURABH TRIPATHI

201311013
ASSIGNMENT
Develop a Verilog HDL code for shift register functionality (74595) and test that it works upto
20 MHz frequency.
Please use the post place and route analysis to determine Fmax.

74ls595 is a 8-bit serial-in parallel out shift register. The data is shifted serially in 8-D Flipflops
and then transferred to storage registers. Shift registers have reset, clk, data-in. Storage
registers have input as output of the shift register. Tri-state buffer is used to enable output to
be seen parallelly.














Storage 0
Shifter 0
Shifter 1
Shifter 2
Shifter 3
Shifter 4
Shifter 5
Shifter 6
Shifter 7
Storage 1
Storage 2
Storage 3
Storage 4
Storage 5
Storage 6
Storage 7
ctrl
output
Verilog Code

Test bench

Simulation result



Synthesis report
Release 14.4 - xst P.49d (nt64)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs

--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.20 secs

--> Reading design: shift_reg.prj

TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT


=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "shift_reg.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO

---- Target Parameters
Output File Name : "shift_reg"
Output Format : NGC
Target Device : xc3s500e-4-vq100

---- Source Options
Top Module Name : shift_reg
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No

---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES

---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5

=========================================================================


=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "shift_reg.v" in library work
Module <shift_reg> compiled
No errors in compilation
Analysis of file <"shift_reg.prj"> succeeded.


=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <shift_reg> in library <work>.


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <shift_reg>.
Module <shift_reg> is correct for synthesis.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <i> in unit <shift_reg> has a constant value of 0 during circuit operation. The
register is replaced by logic.

Synthesizing Unit <shift_reg>.
Related source file is "shift_reg.v".
Found 8-bit tristate buffer for signal <out>.
Found 8-bit register for signal <temp1>.
Found 8-bit register for signal <temp2>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <shift_reg> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers : 9
1-bit register : 8
8-bit register : 1
# Tristates : 8
1-bit tristate buffer : 8

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers : 16
Flip-Flops : 16

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <shift_reg> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block shift_reg, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers : 16
Flip-Flops : 16

=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : shift_reg.ngr
Top Level Output File Name : shift_reg
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No

Design Statistics
# IOs : 12

Cell Usage :
# BELS : 1
# INV : 1
# FlipFlops/Latches : 16
# FDC : 8
# FDR : 8
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 11
# IBUF : 3
# OBUFT : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500evq100-4

Number of Slices: 9 out of 4656 0%
Number of Slice Flip Flops: 16 out of 9312 0%
Number of 4 input LUTs: 1 out of 9312 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 66 18%
Number of GCLKs: 1 out of 24 4%

---------------------------
Partition Resource Summary:
---------------------------

No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 16 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF | 8 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 1.346ns (Maximum Frequency: 742.942MHz)
Minimum input arrival time before clock: 3.163ns
Maximum output required time after clock: 4.283ns
Maximum combinational path delay: 6.371ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 1.346ns (frequency: 742.942MHz)
Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Delay: 1.346ns (Levels of Logic = 0)
Source: temp1_7 (FF)
Destination: temp1_6 (FF)
Source Clock: clk rising
Destination Clock: clk rising

Data Path: temp1_7 to temp1_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 2 0.591 0.447 temp1_7 (temp1_7)
FDC:D 0.308 temp1_6
----------------------------------------
Total 1.346ns (0.899ns logic, 0.447ns route)
(66.8% logic, 33.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset: 3.163ns (Levels of Logic = 1)
Source: reset (PAD)
Destination: temp2_0 (FF)
Destination Clock: clk rising

Data Path: reset to temp2_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 16 1.218 1.034 reset_IBUF (reset_IBUF)
FDR:R 0.911 temp2_0
----------------------------------------
Total 3.163ns (2.129ns logic, 1.034ns route)
(67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset: 4.283ns (Levels of Logic = 1)
Source: temp2_7 (FF)
Destination: out<7> (PAD)
Source Clock: clk rising

Data Path: temp2_7 to out<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.591 0.420 temp2_7 (temp2_7)
OBUFT:I->O 3.272 out_7_OBUFT (out<7>)
----------------------------------------
Total 4.283ns (3.863ns logic, 0.420ns route)
(90.2% logic, 9.8% route)

=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay: 6.371ns (Levels of Logic = 3)
Source: ctrl (PAD)
Destination: out<7> (PAD)

Data Path: ctrl to out<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.218 0.420 ctrl_IBUF (ctrl_IBUF)
INV:I->O 8 0.704 0.757 ctrl_inv1_INV_0 (ctrl_inv)
OBUFT:T->O 3.272 out_7_OBUFT (out<7>)
----------------------------------------
Total 6.371ns (5.194ns logic, 1.177ns route)
(81.5% logic, 18.5% route)

=========================================================================


Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 9.49 secs

-->

Total memory usage is 267872 kilobytes

Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 1 ( 0 filtered)

RTL schematic

Technology schematic

Post place and route synthesis

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "E:/daiict/xilinx/my_work/shifting/shift_reg.xst" -ofn
"E:/daiict/xilinx/my_work/shifting/shift_reg.syr"
Reading design: shift_reg.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "shift_reg.v" in library work
Module <shift_reg> compiled
No errors in compilation
Analysis of file <"shift_reg.prj"> succeeded.


=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <shift_reg> in library <work>.


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <shift_reg>.
Module <shift_reg> is correct for synthesis.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...
INFO:Xst:2679 - Register <i> in unit <shift_reg> has a constant value of 0 during circuit operation. The
register is replaced by logic.

Synthesizing Unit <shift_reg>.
Related source file is "shift_reg.v".
Found 8-bit tristate buffer for signal <out>.
Found 8-bit register for signal <temp1>.
Found 8-bit register for signal <temp2>.
Summary:
inferred 16 D-type flip-flop(s).
inferred 8 Tristate(s).
Unit <shift_reg> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers : 9
1-bit register : 8
8-bit register : 1
# Tristates : 8
1-bit tristate buffer : 8

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers : 16
Flip-Flops : 16

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <shift_reg> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block shift_reg, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers : 16
Flip-Flops : 16

=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 16 |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF | 8 |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

Minimum period: 1.346ns (Maximum Frequency: 742.942MHz)
Minimum input arrival time before clock: 3.163ns
Maximum output required time after clock: 4.283ns
Maximum combinational path delay: 6.371ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 shift_reg.ngc
shift_reg.ngd

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4 shift_reg.ngc shift_reg.ngd

Reading NGO file "E:/daiict/xilinx/my_work/shifting/shift_reg.ngc" ...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0

Writing NGD file "shift_reg.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec

Writing NGDBUILD log file "shift_reg.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc3s500e-fg320-4 -cm area -ir off -pr off -c 100 -o shift_reg_map.ncd
shift_reg.ngd shift_reg.pcf
Using target part "3s500efg320-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...

Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 16 out of 9,312 1%
Logic Distribution:
Number of occupied Slices: 8 out of 4,656 1%
Number of Slices containing only related logic: 8 out of 8 100%
Number of Slices containing unrelated logic: 0 out of 8 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Number of bonded IOBs: 12 out of 232 5%
Number of BUFGMUXs: 1 out of 24 4%

Average Fanout of Non-Clock Nets: 2.53

Peak Memory Usage: 202 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 2 secs

NOTES:

Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.

Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.

Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.

Mapping completed.
See MAP report file "shift_reg_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -t 1 shift_reg_map.ncd shift_reg.ncd shift_reg.pcf



Constraints file: shift_reg.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"shift_reg" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing
constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the
performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will
not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved
for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to
"high".

Device speed data version: "PRODUCTION 1.27 2013-10-13".


Design Summary Report:

Number of External IOBs 12 out of 232 5%

Number of External Input IOBs 4

Number of External Input IBUFs 4

Number of External Output IOBs 8

Number of External Output IOBs 8

Number of External Bidir IOBs 0


Number of BUFGMUXs 1 out of 24 4%
Number of Slices 8 out of 4656 1%
Number of SLICEMs 0 out of 2328 0%



Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High

Starting initial Timing Analysis. REAL time: 2 secs
Finished initial Timing Analysis. REAL time: 2 secs


Starting Placer
Total REAL time at the beginning of Placer: 2 secs
Total CPU time at the beginning of Placer: 1 secs

Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:d7) REAL time: 3 secs

Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:d7) REAL time: 3 secs

Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:d7) REAL time: 3 secs

Phase 4.2 Initial Clock and IO Placement
..............
Phase 4.2 Initial Clock and IO Placement (Checksum:c2eadd7) REAL time: 3 secs

Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:c2eadd7) REAL time: 3 secs

Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:c2eadd7) REAL time: 3 secs

Phase 7.3 Local Placement Optimization
.............
Phase 7.3 Local Placement Optimization (Checksum:de382d37) REAL time: 3 secs

Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:de382d37) REAL time: 3 secs

Phase 9.8 Global Placement
..
Phase 9.8 Global Placement (Checksum:762a8db3) REAL time: 5 secs

Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:762a8db3) REAL time: 5 secs

Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:6c946ce9) REAL time: 5 secs

Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:6c946ce9) REAL time: 5 secs

Total REAL time to Placer completion: 5 secs
Total CPU time to Placer completion: 3 secs
Writing design to file shift_reg.ncd



Starting Router


Phase 1 : 50 unrouted; REAL time: 9 secs

Phase 2 : 41 unrouted; REAL time: 9 secs

Phase 3 : 8 unrouted; REAL time: 9 secs

Phase 4 : 10 unrouted; (Par is working to improve performance) REAL time: 9 secs

Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs

Updating file: shift_reg.ncd with current fully routed design.

Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs

Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs

Updating file: shift_reg.ncd with current fully routed design.

Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs

Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs

Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs

Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs

Total REAL time to Router completion: 10 secs
Total CPU time to Router completion: 8 secs

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X2Y10| No | 8 | 0.010 | 0.176 |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 1.771ns| N/A| 0
_BUFGP | HOLD | 1.021ns| | 0| 0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
constraint is not analyzed due to the following: No paths covered by this
constraint; Other constraints intersect with this constraint; or This
constraint was disabled by a Path Tracing Control. Please run the Timespec
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs
Total CPU time to PAR completion: 8 secs

Peak Memory Usage: 211 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file shift_reg.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml shift_reg.twx shift_reg.ncd -o shift_reg.twr
shift_reg.pcf
Loading device for application Rf_Device from file '3s500e.nph' in environment
C:\Xilinx\14.7\ISE_DS\ISE\.
"shift_reg" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4

Analysis completed Fri Mar 07 00:42:11 2014
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 1 secs

Process "Generate Post-Place & Route Static Timing" completed successfully