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Intel Core 2 Processor (Penryn)

Intel Nehalem Processor


Intel Atom Processor
AMD Opteron Processor (Barcelona)
Intel 32/64-bit x86 Software Architecture
AMD 32/64-bit x86 Software Architecture
x86 Assembly Language Programming
Protected Mode Programming
PC Virtualization
IO Virtualization (IOV)
Computer Architectures with Intel Chipsets
Intel QuickPath Interconnect (QPI)
PCI Express 2.0
USB 2.0
USB 3.0
Embedded USB 2.0 Workshop
PCI
PCI-X
Modern DRAM Architecture
SAS
Serial ATA
High Speed Design
EMI / EMC
Bluetooth Wireless Product Development
SMT Manufacturing
SMT Testing






Basic Terms and Concepts
Mode/SubMode
































































1
Is This the Book for You?
A Moving Target
x86 Instruction Set Architecture (ISA)

x86 Instruction Set Architecture
2
Glossary of Terms
32-/64-bit x86 Instruction Set Architecture Specification
The Specification Is the Final Word

About This Book
3
Book Organization
Basic Terms and Concepts
Mode/SubMode

x86 Instruction Set Architecture
4
Topics Outside the Scope of This Book
The CPUID Instruction
Detailed Description of Hyper-Threading

About This Book
5
Detailed Description of Performance Monitoring
Documentation Conventions
Trademarks

x86 Instruction Set Architecture
6
Visit Our Web Site

About This Book
7
We Want Your Feedback

x86 Instruction Set Architecture
8

Part 1
Basic Terms and Concepts
Mode/SubMode
The Next Part


11
This Chapter
The Next Chapter
ISA Definition
This Book Focuses on the Common Intel/AMD ISA
For Simplicity, Intel Terminology Is Used Throughout

x86 Instruction Set Architecture
12
Some Terms in This Chapter May Be New To the Reader
Two x86 ISA Architectures

Chapter 1: Basic Terms and Concepts
13
Processors, Cores and Logical Processors

x86 Instruction Set Architecture
14
Fundamental Processing Engine: Logical Processor

Chapter 1: Basic Terms and Concepts
15
IA Instructions vs. Micro-ops
RISC Instructions Sets Are Simple
x86 Instruction Set Is Complex

x86 Instruction Set Architecture
16
But You Cant Leave It Behind
Complexity vs. Speed Dictated a Break With the Past
Why Not Publish a Micro-Op ISA?

Chapter 1: Basic Terms and Concepts
17
Some Important Definitions
Virtual vs. Physical Memory

x86 Instruction Set Architecture
18
Other Important Terms

Chapter 1: Basic Terms and Concepts
19

x86 Instruction Set Architecture
20

21
The Previous Chapter
This Chapter
The Next Chapter
Basic Execution Modes

x86 Instruction Set Architecture
22

Chapter 2: Mode/SubMode Introduction
23

x86 Instruction Set Architecture
24

Chapter 2: Mode/SubMode Introduction
25
IA-32 SubModes

x86 Instruction Set Architecture
26

Chapter 2: Mode/SubMode Introduction
27

x86 Instruction Set Architecture
28
IA-32e SubModes

Chapter 2: Mode/SubMode Introduction
29

x86 Instruction Set Architecture
30
Mode Switching Basics
Initial Switch from IA-32 to IA-32e Mode

Chapter 2: Mode/SubMode Introduction
31

x86 Instruction Set Architecture
32

Chapter 2: Mode/SubMode Introduction
33
IA-32e SubMode Selection

x86 Instruction Set Architecture
34

Chapter 2: Mode/SubMode Introduction
35

x86 Instruction Set Architecture
36

Chapter 2: Mode/SubMode Introduction
37

x86 Instruction Set Architecture
38
Protected/Compatibility 16-/32-bit SubModes

Chapter 2: Mode/SubMode Introduction
39

x86 Instruction Set Architecture
40

41
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
42
Major Evolutionary Developments

Chapter 3: A (very) Brief History
43

x86 Instruction Set Architecture
44

Chapter 3: A (very) Brief History
45

x86 Instruction Set Architecture
46
16-bit Mode Background
8086 and Real Mode

Chapter 3: A (very) Brief History
47

x86 Instruction Set Architecture
48
286 Introduced 16-bit Protected Mode

Chapter 3: A (very) Brief History
49

x86 Instruction Set Architecture
50

Chapter 3: A (very) Brief History
51
386 Supported Both 16- and 32-bit Protected Mode

x86 Instruction Set Architecture
52

Chapter 3: A (very) Brief History
53

x86 Instruction Set Architecture
54

Chapter 3: A (very) Brief History
55
The Intel Microarchitecture Families

x86 Instruction Set Architecture
56

Chapter 3: A (very) Brief History
57
A Brief Timeline

x86 Instruction Set Architecture
58

Chapter 3: A (very) Brief History
59

x86 Instruction Set Architecture
60

Chapter 3: A (very) Brief History
61

x86 Instruction Set Architecture
62

63
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
64
State After Reset

Chapter 4: State After Reset
65

x86 Instruction Set Architecture
66

Chapter 4: State After Reset
67

x86 Instruction Set Architecture
68

Chapter 4: State After Reset
69

x86 Instruction Set Architecture
70

Chapter 4: State After Reset
71

x86 Instruction Set Architecture
72

Chapter 4: State After Reset
73
Soft Reset
Boot Strap Processor (BSP) Selection

x86 Instruction Set Architecture
74
AP Discovery and Configuration
Initial Memory Reads

Chapter 4: State After Reset
75

x86 Instruction Set Architecture
76

The Previous Part
This Part

The Next Part

79
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
80
The Next Chapter
The Pre-386 Register Sets
8086 Register Set

Chapter 5: Intro to the IA-32 Ecosystem
81

x86 Instruction Set Architecture
82
286 Register Set

Chapter 5: Intro to the IA-32 Ecosystem
83

x86 Instruction Set Architecture
84
IA-32 Register Set Overview

Chapter 5: Intro to the IA-32 Ecosystem
85
Control Registers

x86 Instruction Set Architecture
86

Chapter 5: Intro to the IA-32 Ecosystem
87

x86 Instruction Set Architecture
88
Status/Control Register (Eflags)

Chapter 5: Intro to the IA-32 Ecosystem
89
Instruction Fetch Facilities
General

x86 Instruction Set Architecture
90
Branch Prediction Logic
General Purpose Data Registers

Chapter 5: Intro to the IA-32 Ecosystem
91

x86 Instruction Set Architecture
92
Defining Memory Regions/Characteristics
MTRRs
Segment Registers

Chapter 5: Intro to the IA-32 Ecosystem
93
Address Translation Facilities
Interrupt/Exception Facilities

x86 Instruction Set Architecture
94
Kernel Facilities

Chapter 5: Intro to the IA-32 Ecosystem
95
Real Mode Has No Memory Protection
Memory Protection in Protected Mode
Introduction
Segment Selection in Protected Mode

x86 Instruction Set Architecture
96
Access Rights Check
The Descriptor Tables
Descriptor Table Registers

Chapter 5: Intro to the IA-32 Ecosystem
97
Task Data Structure
Address Translation Facilities
Effective/Virtual/Linear/Physical Addresses

x86 Instruction Set Architecture
98
Introduction to Address Translation (Paging)
RAM Is Finite and Cant Hold Everything

Chapter 5: Intro to the IA-32 Ecosystem
99
RAM and Mass Storage Are Managed on a Page Basis
This Requires a Series of Directories
Malloc Request

x86 Instruction Set Architecture
100
Problem: Non-Contiguous Memory Allocation
Malloc Returns a Virtual Address to the Application

Chapter 5: Intro to the IA-32 Ecosystem
101
IA-32 Applications Have a 4GB Virtual Address Space
Legacy FP Facilities
In the Beginning, FPU Was External and Optional

x86 Instruction Set Architecture
102
It Was Slow...
486DX Integrated It
x87 Register Set
x87 FP Instruction Set
General Purpose Instruction Set
MMX Facilities

Chapter 5: Intro to the IA-32 Ecosystem
103
Introduction
SIMD Programming Model

x86 Instruction Set Architecture
104
SSE Facilities
Introduction
Motivation

Chapter 5: Intro to the IA-32 Ecosystem
105
Instruction Set
Model-Specific Registers
General

x86 Instruction Set Architecture
106
Accessing the MSRs
Debug Facilities

Chapter 5: Intro to the IA-32 Ecosystem
107
Automatic Task Switching Mechanism

x86 Instruction Set Architecture
108

109
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
110
The Next Chapter
Why a Comprehensive Instruction Set Listing Isnt
Included

Chapter 6: Instruction Set Expansion
111
386 Instruction Set

x86 Instruction Set Architecture
112

Chapter 6: Instruction Set Expansion
113

x86 Instruction Set Architecture
114

Chapter 6: Instruction Set Expansion
115

x86 Instruction Set Architecture
116

Chapter 6: Instruction Set Expansion
117
Instruction Set (as of March, 2009)

x86 Instruction Set Architecture
118

Chapter 6: Instruction Set Expansion
119

x86 Instruction Set Architecture
120

Chapter 6: Instruction Set Expansion
121

x86 Instruction Set Architecture
122

Chapter 6: Instruction Set Expansion
123

x86 Instruction Set Architecture
124

Chapter 6: Instruction Set Expansion
125

x86 Instruction Set Architecture
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Chapter 6: Instruction Set Expansion
127

x86 Instruction Set Architecture
128

Chapter 6: Instruction Set Expansion
129

x86 Instruction Set Architecture
130

Chapter 6: Instruction Set Expansion
131

x86 Instruction Set Architecture
132

Chapter 6: Instruction Set Expansion
133

x86 Instruction Set Architecture
134

Chapter 6: Instruction Set Expansion
135

x86 Instruction Set Architecture
136

Chapter 6: Instruction Set Expansion
137

x86 Instruction Set Architecture
138

Chapter 6: Instruction Set Expansion
139

x86 Instruction Set Architecture
140

Chapter 6: Instruction Set Expansion
141

x86 Instruction Set Architecture
142

Chapter 6: Instruction Set Expansion
143

x86 Instruction Set Architecture
144

Chapter 6: Instruction Set Expansion
145

x86 Instruction Set Architecture
146

Chapter 6: Instruction Set Expansion
147

x86 Instruction Set Architecture
148

Chapter 6: Instruction Set Expansion
149

x86 Instruction Set Architecture
150

Chapter 6: Instruction Set Expansion
151

x86 Instruction Set Architecture
152

Chapter 6: Instruction Set Expansion
153

x86 Instruction Set Architecture
154

155
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
156
The Next Chapter
64-bit Machine Language Instruction Format
A Complex Instruction Set with Roots in the Past

Chapter 7: 32-bit Machine Language Instruction Format
157
Effective Operand Size
Introduction
Operand Size in 16- and 32-bit Code Segments

x86 Instruction Set Architecture
158
Operand Size in 64-bit Code Segments

Chapter 7: 32-bit Machine Language Instruction Format
159

x86 Instruction Set Architecture
160
Instruction Composition

Chapter 7: 32-bit Machine Language Instruction Format
161

x86 Instruction Set Architecture
162
Instruction Format Basics

Chapter 7: 32-bit Machine Language Instruction Format
163

x86 Instruction Set Architecture
164

Chapter 7: 32-bit Machine Language Instruction Format
165

x86 Instruction Set Architecture
166

Chapter 7: 32-bit Machine Language Instruction Format
167

x86 Instruction Set Architecture
168
Opcode (Instruction Identification)
In the Beginning

Chapter 7: 32-bit Machine Language Instruction Format
169
1-byte Opcodes

x86 Instruction Set Architecture
170

Chapter 7: 32-bit Machine Language Instruction Format
171

x86 Instruction Set Architecture
172
2-byte Opcodes Use 2-Level Lookup
2nd-Level Opcode Map Introduced in 286
Instructions with 2-byte Opcodes: Five Possible Forms

Chapter 7: 32-bit Machine Language Instruction Format
173
A 2-byte opcode preceded by a prefix byte being used in a non-stan-
dard manner (see Special Use of Prefix Bytes on page177) that alters
the characteristics of the instruction.

x86 Instruction Set Architecture
174

Chapter 7: 32-bit Machine Language Instruction Format
175

x86 Instruction Set Architecture
176
3-byte Opcodes Use 3-Level Lookup
3-Level Opcode Maps Introduced in Pentium 4 Prescott
Currently There Are Two 3rd-Level Maps Defined
Instructions with 3-byte Opcodes: Three Possible Forms

Chapter 7: 32-bit Machine Language Instruction Format
177
A 3-byte opcode preceded by a prefix byte being used in a non-standard
manner (see Special Use of Prefix Bytes on page177) that alters the
characteristics of the instruction.
Special Use of Prefix Bytes

x86 Instruction Set Architecture
178

Chapter 7: 32-bit Machine Language Instruction Format
179

x86 Instruction Set Architecture
180
Opcode Micro-Maps (Groups)
Micro-Maps Associated with 1-byte Opcodes
Some Opcodes Employ 2 x 8 Micro-Maps

Chapter 7: 32-bit Machine Language Instruction Format
181

x86 Instruction Set Architecture
182

Chapter 7: 32-bit Machine Language Instruction Format
183
Micro-Maps Associated with 2-byte Opcodes

x86 Instruction Set Architecture
184

Chapter 7: 32-bit Machine Language Instruction Format
185

x86 Instruction Set Architecture
186

Chapter 7: 32-bit Machine Language Instruction Format
187
3-byte Opcodes Dont Use Micro-Maps
x87 FP Opcodes Inhabit Opcode Mini-Maps

x86 Instruction Set Architecture
188

Chapter 7: 32-bit Machine Language Instruction Format
189
Special Opcode Fields

x86 Instruction Set Architecture
190

Chapter 7: 32-bit Machine Language Instruction Format
191

x86 Instruction Set Architecture
192

Chapter 7: 32-bit Machine Language Instruction Format
193

x86 Instruction Set Architecture
194
Operand Identification
General

Chapter 7: 32-bit Machine Language Instruction Format
195
Specifying Registers as Operands

x86 Instruction Set Architecture
196
Implicit Register Specification
Explicit Register Specification in Opcode
Explicit Register Specification in ModRM Byte

Chapter 7: 32-bit Machine Language Instruction Format
197

x86 Instruction Set Architecture
198
Addressing a Memory-Based Operand
Instruction Can Specify Only One Memory-Based Operand

Chapter 7: 32-bit Machine Language Instruction Format
199

x86 Instruction Set Architecture
200
Addressing Memory Using the ModRM Byte

Chapter 7: 32-bit Machine Language Instruction Format
201

x86 Instruction Set Architecture
202

Chapter 7: 32-bit Machine Language Instruction Format
203
Using the SIB Byte to Access a Data Structure

x86 Instruction Set Architecture
204

Chapter 7: 32-bit Machine Language Instruction Format
205

x86 Instruction Set Architecture
206
Near and Far Branch Target Addressing

Chapter 7: 32-bit Machine Language Instruction Format
207

x86 Instruction Set Architecture
208

Chapter 7: 32-bit Machine Language Instruction Format
209
Specifying an Immediate Value As an Operand

x86 Instruction Set Architecture
210
Instruction Prefixes

Chapter 7: 32-bit Machine Language Instruction Format
211
Operand Size Override Prefix (66h)
In 32-bit Mode

x86 Instruction Set Architecture
212

Chapter 7: 32-bit Machine Language Instruction Format
213
In 16-bit Mode
Special Usage of 66h Prefix

x86 Instruction Set Architecture
214
Address Size Override Prefix (67h)
In 32-Bit Mode

Chapter 7: 32-bit Machine Language Instruction Format
215
In 16-Bit Mode
Lock Prefix
Shared Resource Concept

x86 Instruction Set Architecture
216
Race Condition Can Present Problem
Guaranteeing Atomicity of Read/Modify/Write

Chapter 7: 32-bit Machine Language Instruction Format
217
Use Locked RMW to Obtain and Give Up Semaphore Owner-
ship

x86 Instruction Set Architecture
218
Instructions That Accept Lock Prefix
Repeat Prefixes
Normal Usage

Chapter 7: 32-bit Machine Language Instruction Format
219

x86 Instruction Set Architecture
220
Special Usage
Segment Override Prefix
General

Chapter 7: 32-bit Machine Language Instruction Format
221
Usage In String Operations
Segment Override Use With MMX and SSE1 - 4 Instructions
Branch Hint Prefix

x86 Instruction Set Architecture
222
Summary of Instruction Set Formats

Chapter 7: 32-bit Machine Language Instruction Format
223

x86 Instruction Set Architecture
224

Chapter 7: 32-bit Machine Language Instruction Format
225

x86 Instruction Set Architecture
226

227
The Previous Chapter

x86 Instruction Set Architecture
228
This Chapter
The Next Chapter

Chapter 8: Real Mode (8086 Emulation)
229
8086 Emulation

x86 Instruction Set Architecture
230

Chapter 8: Real Mode (8086 Emulation)
231
Unused Facilities

x86 Instruction Set Architecture
232
Real Mode OS Environment
Single-Task OS Environment Overview
Command Line Interface (CLI)

Chapter 8: Real Mode (8086 Emulation)
233
Program Loader
OS Services

x86 Instruction Set Architecture
234
Direct IO Access
Application Memory Usage
Task Initiation, Execution and Termination

Chapter 8: Real Mode (8086 Emulation)
235
Running Real Mode Applications Under a Protected Mode
OS
Real Mode Applications Arent Supported in IA-32e Mode
Real Mode Register Set
Introduction

x86 Instruction Set Architecture
236

Chapter 8: Real Mode (8086 Emulation)
237
Control Registers

x86 Instruction Set Architecture
238
CR0

Chapter 8: Real Mode (8086 Emulation)
239

x86 Instruction Set Architecture
240

Chapter 8: Real Mode (8086 Emulation)
241

x86 Instruction Set Architecture
242

Chapter 8: Real Mode (8086 Emulation)
243
Address Translation (Paging) Control Registers

x86 Instruction Set Architecture
244
CR4 (Feature Control Register)

Chapter 8: Real Mode (8086 Emulation)
245

x86 Instruction Set Architecture
246

Chapter 8: Real Mode (8086 Emulation)
247

x86 Instruction Set Architecture
248

Chapter 8: Real Mode (8086 Emulation)
249
XCR0 (XFEM)

x86 Instruction Set Architecture
250

Chapter 8: Real Mode (8086 Emulation)
251
Flags Register

x86 Instruction Set Architecture
252

Chapter 8: Real Mode (8086 Emulation)
253

x86 Instruction Set Architecture
254

Chapter 8: Real Mode (8086 Emulation)
255
General Purpose Registers (GPRs)
A, B, C and D Registers

x86 Instruction Set Architecture
256
EBP Register: Stack Frame Address Register

Chapter 8: Real Mode (8086 Emulation)
257

x86 Instruction Set Architecture
258
Index Registers

Chapter 8: Real Mode (8086 Emulation)
259
Stack Pointer (SP) Register
Instruction Pointer Register

x86 Instruction Set Architecture
260
Kernel Registers
x87/MMX FPU Register Set

Chapter 8: Real Mode (8086 Emulation)
261

x86 Instruction Set Architecture
262
SSE Register Set
Debug Address Breakpoint Register Set
General

Chapter 8: Real Mode (8086 Emulation)
263
Defining Trigger Address Range

x86 Instruction Set Architecture
264
Defining Access Type
Defining Scope (Current Task or All Tasks)
Special Notes

Chapter 8: Real Mode (8086 Emulation)
265

x86 Instruction Set Architecture
266

Chapter 8: Real Mode (8086 Emulation)
267

x86 Instruction Set Architecture
268

Chapter 8: Real Mode (8086 Emulation)
269
Local APIC Register Set

x86 Instruction Set Architecture
270

Chapter 8: Real Mode (8086 Emulation)
271

x86 Instruction Set Architecture
272
Architecturally-Defined MSRs
General
Determining MSR Support
Accessing the MSRs

Chapter 8: Real Mode (8086 Emulation)
273

x86 Instruction Set Architecture
274

Chapter 8: Real Mode (8086 Emulation)
275

x86 Instruction Set Architecture
276

Chapter 8: Real Mode (8086 Emulation)
277

x86 Instruction Set Architecture
278

Chapter 8: Real Mode (8086 Emulation)
279

x86 Instruction Set Architecture
280

Chapter 8: Real Mode (8086 Emulation)
281
IO Space versus Memory Space
IO Operations
IO Operations in IO Address Space
IN and OUT Instructions

x86 Instruction Set Architecture
282
Block (String) IO Operations

Chapter 8: Real Mode (8086 Emulation)
283

x86 Instruction Set Architecture
284
IO Space is Limited and Crowded
Memory-Mapped IO (MMIO) Operations
Introduction
Know the Characteristics of Your Target
Why the Logical Processor Must Know the Memory Type

Chapter 8: Real Mode (8086 Emulation)
285
Uncacheable (UC) Memory

x86 Instruction Set Architecture
286
No IO Protection
Operand Size Selection

Chapter 8: Real Mode (8086 Emulation)
287
Address Size Selection

x86 Instruction Set Architecture
288
Real Mode Memory Addressing
No Address Translation
Introduction to Real Mode Segmentation

Chapter 8: Real Mode (8086 Emulation)
289

x86 Instruction Set Architecture
290

Chapter 8: Real Mode (8086 Emulation)
291

x86 Instruction Set Architecture
292
All Segments are 64KB in Size

Chapter 8: Real Mode (8086 Emulation)
293
Memory Address Representation
Accessing the Code Segment

x86 Instruction Set Architecture
294
Jumping Between Code Segments
Far Jumps and Calls

Chapter 8: Real Mode (8086 Emulation)
295
Near Jumps and Calls

x86 Instruction Set Architecture
296
IP-Relative Branches
Operations That Default to the Code Segment

Chapter 8: Real Mode (8086 Emulation)
297
Accessing the Stack Segment
Introduction

x86 Instruction Set Architecture
298
Stack Characteristics
Pushing Data Onto the Stack

Chapter 8: Real Mode (8086 Emulation)
299

x86 Instruction Set Architecture
300
Popping Data From the Stack
Stack Underflow/Overflow

Chapter 8: Real Mode (8086 Emulation)
301
Processor Stack Usage
Accessing Parameters Passed on the Stack

x86 Instruction Set Architecture
302
Operations That Default To the Stack Segment

Chapter 8: Real Mode (8086 Emulation)
303
Accessing the DS Data Segment
General
Operations That Default to the DS Data Segment

x86 Instruction Set Architecture
304
Accessing the ES/FS/GS Data Segments
General

Chapter 8: Real Mode (8086 Emulation)
305
Operations That Default to the ES Data Segment
Segment Override Prefixes
Example Segment Register Initialization

x86 Instruction Set Architecture
306

Chapter 8: Real Mode (8086 Emulation)
307
Accessing Extended Memory in Real Mode

x86 Instruction Set Architecture
308

Chapter 8: Real Mode (8086 Emulation)
309

x86 Instruction Set Architecture
310
Big Real Mode

Chapter 8: Real Mode (8086 Emulation)
311
286 DOS Extender Programs
Hot Reset and 286 DOS Extender Programs

x86 Instruction Set Architecture
312
Alternate (Fast) Hot Reset

Chapter 8: Real Mode (8086 Emulation)
313
286 DOS Extenders on Post-286 Processors

x86 Instruction Set Architecture
314

Chapter 8: Real Mode (8086 Emulation)
315
String Operations

x86 Instruction Set Architecture
316
Real Mode Interrupt/Exception Handling
Events and Event Handlers

Chapter 8: Real Mode (8086 Emulation)
317
Events Are Recognized on an Instruction Boundary
The IDT
Definition of the IDT

x86 Instruction Set Architecture
318

Chapter 8: Real Mode (8086 Emulation)
319

x86 Instruction Set Architecture
320

Chapter 8: Real Mode (8086 Emulation)
321

x86 Instruction Set Architecture
322

Chapter 8: Real Mode (8086 Emulation)
323

x86 Instruction Set Architecture
324
IDT and IDTR Initialization

Chapter 8: Real Mode (8086 Emulation)
325
Stack Initialization

x86 Instruction Set Architecture
326
Event (Interrupt and Exception) Handling

Chapter 8: Real Mode (8086 Emulation)
327
Software Event Types
Introduction

x86 Instruction Set Architecture
328
Software Exceptions

Chapter 8: Real Mode (8086 Emulation)
329

x86 Instruction Set Architecture
330
Software Interrupt Instructions

Chapter 8: Real Mode (8086 Emulation)
331

x86 Instruction Set Architecture
332
Hardware Event Types
NMI

Chapter 8: Real Mode (8086 Emulation)
333

x86 Instruction Set Architecture
334
SMI
Maskable Interrupts

Chapter 8: Real Mode (8086 Emulation)
335

x86 Instruction Set Architecture
336
Machine Check Exception

Chapter 8: Real Mode (8086 Emulation)
337
Summary of Real Mode Limitations
Transitioning to Protected Mode

x86 Instruction Set Architecture
338

339
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
340
The Next Chapter
A Little History

Chapter 9: Legacy x87 FP Support
341
x87 FP Instruction Format
FPU-Related CR0 Bit Fields

x86 Instruction Set Architecture
342

Chapter 9: Legacy x87 FP Support
343
x87 FPU Register Set
The FP Data Registers

x86 Instruction Set Architecture
344
x87 FPUs Native Data Operand Format

Chapter 9: Legacy x87 FP Support
345

x86 Instruction Set Architecture
346
32-bit SP FP Numeric Format
Background
A Brief IEEE FP Primer

Chapter 9: Legacy x87 FP Support
347
The 32-bit SP FP Format

x86 Instruction Set Architecture
348
Representing Special Values
An Example

Chapter 9: Legacy x87 FP Support
349
Another Example

x86 Instruction Set Architecture
350
DP FP Number Representation
FCW Register

Chapter 9: Legacy x87 FP Support
351

x86 Instruction Set Architecture
352
FSW Register

Chapter 9: Legacy x87 FP Support
353

x86 Instruction Set Architecture
354

Chapter 9: Legacy x87 FP Support
355
FTW Register
Instruction Pointer Register
Data Pointer Register

x86 Instruction Set Architecture
356
Fopcode Register
General
Fopcode Compatibility Mode

Chapter 9: Legacy x87 FP Support
357
FP Error Reporting
Precise Error Reporting
Imprecise (Deferred) Error Reporting

x86 Instruction Set Architecture
358
Why Deferred Error Reporting Is Used
The WAIT/FWAIT Instruction
CR0[NE]

Chapter 9: Legacy x87 FP Support
359
DOS-Compatible FP Error Reporting
FP Error Reporting Via Exception 16

x86 Instruction Set Architecture
360
Ignoring FP Errors

361
The Previous Chapter

x86 Instruction Set Architecture
362
This Chapter
The Next Chapter

Chapter 10: Introduction to Multitasking
363
Concept

x86 Instruction Set Architecture
364
An ExampleTimeslicing
Another ExampleAwaiting an Event
1. Task Issues Call to OS for Disk Read
2. Device Driver Initiates Disk Read

Chapter 10: Introduction to Multitasking
365
3. OS Suspends Task
4. OS Makes Entry in Event Queue
5. OS Starts or Resumes Another Task
6. Disk-Generated Interrupt Causes Jump to OS

x86 Instruction Set Architecture
366
7. Interrupted Task Suspended
8. Task Queue Checked
9. OS Resumes Task

367
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
368
The Next Chapter
Hardware-based Task Switching Is Slow!

Chapter 11: Multitasking-Related Issues
369
Private (Local) and Global Memory
Preventing Unauthorized Use of OS Code

x86 Instruction Set Architecture
370
With Privilege Comes Access
Program Privilege Level
The CPL

Chapter 11: Multitasking-Related Issues
371
Calling One of Your Equals
Calling a Procedure to Act as Your Surrogate
Data Segment Protection
Data Segment Privilege Level
Read-Only Data Areas

x86 Instruction Set Architecture
372
Some Code Segments Contain Data, Others Dont

Chapter 11: Multitasking-Related Issues
373

x86 Instruction Set Architecture
374
IO Port Anarchy

Chapter 11: Multitasking-Related Issues
375
No Interrupts, Please!

x86 Instruction Set Architecture
376
BIOS Calls

377
The Previous Chapter

x86 Instruction Set Architecture
378
This Chapter
The Next Chapter
Protection-Related Mechanisms

Chapter 12: Summary of the Protection Mechanisms
379

x86 Instruction Set Architecture
380

Chapter 12: Summary of the Protection Mechanisms
381

x86 Instruction Set Architecture
382

383
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
384
Real Mode Segment Limitations

Chapter 13: Protected Mode Memory Addressing
385
An Important Reminder: Segment Base + Offset = Virtual
Address

x86 Instruction Set Architecture
386
Descriptor Contains Detailed Segment Description
Segment RegisterSelects Descriptor Table and Entry

Chapter 13: Protected Mode Memory Addressing
387

x86 Instruction Set Architecture
388

Chapter 13: Protected Mode Memory Addressing
389

x86 Instruction Set Architecture
390
Introduction to the Descriptor Tables
Segment Descriptors Reside in Memory

Chapter 13: Protected Mode Memory Addressing
391

x86 Instruction Set Architecture
392

Chapter 13: Protected Mode Memory Addressing
393
Global Descriptor Table (GDT)
GDT Description
Setting the GDT Base Address and Size

x86 Instruction Set Architecture
394
GDT Entry 0

Chapter 13: Protected Mode Memory Addressing
395
Local Descriptor Tables (LDTs)
General

x86 Instruction Set Architecture
396
Creating and Selecting an LDT

Chapter 13: Protected Mode Memory Addressing
397

x86 Instruction Set Architecture
398

Chapter 13: Protected Mode Memory Addressing
399
General Segment Descriptor Format
Granularity Bit and the Segment Size

x86 Instruction Set Architecture
400
Segment Base Address Field
Default/Big Bit
In a Code Segment Descriptor, D/B = Default Bit

Chapter 13: Protected Mode Memory Addressing
401
Override Prefixes

x86 Instruction Set Architecture
402
In a Stack Segment Descriptor, D/B = Big Bit

Chapter 13: Protected Mode Memory Addressing
403
Segment Type Field
Introduction to the Type Field
Non-System Segment Types

x86 Instruction Set Architecture
404

Chapter 13: Protected Mode Memory Addressing
405

x86 Instruction Set Architecture
406
Segment Present Bit
Descriptor Privilege Level (DPL) Field

Chapter 13: Protected Mode Memory Addressing
407
System Bit

x86 Instruction Set Architecture
408
Available Bit
Goodbye to Segmentation
Introduction

Chapter 13: Protected Mode Memory Addressing
409
IA-32 Flat Memory Model

x86 Instruction Set Architecture
410

Chapter 13: Protected Mode Memory Addressing
411

x86 Instruction Set Architecture
412
No Protection? Paging Takes Care of It
A Reminder of Where We Are

Chapter 13: Protected Mode Memory Addressing
413

x86 Instruction Set Architecture
414

415
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
416
The Next Chapter
Abbreviation Alert
Selecting the Active Code Segment

Chapter 14: Code, Calls and Privilege Checks
417

x86 Instruction Set Architecture
418
CS Descriptor
CS Descriptor Selector

Chapter 14: Code, Calls and Privilege Checks
419
Calculating the Descriptors Memory Address
Descriptor Read and Privilege Checked
CS Descriptor Format

x86 Instruction Set Architecture
420

Chapter 14: Code, Calls and Privilege Checks
421

x86 Instruction Set Architecture
422

Chapter 14: Code, Calls and Privilege Checks
423
Accessing the Code Segment
In-Line Code Fetching
Short and Near Branches (Jumps and Calls)
General

x86 Instruction Set Architecture
424
Example Near Jump
Far Branches (Far Jumps and Calls)
General

Chapter 14: Code, Calls and Privilege Checks
425
Example Far Jump

x86 Instruction Set Architecture
426

Chapter 14: Code, Calls and Privilege Checks
427
Short/Near Jumps
General
No Privilege Check
Unconditional Short/Near Branches

x86 Instruction Set Architecture
428
Conditional Branches
General

Chapter 14: Code, Calls and Privilege Checks
429

x86 Instruction Set Architecture
430

Chapter 14: Code, Calls and Privilege Checks
431
Loop Instructions

x86 Instruction Set Architecture
432

Chapter 14: Code, Calls and Privilege Checks
433

x86 Instruction Set Architecture
434
Unconditional Far Jumps
The Privilege Check

Chapter 14: Code, Calls and Privilege Checks
435
Far Jump Targets
Far Jump Forms

x86 Instruction Set Architecture
436
Privilege Checking
No Check on Near Calls or Near Jumps

Chapter 14: Code, Calls and Privilege Checks
437
General
Definitions
Definition of a Task
Definition of a Procedure
CPL Definition

x86 Instruction Set Architecture
438
CS DPL Definition
Conforming and Non-Conforming Code Segments

Chapter 14: Code, Calls and Privilege Checks
439
RPL Definition

x86 Instruction Set Architecture
440
Privilege Check on Far Call or Far Jmp
General
Example

Chapter 14: Code, Calls and Privilege Checks
441
Jumping from a Higher-to-Lesser Privileged Program

x86 Instruction Set Architecture
442
Direct Procedure Calls
Introduction
General

Chapter 14: Code, Calls and Privilege Checks
443
Near Calls/Returns
Description

x86 Instruction Set Architecture
444

Chapter 14: Code, Calls and Privilege Checks
445
Call/Ret Operand Size Matching
Near Call/Return Forms

x86 Instruction Set Architecture
446

Chapter 14: Code, Calls and Privilege Checks
447
Far Calls
General
Far Call Forms

x86 Instruction Set Architecture
448

Chapter 14: Code, Calls and Privilege Checks
449

x86 Instruction Set Architecture
450

Chapter 14: Code, Calls and Privilege Checks
451
Far Call, Same Privilege Level
Far Call to a More-Privileged Procedure

x86 Instruction Set Architecture
452
Far Call to a Procedure in a Different Task
Indirect Procedure Far Call Through a Call Gate
Example Scenario Defines the Problem
The Scenario

Chapter 14: Code, Calls and Privilege Checks
453
The Problem

x86 Instruction Set Architecture
454
The SolutionDifferent Gateways
The Call Gate Descriptor

Chapter 14: Code, Calls and Privilege Checks
455

x86 Instruction Set Architecture
456
Call Gate Example
Execution Begins

Chapter 14: Code, Calls and Privilege Checks
457
Call Gate Descriptor Read

x86 Instruction Set Architecture
458
Call Gate Contains Target Code Segment Selector

Chapter 14: Code, Calls and Privilege Checks
459
Target Code Segment Descriptor Read

x86 Instruction Set Architecture
460

Chapter 14: Code, Calls and Privilege Checks
461
The Big Picture
The Call Gate Privilege Check

x86 Instruction Set Architecture
462
Automatic Stack Switch
Background
A Potential Problem
The Solution: Pre-Allocated Stacks

Chapter 14: Code, Calls and Privilege Checks
463

x86 Instruction Set Architecture
464

Chapter 14: Code, Calls and Privilege Checks
465

x86 Instruction Set Architecture
466
Far Call From 32-bit CS to 16-bit CS
General
Method 1: Far Call with Operand Size Override Prefix

Chapter 14: Code, Calls and Privilege Checks
467
Method 2: Far Call Via 16-bit Call Gate

x86 Instruction Set Architecture
468

Chapter 14: Code, Calls and Privilege Checks
469

x86 Instruction Set Architecture
470
Method 3: Call 32-bit/16-bit Interface Procedure

Chapter 14: Code, Calls and Privilege Checks
471
Far Call From 16-bit CS to 32-bit CS

x86 Instruction Set Architecture
472
Method 1: Far Call With an Operand Size Prefix

Chapter 14: Code, Calls and Privilege Checks
473
Method 2: Far Call Via a 32-bit Call Gate

x86 Instruction Set Architecture
474

Chapter 14: Code, Calls and Privilege Checks
475
Far Returns
General

x86 Instruction Set Architecture
476
Far Return Forms

Chapter 14: Code, Calls and Privilege Checks
477

x86 Instruction Set Architecture
478

479
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
480
The Next Chapter
A Note Regarding Stack Segments

Chapter 15: Data and Stack Segments
481
Data Segments
General
Two-Step Permission Check

x86 Instruction Set Architecture
482
An Example

Chapter 15: Data and Stack Segments
483

x86 Instruction Set Architecture
484
Selecting and Accessing a Stack Segment
Introduction

Chapter 15: Data and Stack Segments
485
Expand-Up Stack

x86 Instruction Set Architecture
486

Chapter 15: Data and Stack Segments
487
Expand-Down Stack
The Problem

x86 Instruction Set Architecture
488

Chapter 15: Data and Stack Segments
489
Expand-Down Stack Description

x86 Instruction Set Architecture
490
An Example

Chapter 15: Data and Stack Segments
491
Another Example

x86 Instruction Set Architecture
492

493
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
494
The Next Chapter
Three Generations

Chapter 16: IA-32 Address Translation Mechanisms
495
Demand Mode Paging Evolution

x86 Instruction Set Architecture
496
Background
Memory and Disk: Block-Oriented Devices
Definition of a Page

Chapter 16: IA-32 Address Translation Mechanisms
497
Example Scenario: Block Transfer from Disk to
Memory

x86 Instruction Set Architecture
498
A Poor Memory Allocation Strategy

Chapter 16: IA-32 Address Translation Mechanisms
499
Applications Are Presented With a Simplified World-View
Introduction
Life Without Paging Would Be Chaotic

x86 Instruction Set Architecture
500
The Virtual World Is a Simple One

Chapter 16: IA-32 Address Translation Mechanisms
501

x86 Instruction Set Architecture
502

Chapter 16: IA-32 Address Translation Mechanisms
503

x86 Instruction Set Architecture
504

Chapter 16: IA-32 Address Translation Mechanisms
505

x86 Instruction Set Architecture
506
Virtual Address Space Partitioning

Chapter 16: IA-32 Address Translation Mechanisms
507

x86 Instruction Set Architecture
508
Example Virtual Buffer Allocation

Chapter 16: IA-32 Address Translation Mechanisms
509
Address Translation Advantages
Introduction
Simplifies Memory Management

x86 Instruction Set Architecture
510
Efficient Memory Usage
A Wasteful Approach

Chapter 16: IA-32 Address Translation Mechanisms
511
A Better Approach: Load On Demand
Attribute Assignment

x86 Instruction Set Architecture
512
Track Access History
Allows DOS Applications to Co-Exist
Problem: Running Multiple DOS Programs
Solution: Address Redirection

Chapter 16: IA-32 Address Translation Mechanisms
513
First-Generation Paging
Definition of First Generation Paging

x86 Instruction Set Architecture
514
Paging Logics Interpretation of a Virtual Address

Chapter 16: IA-32 Address Translation Mechanisms
515
First-Generation Paging Overview
The Set-Up

x86 Instruction Set Architecture
516
Virtual-to-Physical Address Translation

Chapter 16: IA-32 Address Translation Mechanisms
517

x86 Instruction Set Architecture
518

Chapter 16: IA-32 Address Translation Mechanisms
519

x86 Instruction Set Architecture
520

Chapter 16: IA-32 Address Translation Mechanisms
521

x86 Instruction Set Architecture
522
Two Overhead Memory Reads Take a Toll

Chapter 16: IA-32 Address Translation Mechanisms
523
The TLBs
TLB Miss

x86 Instruction Set Architecture
524
TLB Hit
TLB Maintenance

Chapter 16: IA-32 Address Translation Mechanisms
525
TLBs Are Cleared on Task Switch or Page Directory Change
Updating a Single Page Table Entry

x86 Instruction Set Architecture
526
Global Pages
Problem
Global Page Feature

Chapter 16: IA-32 Address Translation Mechanisms
527
Enabling Paging

x86 Instruction Set Architecture
528

Chapter 16: IA-32 Address Translation Mechanisms
529
Detailed Description of PDE and PTE
PDE Layout

x86 Instruction Set Architecture
530

Chapter 16: IA-32 Address Translation Mechanisms
531
PTE Layout

x86 Instruction Set Architecture
532

Chapter 16: IA-32 Address Translation Mechanisms
533

x86 Instruction Set Architecture
534

Chapter 16: IA-32 Address Translation Mechanisms
535
Checking Page Access Permission
The Privilege Check
Segment Privilege Check Takes Precedence Over Page Check

x86 Instruction Set Architecture
536
U/S Bit in PDE and PTE Are Checked

Chapter 16: IA-32 Address Translation Mechanisms
537
Accesses with Special Privilege
The Read/Write Check

x86 Instruction Set Architecture
538
Missing Page or Page Table
Introduction
Page Table Not Present

Chapter 16: IA-32 Address Translation Mechanisms
539

x86 Instruction Set Architecture
540

Chapter 16: IA-32 Address Translation Mechanisms
541

x86 Instruction Set Architecture
542
Page Not Present

Chapter 16: IA-32 Address Translation Mechanisms
543

x86 Instruction Set Architecture
544

Chapter 16: IA-32 Address Translation Mechanisms
545
Page Faults
Page Fault Causes

x86 Instruction Set Architecture
546
Page Fault During a Task Switch

Chapter 16: IA-32 Address Translation Mechanisms
547
Page Fault while Changing to a Different Stack
Page Fault Error Code
Additional Page Fault Information

x86 Instruction Set Architecture
548
Access History

Chapter 16: IA-32 Address Translation Mechanisms
549

x86 Instruction Set Architecture
550
4MB Pages
Basic Concept
Enabling the PSE Feature
Simplifies Housekeeping

Chapter 16: IA-32 Address Translation Mechanisms
551
How To Set Up a 4MB Page

x86 Instruction Set Architecture
552
The Address Translation

Chapter 16: IA-32 Address Translation Mechanisms
553
Second-Generation Paging
First-Gen Problem: 4GB Physical Memory
The Solution: PAE-36 Mode
Enabling PAE-36 Mode

x86 Instruction Set Architecture
554
CR4[PSE] Is Dont Care
Application Still Limited to a 4GB Virtual Address
Space

Chapter 16: IA-32 Address Translation Mechanisms
555
Virtual Address Space Partitioning
First Generation Partitioning

x86 Instruction Set Architecture
556
Second Generation Partitioning

Chapter 16: IA-32 Address Translation Mechanisms
557
Second Generation Uses 3-Level Lookup Mechanism

x86 Instruction Set Architecture
558
CR3 Points to PDPT in Lower 4GB

Chapter 16: IA-32 Address Translation Mechanisms
559
Enlarged Physical Address Space

x86 Instruction Set Architecture
560
The Translation
Step 1: PDPT Lookup

Chapter 16: IA-32 Address Translation Mechanisms
561

x86 Instruction Set Architecture
562
Step 2: Page Directory Lookup

Chapter 16: IA-32 Address Translation Mechanisms
563

x86 Instruction Set Architecture
564

Chapter 16: IA-32 Address Translation Mechanisms
565
Step 3: Page Table Lookup

x86 Instruction Set Architecture
566

Chapter 16: IA-32 Address Translation Mechanisms
567
Page Protection Mechanisms
General

x86 Instruction Set Architecture
568
Write-Protection

Chapter 16: IA-32 Address Translation Mechanisms
569
Example Usage: Unix Copy-on-Write Strategy

x86 Instruction Set Architecture
570

Chapter 16: IA-32 Address Translation Mechanisms
571
3-Level LookupIncreased TLB Size

x86 Instruction Set Architecture
572
Microsoft PAE Support

Chapter 16: IA-32 Address Translation Mechanisms
573

x86 Instruction Set Architecture
574
Linux PAE Support
PSE-36 Mode (PAE-36 Modes Poor Cousin)

Chapter 16: IA-32 Address Translation Mechanisms
575
PSE-36 Mode Background
Detecting PSE-36 Mode Capability
Enabling PSE-36 Mode

x86 Instruction Set Architecture
576
Per Application Virtual Memory Space = 4GB
First-Generation Lookup Mechanism
Selected PDE Can Point to 4KB Page Table or a 4MB
Page

Chapter 16: IA-32 Address Translation Mechanisms
577
Virtual Address Maps to a 4MB Page in 64GB Space

x86 Instruction Set Architecture
578
Windows and PSE-36

Chapter 16: IA-32 Address Translation Mechanisms
579
AMD Enhanced PSE-36 to PSE-40
Execute Disable Feature
Problem: Malicious Code
The Overflow

x86 Instruction Set Architecture
580

Chapter 16: IA-32 Address Translation Mechanisms
581
The Exploit

x86 Instruction Set Architecture
582
The Fix: Intercept Code Fetches from Data Pages
Enabling the Execute-Disable Feature

Chapter 16: IA-32 Address Translation Mechanisms
583
Available in both IA-32 and IA-32e Mode
How It Works

x86 Instruction Set Architecture
584

Chapter 16: IA-32 Address Translation Mechanisms
585
Defining a Pages Caching Rules
Introduction
Translation Table Caching Rules
General

x86 Instruction Set Architecture
586
First-Generation Paging Tables
Second-Generation Paging Tables

Chapter 16: IA-32 Address Translation Mechanisms
587
Page Caching Rules
PAT Feature (Page Attribute Table)
Whats the Problem?

x86 Instruction Set Architecture
588
Detecting PAT Support
PAT Allows More Memory Types

Chapter 16: IA-32 Address Translation Mechanisms
589
Default Contents of IA32_CR_PAT MSR

x86 Instruction Set Architecture
590
Memory Type When Page Definition and MTRR
Disagree

Chapter 16: IA-32 Address Translation Mechanisms
591

x86 Instruction Set Architecture
592

Chapter 16: IA-32 Address Translation Mechanisms
593
Altering IA32_CR_PAT MSR
Ensuring IA32_CR_PAT and MTRR Consistency

x86 Instruction Set Architecture
594

Chapter 16: IA-32 Address Translation Mechanisms
595
Assigning Multiple Memory Types to a Single
Physical Page

x86 Instruction Set Architecture
596
Compatibility with Earlier IA-32 Processors

Chapter 16: IA-32 Address Translation Mechanisms
597
Third Generation Paging

x86 Instruction Set Architecture
598

599
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
600
The Next Chapter
Characteristics of Memory Targets
Introduction
Example Problem: Caching from MMIO

Chapter 17: Memory Type Configuration
601
Early Processors Implemented Primitive Mechanism

x86 Instruction Set Architecture
602
Solution/Problem: Chipset Memory Type Registers
Solution: Memory Type Register Set

Chapter 17: Memory Type Configuration
603
MTRR Feature Determination

x86 Instruction Set Architecture
604
MTRRs Are Divided Into Four Categories
MTRRDefType Register

Chapter 17: Memory Type Configuration
605
State of the MTRRs after Reset
Fixed-Range MTRRs
The Problem: Legacy Issues
Enabling the Fixed-Range MTRRs

x86 Instruction Set Architecture
606
Defining Memory Types in Lower 1MB

Chapter 17: Memory Type Configuration
607
Variable-Range MTRRs
How Many Variable-Range Register Pairs?
Variable-Range Register Pair Format

x86 Instruction Set Architecture
608
MTRRPhysBasen Register
MTRRPhysMaskn Register

Chapter 17: Memory Type Configuration
609
Programming Variable-Range Register Pairs
Enabling Variable-Range Register Pairs
Memory Types
Memory Type Defines Processor Aggressiveness

x86 Instruction Set Architecture
610
Five Memory Types
Uncacheable (UC) Memory

Chapter 17: Memory Type Configuration
611
Uncacheable Write-Combining (WC) Memory
Description

x86 Instruction Set Architecture
612
Weakly-Ordered Writes
Cacheable Write-Protect (WP) Memory

Chapter 17: Memory Type Configuration
613
Cacheable Write-Through (WT) Memory

x86 Instruction Set Architecture
614
Cacheable Write-Back (WB) Memory

Chapter 17: Memory Type Configuration
615
The Definition of a Speculatively Executed Load

x86 Instruction Set Architecture
616
Rules as Defined by MTRRs

Chapter 17: Memory Type Configuration
617
Memory Type Provided in Memory Transaction
Paging Also Defines Memory Type

x86 Instruction Set Architecture
618
In an MP System, MTRRs Must Be Synchronized
Posted-Write Related Issues
General
Synchronizing Events

Chapter 17: Memory Type Configuration
619
PMWB and WCBs Arent Snooped

x86 Instruction Set Architecture
620
WCB Usage
An Example

Chapter 17: Memory Type Configuration
621

x86 Instruction Set Architecture
622

Chapter 17: Memory Type Configuration
623

x86 Instruction Set Architecture
624

Chapter 17: Memory Type Configuration
625

x86 Instruction Set Architecture
626

Chapter 17: Memory Type Configuration
627
All WCBs in Use

x86 Instruction Set Architecture
628
Draining the WCBs

629
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
630
The Next Chapter
Hardware- vs. Software-Based Task Switching

Chapter 18: Task Switching
631
A Condensed Conceptual Overview
A More Comprehensive Overview
The Scheduler and the Task Queue

x86 Instruction Set Architecture
632
Setting Up a Task
The Task Data Structure

Chapter 18: Task Switching
633
The LDT
The TSS

x86 Instruction Set Architecture
634
The Address Translation Tables

Chapter 18: Task Switching
635
The GDT and GDTR Register

x86 Instruction Set Architecture
636
The LDTR Register

Chapter 18: Task Switching
637
The Task Register (TR)

x86 Instruction Set Architecture
638
Starting a Task

Chapter 18: Task Switching
639
Suspend Task and Resume Scheduler
Execution

x86 Instruction Set Architecture
640

Chapter 18: Task Switching
641
Hardware-Based Task Switching
Its Slow

x86 Instruction Set Architecture
642
Why Didnt OSs Use It?
Why Wasnt It Improved?
Why Does It Still Exist?
Introduction to the Key Elements

Chapter 18: Task Switching
643

x86 Instruction Set Architecture
644

Chapter 18: Task Switching
645

x86 Instruction Set Architecture
646
The Trigger Events

Chapter 18: Task Switching
647

x86 Instruction Set Architecture
648
The Descriptors
TSS Descriptor

Chapter 18: Task Switching
649
Task Gate Descriptor

x86 Instruction Set Architecture
650

Chapter 18: Task Switching
651

x86 Instruction Set Architecture
652
The Task Register
General
TR Instruction Pair

Chapter 18: Task Switching
653

x86 Instruction Set Architecture
654
TSS Data Structure Format
General

Chapter 18: Task Switching
655
Required Fields
Optional Fields

x86 Instruction Set Architecture
656
Register Snapshot Area

Chapter 18: Task Switching
657

x86 Instruction Set Architecture
658

Chapter 18: Task Switching
659
Debug Trap Bit (T)
IO Port Access Protection

x86 Instruction Set Architecture
660

Chapter 18: Task Switching
661
IO Permission Bit Map

x86 Instruction Set Architecture
662

Chapter 18: Task Switching
663

x86 Instruction Set Architecture
664
Interrupt Redirection Bit Map
OS-Specific Data Structures
Privilege Level 0 - 2 Stack Definition Fields

Chapter 18: Task Switching
665
Link Field (to Old TSS Selector)
Comprehensive Task Switch Description

x86 Instruction Set Architecture
666

Chapter 18: Task Switching
667

x86 Instruction Set Architecture
668

Chapter 18: Task Switching
669

x86 Instruction Set Architecture
670
Calling Another Task
An Overview

Chapter 18: Task Switching
671
A Comprehensive Example

x86 Instruction Set Architecture
672

Chapter 18: Task Switching
673

x86 Instruction Set Architecture
674

Chapter 18: Task Switching
675

x86 Instruction Set Architecture
676

Chapter 18: Task Switching
677
LTR Instruction and the Busy Bit
When Is Busy Cleared?
Critical Error: Switching to a Busy Task

x86 Instruction Set Architecture
678
Busy Toggle Is a Locked Operation
Linkage Modification
Task Switching and Address Translation
One GDT to Serve Them All

Chapter 18: Task Switching
679
Each Task Can Have Different Virtual-to-Physical Mapping
TSS Mapping Must Remain the Same for All Tasks

x86 Instruction Set Architecture
680
Placement of a TSS Within a Page(s)
Switch from More-Privileged Code to Lower
Software-Based Task Switching

681
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
682
The Next Chapter
Handler vs. ISR

Chapter 19: Protected Mode Interrupts and Exceptions
683
Real Mode Interrupt/Exception Handling

x86 Instruction Set Architecture
684
The IDT
General

Chapter 19: Protected Mode Interrupts and Exceptions
685
Protected Mode IDT and the IDTR

x86 Instruction Set Architecture
686

Chapter 19: Protected Mode Interrupts and Exceptions
687

x86 Instruction Set Architecture
688
The Gates
Introduction

Chapter 19: Protected Mode Interrupts and Exceptions
689

x86 Instruction Set Architecture
690

Chapter 19: Protected Mode Interrupts and Exceptions
691
Interrupt Gate

x86 Instruction Set Architecture
692

Chapter 19: Protected Mode Interrupts and Exceptions
693
Trap Gate

x86 Instruction Set Architecture
694
Actions Taken When Interrupt or Trap Gate Selected

Chapter 19: Protected Mode Interrupts and Exceptions
695

x86 Instruction Set Architecture
696
Actions Taken When Task Gate Selected

Chapter 19: Protected Mode Interrupts and Exceptions
697
Interrupt/Exception Event Categories

x86 Instruction Set Architecture
698

Chapter 19: Protected Mode Interrupts and Exceptions
699
General Event Handling

x86 Instruction Set Architecture
700

Chapter 19: Protected Mode Interrupts and Exceptions
701

x86 Instruction Set Architecture
702

Chapter 19: Protected Mode Interrupts and Exceptions
703

x86 Instruction Set Architecture
704
State Saved on Stack (but which stack?)

Chapter 19: Protected Mode Interrupts and Exceptions
705

x86 Instruction Set Architecture
706

Chapter 19: Protected Mode Interrupts and Exceptions
707

x86 Instruction Set Architecture
708
Return to the Interrupted Program
General

Chapter 19: Protected Mode Interrupts and Exceptions
709
The IRET Instruction

x86 Instruction Set Architecture
710

Chapter 19: Protected Mode Interrupts and Exceptions
711

x86 Instruction Set Architecture
712

Chapter 19: Protected Mode Interrupts and Exceptions
713
Maskable Hardware Interrupts
General
Maskable Interrupt Vector Delivery

x86 Instruction Set Architecture
714
PC-Compatible Vector Assignment

Chapter 19: Protected Mode Interrupts and Exceptions
715

x86 Instruction Set Architecture
716

Chapter 19: Protected Mode Interrupts and Exceptions
717

x86 Instruction Set Architecture
718

Chapter 19: Protected Mode Interrupts and Exceptions
719
Actions Performed by the Handler

x86 Instruction Set Architecture
720
Effect of CLI/STI Execution
General

Chapter 19: Protected Mode Interrupts and Exceptions
721

x86 Instruction Set Architecture
722
Other Events That Affect Interrupt Flag Bit

Chapter 19: Protected Mode Interrupts and Exceptions
723
Protected Mode Virtual Interrupt Feature
Non-Maskable Interrupt (NMI) Requests
PC-Compatible NMI Logic
NMI Description

x86 Instruction Set Architecture
724
More Detailed Coverage of Hardware Interrupt Handling
Machine Check Exception

Chapter 19: Protected Mode Interrupts and Exceptions
725
SMI (System Management Interrupt)
Software Interrupts

x86 Instruction Set Architecture
726
INT nn Instruction
INTO Instruction

Chapter 19: Protected Mode Interrupts and Exceptions
727
BOUND Instruction
INT3 (Breakpoint) Instruction

x86 Instruction Set Architecture
728
Software Exceptions
General
Faults, Traps, and Aborts

Chapter 19: Protected Mode Interrupts and Exceptions
729

x86 Instruction Set Architecture
730

Chapter 19: Protected Mode Interrupts and Exceptions
731

x86 Instruction Set Architecture
732

Chapter 19: Protected Mode Interrupts and Exceptions
733

x86 Instruction Set Architecture
734

Chapter 19: Protected Mode Interrupts and Exceptions
735
Instruction Restart After a Fault
Exception Error Codes

x86 Instruction Set Architecture
736

Chapter 19: Protected Mode Interrupts and Exceptions
737

x86 Instruction Set Architecture
738

Chapter 19: Protected Mode Interrupts and Exceptions
739
Interrupt/Exception Priority

x86 Instruction Set Architecture
740

Chapter 19: Protected Mode Interrupts and Exceptions
741

x86 Instruction Set Architecture
742

Chapter 19: Protected Mode Interrupts and Exceptions
743
Detailed Description of Software Exceptions
Divide-by-Zero Exception (0)
Processor Introduced In
Exception Class
Description
Error Code
Saved Instruction Pointer
Processor State

x86 Instruction Set Architecture
744
Debug Exception (1)
Processor Introduced In
Exception Class
Description

Chapter 19: Protected Mode Interrupts and Exceptions
745
Error Code
Saved Instruction Pointer
Processor State
The Resume Flag Prevents Multiple Debug Exceptions

x86 Instruction Set Architecture
746
NMI (2)
Processor Introduced In
Exception Class
Error Code
Saved Instruction Pointer
Processor State
Breakpoint Exception (3)
Processor Introduced In

Chapter 19: Protected Mode Interrupts and Exceptions
747
Exception Class
Description
Error Code
Saved Instruction Pointer
Processor State

x86 Instruction Set Architecture
748
Overflow Exception (4)
Processor Introduced In
Exception Class
Description
Error Code
Saved Instruction Pointer
Processor State
Array Bounds Check Exception (5)
Processor Introduced In

Chapter 19: Protected Mode Interrupts and Exceptions
749
Exception Class
Description
Error Code
Saved Instruction Pointer
Processor State
Invalid OpCode Exception (6)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
750
Error Code
Saved Instruction Pointer

Chapter 19: Protected Mode Interrupts and Exceptions
751
Processor State
Device Not Available (DNA) Exception (7)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
752
Error Code
Saved Instruction Pointer
Processor State
Double Fault Exception (8)
Processor Introduced In
Exception Class

Chapter 19: Protected Mode Interrupts and Exceptions
753
Description

x86 Instruction Set Architecture
754

Chapter 19: Protected Mode Interrupts and Exceptions
755
Shutdown Mode

x86 Instruction Set Architecture
756
Error Code
Saved Instruction Pointer
Processor State
Coprocessor Segment Overrun Exception (9)
Processor Introduced In
Exception Class
Description
Error Code
Saved Instruction Pointer

Chapter 19: Protected Mode Interrupts and Exceptions
757
Processor State
Invalid TSS Exception (10)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
758
Error Code

Chapter 19: Protected Mode Interrupts and Exceptions
759
Saved Instruction Pointer
Processor State
Segment Not Present Exception (11)
Processor Introduced In
Exception Class

x86 Instruction Set Architecture
760
Description
Error Code
Saved Instruction Pointer

Chapter 19: Protected Mode Interrupts and Exceptions
761
Processor State
Stack Exception (12)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
762
Error Code
Saved Instruction Pointer

Chapter 19: Protected Mode Interrupts and Exceptions
763
Processor State
General Protection (GP) Exception (13)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
764

Chapter 19: Protected Mode Interrupts and Exceptions
765
Error Code
Saved Instruction Pointer

x86 Instruction Set Architecture
766
Processor State
Page Fault Exception (14)
Processor Introduced In
Exception Class
Description

Chapter 19: Protected Mode Interrupts and Exceptions
767
Error Code

x86 Instruction Set Architecture
768
CR2
Saved Instruction Pointer
Processor State

Chapter 19: Protected Mode Interrupts and Exceptions
769
Page Fault During a Stack Switch

x86 Instruction Set Architecture
770
Vector (Exception) 15
FPU Exception (16)
Processor Introduced In
Exception Class
Description

Chapter 19: Protected Mode Interrupts and Exceptions
771
Handling of Masked Errors

x86 Instruction Set Architecture
772
Handling of Unmasked Errors

Chapter 19: Protected Mode Interrupts and Exceptions
773
Error Code
Saved Instruction Pointer
Processor State

x86 Instruction Set Architecture
774
Alignment Check Exception (17)
Processor Introduced In
Background: Misaligned Transfers Affect Performance
Alignment Is Important!

Chapter 19: Protected Mode Interrupts and Exceptions
775
Exception Class
Description

x86 Instruction Set Architecture
776
Implicit Privilege Level 0 Accesses
Storing GDTR, LDTR, IDTR or TR

Chapter 19: Protected Mode Interrupts and Exceptions
777
FP/MMX/SSE Save and Restore Accesses
MOVUPS and MOVUPD Accesses
FSAVE and FRSTOR Accesses
Error Code
Saved Instruction Pointer

x86 Instruction Set Architecture
778
Processor State
Machine Check Exception (18)
Processor Introduced In
Exception Class
Description
Error Code

Chapter 19: Protected Mode Interrupts and Exceptions
779
Saved Instruction Pointer
Processor State
SIMD Floating-Point Exception (19)
Processor Introduced In
Exception Class
Description

x86 Instruction Set Architecture
780

Chapter 19: Protected Mode Interrupts and Exceptions
781

x86 Instruction Set Architecture
782
Exception Error Code
Saved Instruction Pointer
Processor State
Legacy Problem: 2-Step SS:ESP Update
Problem Description
The Solution

783
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
784
The Next Chapter
A Special Note
Real Mode Applications Are Dangerous

Chapter 20: Virtual 8086 Mode
785
Solution: a Watchdog

x86 Instruction Set Architecture
786

Chapter 20: Virtual 8086 Mode
787
Real Mode Applications Run at Privilege Level 3
Switching Between Protected Mode and VM86 Mode
Eflags[VM] = 1 Switches Processor into VM86 Mode

x86 Instruction Set Architecture
788
But Software Cannot Directly Access Eflags[VM]
Scheduler Activates VM86 Mode

Chapter 20: Virtual 8086 Mode
789
Exiting VM86 Mode
Determining Interrupted Task Is a Real Mode Task

x86 Instruction Set Architecture
790
Returning to VM86 Mode from VMM
VMM Passes Control to Real Mode Interrupt/Excep-
tion Handler
Real Mode Applications World View
The DOS World

Chapter 20: Virtual 8086 Mode
791

x86 Instruction Set Architecture
792
Memory Address Formation in VM86 Mode

Chapter 20: Virtual 8086 Mode
793
Multiple DOS Domains in Separate 1MB Areas

x86 Instruction Set Architecture
794

Chapter 20: Virtual 8086 Mode
795
VMM Should Not Reside in the HMA

x86 Instruction Set Architecture
796
Dealing with Segment Wraparound
8088/8086 Processor
286 and Later Processors
Solutions

Chapter 20: Virtual 8086 Mode
797
Using the Address Size Override Prefix
Sensitive Instructions
Problematic Instructions

x86 Instruction Set Architecture
798
CLI (Clear Interrupt Enable) Instruction
STI (Set Interrupt Enable) Instruction

Chapter 20: Virtual 8086 Mode
799
PUSHF (Push Flags) Instruction
POPF (Pop Flags) Instruction
INT nn (Software Interrupt) Instruction
IRET (Interrupt Return) Instruction

x86 Instruction Set Architecture
800
Solution: IOPL Sensitive Instructions
Handling Direct IO
The Problem
IO-Mapped IO
IO Permission in Protected Mode

Chapter 20: Virtual 8086 Mode
801
IO Permission in VM86 Mode

x86 Instruction Set Architecture
802
Memory-Mapped IO

Chapter 20: Virtual 8086 Mode
803
To Permit an Access
To Deny an Access
For Finer Control
Handling Video Frame Buffer Updates

x86 Instruction Set Architecture
804
Handling Exceptions in VM86 Mode
Processor Actions

Chapter 20: Virtual 8086 Mode
805
Option 1.
Option 2.
Option 3.

x86 Instruction Set Architecture
806
Option 1: Protected Mode Handler Services
Exception
Option 2: Handler Passes Exception to VMM for
Servicing

Chapter 20: Virtual 8086 Mode
807

x86 Instruction Set Architecture
808
Option 3: Exception Handled by Another Task

Chapter 20: Virtual 8086 Mode
809
Hardware Interrupt Handling in VM86 Mode
NMI, SMI, and Maskable Interrupts

x86 Instruction Set Architecture
810

Chapter 20: Virtual 8086 Mode
811
Real Mode Applications Unreal Reality

x86 Instruction Set Architecture
812
VM86 Task Executes CLI When VME = 0
CLI Handling

Chapter 20: Virtual 8086 Mode
813
Subsequent High-Priority Interrupt Detected
Servicing of Lower-Priority Interrupt Deferred

x86 Instruction Set Architecture
814

Chapter 20: Virtual 8086 Mode
815

x86 Instruction Set Architecture
816
STI/POPF/PUSHF/IRET Handling When VME = 0
Attempted Execution of STI Instruction (VME = 0)
Attempted Execution of PUSHF Instruction (VME = 0)

Chapter 20: Virtual 8086 Mode
817
Attempted Execution of POPF Instruction (VME = 0)
Attempted Execution of IRET Instruction (VME = 0)

x86 Instruction Set Architecture
818
CLI/STI/POPF/PUSHF Handling When VME = 1
VM86 Extensions

Chapter 20: Virtual 8086 Mode
819
Background
When VME = 1 and IOPL = 3, Task Can Control Eflags[IF]

x86 Instruction Set Architecture
820
When VME = 1 and IOPL < 3, Task Controls VIF, Not IF
Eflags[VIP] Is Controlled by the VMM
Software Cannot Directly Access Eflags[VIP]
CLI Followed by a Maskable Interrupt

Chapter 20: Virtual 8086 Mode
821

x86 Instruction Set Architecture
822
Subsequent STI Effect Depends on Eflags[VIP]

Chapter 20: Virtual 8086 Mode
823

x86 Instruction Set Architecture
824

Chapter 20: Virtual 8086 Mode
825
A Special Case
POPF/PUSHF Handling
Software Interrupt Instruction Handling
Software Interrupt Handling in Protected Mode

x86 Instruction Set Architecture
826
Software Interrupt Handling in VM86 Mode
INT3 Is Special

Chapter 20: Virtual 8086 Mode
827

x86 Instruction Set Architecture
828

Chapter 20: Virtual 8086 Mode
829
VMM Passes Control To Real Mode Handler

x86 Instruction Set Architecture
830

Chapter 20: Virtual 8086 Mode
831

x86 Instruction Set Architecture
832
Halt Instruction in VM86 Mode
Protected Mode Virtual Interrupt Feature
General

Chapter 20: Virtual 8086 Mode
833
1. Task executes CLI, Clears VIF
2. Maskable Interrupt Occurs and Is deferred
3. Task Executes STI

x86 Instruction Set Architecture
834
Registers Accessible in Real/VM86 Mode
Instructions Usable in Real/VM86 Mode

835
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
836
Introduction

Chapter 21: The MMX Facilities
837
Detecting MMX Capability
The Basic Problem
Assumptions
The Operation

x86 Instruction Set Architecture
838
Example: Processing One Pixel Per Iteration
Example: Processing Four Pixels Per Iteration

Chapter 21: The MMX Facilities
839

x86 Instruction Set Architecture
840
MMX SIMD Solution

Chapter 21: The MMX Facilities
841
Dealing with Unpacked Data

x86 Instruction Set Architecture
842
Dealing with Math Underflows and Overflows

Chapter 21: The MMX Facilities
843
Elimination of Conditional Branches
Introduction

x86 Instruction Set Architecture
844
Non-MMX Chroma-Key/Blue Screen Compositing
Example

Chapter 21: The MMX Facilities
845
MMX Chroma-Keying/Blue Screen Compositing
Example

x86 Instruction Set Architecture
846

Chapter 21: The MMX Facilities
847
Changes To the Programming Environment

x86 Instruction Set Architecture
848
Handling a Task Switch
MMX Instruction Set Syntax

Chapter 21: The MMX Facilities
849

x86 Instruction Set Architecture
850

851
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
852
Chapter Objectives
SSE: MMX on Steroids

Chapter 22: The SSE Facilities
853

x86 Instruction Set Architecture
854

Chapter 22: The SSE Facilities
855

x86 Instruction Set Architecture
856

Chapter 22: The SSE Facilities
857
Streaming SIMD Extensions (SSE)
The Motivation Behind SSE

x86 Instruction Set Architecture
858
Detecting SSE Support
The SSE Elements

Chapter 22: The SSE Facilities
859
SSE Data Types

x86 Instruction Set Architecture
860
The MXCSR
MXCSR Description

Chapter 22: The SSE Facilities
861

x86 Instruction Set Architecture
862

Chapter 22: The SSE Facilities
863
Loading and Storing the MXCSR
SIMD (Packed) Operations

x86 Instruction Set Architecture
864
Scalar Operations
Cache-Related Instructions

Chapter 22: The SSE Facilities
865
Overlapping Data Prefetch with Program Execution

x86 Instruction Set Architecture
866

Chapter 22: The SSE Facilities
867

x86 Instruction Set Architecture
868
Streaming Store Instructions

Chapter 22: The SSE Facilities
869

x86 Instruction Set Architecture
870

Chapter 22: The SSE Facilities
871

x86 Instruction Set Architecture
872

Chapter 22: The SSE Facilities
873
Ensuring Delivery of Writes Before Proceeding
An Example Scenario

x86 Instruction Set Architecture
874
SFENCE Instruction

Chapter 22: The SSE Facilities
875

x86 Instruction Set Architecture
876

Chapter 22: The SSE Facilities
877
Elimination of Mispredicted Branches
Background
SSE Misprediction Enhancements

x86 Instruction Set Architecture
878
Reciprocal and Reciprocal Square Root Operations

Chapter 22: The SSE Facilities
879
MPEG-2 Motion Compensation

x86 Instruction Set Architecture
880
Optimizing 3D Rasterization Performance
Optimizing Motion-Estimation Performance
Accuracy vs. Fast Real-Time 3D Processing (FTZ)

Chapter 22: The SSE Facilities
881
SSE Alignment Checking
The SIMD FP Exception
Saving and Restoring x87/MMX/SSE Registers
General

x86 Instruction Set Architecture
882
MXCSR Mask Field

Chapter 22: The SSE Facilities
883
OS Support for SSE
General

x86 Instruction Set Architecture
884
Enable SSE Instruction Sets and Register Set Save/Restore
Enable the SSE SIMD FP Exception

Chapter 22: The SSE Facilities
885
SSE Setup
Summary of the SSE Instruction Set

x86 Instruction Set Architecture
886

Chapter 22: The SSE Facilities
887
The SSE2 Instruction Set
General
DP FP Number Representation

x86 Instruction Set Architecture
888
SSE2 Packed and Scalar DP FP Instructions
SSE2 64-Bit and 128-Bit SIMD Integer Instructions

Chapter 22: The SSE Facilities
889
SSE2 128-Bit SIMD Integer Instruction Extensions
Your Choice: Accuracy or Speed (DAZ)

x86 Instruction Set Architecture
890
The Cache Line Flush Instruction

Chapter 22: The SSE Facilities
891
Fence Instructions
MFENCE Instruction

x86 Instruction Set Architecture
892

Chapter 22: The SSE Facilities
893
LFENCE Instruction

x86 Instruction Set Architecture
894
SFENCE Instruction
Non-Temporal Store Instructions
Introduction
MOVNTDQ Instruction

Chapter 22: The SSE Facilities
895
MOVNTPD Instruction

x86 Instruction Set Architecture
896
MOVNTI Instruction

Chapter 22: The SSE Facilities
897
MASKMOVDQU Instruction

x86 Instruction Set Architecture
898
PAUSE Instruction
Thread Synchronization

Chapter 22: The SSE Facilities
899
The Problem

x86 Instruction Set Architecture
900
The Fix

Chapter 22: The SSE Facilities
901
When a Thread Is Idle
Spin-Lock Optimization
Branch Hints

x86 Instruction Set Architecture
902
SSE3 Instruction Set
Introduction
Improved x87 FP-to-Integer Conversion Instruction
The Problem

Chapter 22: The SSE Facilities
903
The Solution
New Complex Arithmetic Instructions

x86 Instruction Set Architecture
904
Improved Motion Estimation Performance
The Problem

Chapter 22: The SSE Facilities
905
The Solution
The Downside

x86 Instruction Set Architecture
906
Instructions to Improve Processing of a Vertex
Database

Chapter 22: The SSE Facilities
907
MONITOR/MWAIT Instruction Pair
Background

x86 Instruction Set Architecture
908
Monitor Instruction
Mwait Instruction

Chapter 22: The SSE Facilities
909
Example Code Usage
The Wake Up Call

x86 Instruction Set Architecture
910
SSSE3, SSE 4.1, and 4.2

The Previous Part
This Part
The Next Part


913
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
914
The Next Chapter
The Big Picture

Chapter 23: IA-32e OS Environment
915

x86 Instruction Set Architecture
916
Mode Switching Overview
Booting Into Protected Mode

Chapter 23: IA-32e OS Environment
917
Initial Switch from IA-32 to IA-32e Mode

x86 Instruction Set Architecture
918

Chapter 23: IA-32e OS Environment
919

x86 Instruction Set Architecture
920
CS D and L Bits Control IA-32e SubMode Selection

Chapter 23: IA-32e OS Environment
921

x86 Instruction Set Architecture
922
Old and New Applications Running Under a 64-bit OS

Chapter 23: IA-32e OS Environment
923
Things You Lose In IA-32e Mode (hint: not much)
Old Applications Live in an Expanded Universe
Old Legacy Universe = 4GB or 64GB

x86 Instruction Set Architecture
924
IA-32e Universe Is At Least 16 Times Larger

Chapter 23: IA-32e OS Environment
925
Virtual Memory Addressing in IA-32e Mode
Virtual Address in Compatibility Mode

x86 Instruction Set Architecture
926
Virtual Address in 64-bit Mode
In Compatibility Mode, Segmentation Is Operative

Chapter 23: IA-32e OS Environment
927
In 64-bit Mode, Hardware-Enforced Flat Model
General
New Segment Selector Causes Descriptor Read
Segment Register Usage in 64-bit Mode

x86 Instruction Set Architecture
928

Chapter 23: IA-32e OS Environment
929

x86 Instruction Set Architecture
930

Chapter 23: IA-32e OS Environment
931

x86 Instruction Set Architecture
932

Chapter 23: IA-32e OS Environment
933

x86 Instruction Set Architecture
934
64-bit Mode: No Limit Checking = No Limits?

Chapter 23: IA-32e OS Environment
935
Table Limit Checks Are Performed
Stack Management
Stack Management in Compatibility Mode

x86 Instruction Set Architecture
936
Stack Management in 64-bit Mode

Chapter 23: IA-32e OS Environment
937
Segment Override Prefixes Other Than FS/GS Are
Ignored

x86 Instruction Set Architecture
938
Protection Provided by Paging
Segment Registers Preserved On Mode Switch
64-bit Instruction Pointer
Instruction Fetching

Chapter 23: IA-32e OS Environment
939
RIP-Relative Data Accesses
Changes To Kernel-Related Registers and Structures
Address Translation Mechanism
Basic Description

x86 Instruction Set Architecture
940
Top-Level Directory Placement
Detailed Description
GDT/LDT Descriptor Changes

Chapter 23: IA-32e OS Environment
941

x86 Instruction Set Architecture
942

Chapter 23: IA-32e OS Environment
943

x86 Instruction Set Architecture
944

Chapter 23: IA-32e OS Environment
945

x86 Instruction Set Architecture
946

Chapter 23: IA-32e OS Environment
947
GDT and GDTR Changes
GDT Descriptor Types

x86 Instruction Set Architecture
948

Chapter 23: IA-32e OS Environment
949
Executing LGDT in Compatibility Mode

x86 Instruction Set Architecture
950
Executing LGDT in 64-bit Mode

Chapter 23: IA-32e OS Environment
951
Unaligned Accesses to GDT or LDT

x86 Instruction Set Architecture
952
LDT and LDTR Changes
LDT Descriptor Types

Chapter 23: IA-32e OS Environment
953
LDTR Contents in IA-32e Mode
Unaligned Accesses to LDT

x86 Instruction Set Architecture
954

Chapter 23: IA-32e OS Environment
955
IDT/IDTR and Interrupt/Exception Changes
IDT Descriptor Types

x86 Instruction Set Architecture
956

Chapter 23: IA-32e OS Environment
957

x86 Instruction Set Architecture
958
Interrupt/Trap Gate Operational Changes

Chapter 23: IA-32e OS Environment
959

x86 Instruction Set Architecture
960

Chapter 23: IA-32e OS Environment
961

x86 Instruction Set Architecture
962

Chapter 23: IA-32e OS Environment
963
Executing LIDT in Compatibility Mode
Executing LIDT in 64-bit Mode

x86 Instruction Set Architecture
964
All Accesses to IDT Are Properly Aligned
IA-32e Call Gate Operation
General

Chapter 23: IA-32e OS Environment
965
IA-32e Call Gate Detailed Operation

x86 Instruction Set Architecture
966
IA-32e Call Gate Stack Switch

Chapter 23: IA-32e OS Environment
967

x86 Instruction Set Architecture
968
TR and TSS Changes
Real World TSS Usage

Chapter 23: IA-32e OS Environment
969

x86 Instruction Set Architecture
970

Chapter 23: IA-32e OS Environment
971

x86 Instruction Set Architecture
972

Chapter 23: IA-32e OS Environment
973
Illegal For Jump or Call To Select a TSS Descriptor
Executing LTR in Compatibility Mode

x86 Instruction Set Architecture
974
Executing LTR in 64-bit Mode
Revised TSS Structure

Chapter 23: IA-32e OS Environment
975

x86 Instruction Set Architecture
976
TSS Usage
Register Set Expansion (in 64-bit Mode)

Chapter 23: IA-32e OS Environment
977
Schedulers Software-Based Task Switching Mechanism
Switching to a 64-bit Task

x86 Instruction Set Architecture
978

Chapter 23: IA-32e OS Environment
979
Switching to a Legacy Task
General

x86 Instruction Set Architecture
980
Data Segment Register Initialization
CS and Instruction Pointer Initialization

Chapter 23: IA-32e OS Environment
981
The Switch

x86 Instruction Set Architecture
982

983
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
984
The Next Chapter
Theoretical Address Space Size

Chapter 24: IA-32e Address Translation
985
Limitation Imposed by Current Implementations
Four-Level Lookup Mechanism
Address Space Partitioning

x86 Instruction Set Architecture
986

Chapter 24: IA-32e Address Translation
987

x86 Instruction Set Architecture
988
The Address Translation
Initializing CR3
Step 1: PML4 Lookup

Chapter 24: IA-32e Address Translation
989

x86 Instruction Set Architecture
990
Step 2: PDPT Lookup

Chapter 24: IA-32e Address Translation
991

x86 Instruction Set Architecture
992
Step 3: Page Directory Lookup

Chapter 24: IA-32e Address Translation
993

x86 Instruction Set Architecture
994

Chapter 24: IA-32e Address Translation
995

x86 Instruction Set Architecture
996

Chapter 24: IA-32e Address Translation
997
Step 4: Page Table Lookup

x86 Instruction Set Architecture
998

Chapter 24: IA-32e Address Translation
999
Page Protection Mechanisms in IA-32e Mode
Page Protection in Compatibility Mode
Page Protection in 64-bit Mode

x86 Instruction Set Architecture
1000
Dont Forget the Execute Disable Feature!

Chapter 24: IA-32e Address Translation
1001

x86 Instruction Set Architecture
1002

Chapter 24: IA-32e Address Translation
1003

x86 Instruction Set Architecture
1004
TLBs Are More Important Than Ever

Chapter 24: IA-32e Address Translation
1005
No 4MB Page Support

x86 Instruction Set Architecture
1006

The Previous Part
This Part
The Next Part


1009
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1010
The Next Chapter
Initial Entry to Compatibility Mode
Switching Between Compatibility Mode and 64-bit Mode

Chapter 25: Compatibility Mode
1011
Differences Between IA-32 Mode and Compatibility Mode
IA-32 Background
Unsupported IA-32 Features
Changes to the OS Environment

x86 Instruction Set Architecture
1012

Chapter 25: Compatibility Mode
1013
Memory Addressing
Segmentation

x86 Instruction Set Architecture
1014
FS/GS Segments
Virtual Address
Address Translation

Chapter 25: Compatibility Mode
1015
Register Set
Visible Registers

x86 Instruction Set Architecture
1016
No Access to Additional or Extended Registers
Control Register Accesses
Debug Register Accesses
Register Preservation Across Mode Switches

Chapter 25: Compatibility Mode
1017
Exception and Interrupt Handling
OS Kernel Calls
Call Gates

x86 Instruction Set Architecture
1018
Kernel Call Instruction Usage
SysEnter Instruction
SysCall Instruction

Chapter 25: Compatibility Mode
1019
Odds and Ends
IRET Changes
Segment Load Instructions

x86 Instruction Set Architecture
1020

The Previous Part
This Part
The Next Part


1023
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1024
The Next Chapter
Overview of 64-bit Register Set

Chapter 26: 64-bit Register Overview
1025
EFER (Extended Features Enable) Register

x86 Instruction Set Architecture
1026

Chapter 26: 64-bit Register Overview
1027
Sixteen 64-bit Control Registers

x86 Instruction Set Architecture
1028

Chapter 26: 64-bit Register Overview
1029

x86 Instruction Set Architecture
1030

Chapter 26: 64-bit Register Overview
1031

x86 Instruction Set Architecture
1032

Chapter 26: 64-bit Register Overview
1033
64-bit Rflags Register
Sixteen 64-bit GPRs

x86 Instruction Set Architecture
1034

Chapter 26: 64-bit Register Overview
1035

x86 Instruction Set Architecture
1036
Kernel Data Structure Registers in 64-bit Mode

Chapter 26: 64-bit Register Overview
1037
SSE Register Set Expanded in 64-bit Mode

x86 Instruction Set Architecture
1038
Debug Breakpoint Registers

Chapter 26: 64-bit Register Overview
1039
Local APIC Register Set
x87 FPU/MMX Register Set
Architecturally-Defined MSRs

x86 Instruction Set Architecture
1040

1041
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1042
The Next Chapter
Helpful Background
Switching to 64-bit Mode
The Defaults

Chapter 27: 64-bit Operands and Addressing
1043
The REX Prefix
Problem 1: Addressing New Registers

x86 Instruction Set Architecture
1044

Chapter 27: 64-bit Operands and Addressing
1045
Problem 2: Using 16- and 64-bit Operands
Solution: The Rex Prefix

x86 Instruction Set Architecture
1046
Making Room for REX
REX Prefix Placement

Chapter 27: 64-bit Operands and Addressing
1047
When You Need REX...

x86 Instruction Set Architecture
1048
...and when you dont

Chapter 27: 64-bit Operands and Addressing
1049
Anatomy of a REX Prefix
General

x86 Instruction Set Architecture
1050

Chapter 27: 64-bit Operands and Addressing
1051

x86 Instruction Set Architecture
1052
The Width Bit

Chapter 27: 64-bit Operands and Addressing
1053
The Register Bit

x86 Instruction Set Architecture
1054

Chapter 27: 64-bit Operands and Addressing
1055
The IndeX and Base Bits

x86 Instruction Set Architecture
1056

Chapter 27: 64-bit Operands and Addressing
1057

x86 Instruction Set Architecture
1058
Addressing Registers Using REX[B] + Opcode[Reg]
Addressing Registers Using REX[B] + ModRM[RM]
Byte-Register Addressing Limitations

Chapter 27: 64-bit Operands and Addressing
1059
Sometimes, REX Fields Have No Effect
Addressing Memory in 64-bit Mode
64-bit Mode Uses a Hardware-Enforced Flat Model
CS, DS, ES, and SS Segments Start at Virtual Address 0

x86 Instruction Set Architecture
1060
CS/DS/ES/SS Segment Override Prefixes Ignored
FS and GS Segments Can Start at Non-Zero Base Addresses
FS/GS Segment Override Prefixes Matter

Chapter 27: 64-bit Operands and Addressing
1061
Default Virtual Address Size (and overriding it)

x86 Instruction Set Architecture
1062
Actual Address Size Support: Theory vs. Practice

Chapter 27: 64-bit Operands and Addressing
1063
Canonical Address
General

x86 Instruction Set Architecture
1064
32- (and 16-) bit Addressing Limited to Lower 4GB

Chapter 27: 64-bit Operands and Addressing
1065
Memory-based Operand Address Computation

x86 Instruction Set Architecture
1066

Chapter 27: 64-bit Operands and Addressing
1067

x86 Instruction Set Architecture
1068

Chapter 27: 64-bit Operands and Addressing
1069
RIP-relative Data Addressing

x86 Instruction Set Architecture
1070
Near and Far Branch Addressing

Chapter 27: 64-bit Operands and Addressing
1071

x86 Instruction Set Architecture
1072

Chapter 27: 64-bit Operands and Addressing
1073
Immediate Data Values in 64-bit Mode

x86 Instruction Set Architecture
1074
Displacements in 64-bit Mode

1075
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1076
The Next Chapter
New Instructions
General
SwapGS Instruction
The Problem

Chapter 28: 64-bit Odds and Ends
1077
The SwapGS Solution

x86 Instruction Set Architecture
1078
MOVSXD Instruction: Stretch It Out
Enhanced Instructions

Chapter 28: 64-bit Odds and Ends
1079
Invalid Instructions

x86 Instruction Set Architecture
1080

Chapter 28: 64-bit Odds and Ends
1081
Reassigned Instructions
LAHF/SAHF Instruction Support

x86 Instruction Set Architecture
1082
Instructions That Default to a 64-bit Operand Size
Stack Operations

Chapter 28: 64-bit Odds and Ends
1083
Near Branches
Branching in 64-bit Mode
Short/Near Branches Default to 64-bit Operand Size

x86 Instruction Set Architecture
1084
Unconditional Jumps in 64-bit Mode

Chapter 28: 64-bit Odds and Ends
1085

x86 Instruction Set Architecture
1086

Chapter 28: 64-bit Odds and Ends
1087
Calls/Ret/Iret in 64-bit Mode
Instruction Forms in 64-bit Mode

x86 Instruction Set Architecture
1088

Chapter 28: 64-bit Odds and Ends
1089
Example Call/Return Operations

x86 Instruction Set Architecture
1090

Chapter 28: 64-bit Odds and Ends
1091

x86 Instruction Set Architecture
1092

Chapter 28: 64-bit Odds and Ends
1093
Conditional Branches in 64-bit Mode

x86 Instruction Set Architecture
1094

Chapter 28: 64-bit Odds and Ends
1095

x86 Instruction Set Architecture
1096

Chapter 28: 64-bit Odds and Ends
1097
NOP Instruction
FXSAVE/FXRSTOR
General
Fast FxSave/Restore Feature (AMD-only)

x86 Instruction Set Architecture
1098

Chapter 28: 64-bit Odds and Ends
1099

x86 Instruction Set Architecture
1100

Chapter 28: 64-bit Odds and Ends
1101
The Nested Task Bit (Rflags[NT])

x86 Instruction Set Architecture
1102
SMM Save Area
IA-32 Processor SM Save Area

Chapter 28: 64-bit Odds and Ends
1103

x86 Instruction Set Architecture
1104

Chapter 28: 64-bit Odds and Ends
1105

x86 Instruction Set Architecture
1106
Intel 64 Processor SM Save Area

Chapter 28: 64-bit Odds and Ends
1107

x86 Instruction Set Architecture
1108

Chapter 28: 64-bit Odds and Ends
1109

x86 Instruction Set Architecture
1110

The Previous Part
This Part
The Next Part


1113
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
1114
Real Mode Peculiarities That Affect the OS Boot Process
Example OS Characteristics

Chapter 29: Transitioning to Protected Mode
1115
Flat Model With Paging
Software-Based Task Switching

x86 Instruction Set Architecture
1116
Protected Mode Transition Primer
GDT Must Be In Place Before Switch to Protected
Mode

Chapter 29: Transitioning to Protected Mode
1117

x86 Instruction Set Architecture
1118

Chapter 29: Transitioning to Protected Mode
1119
No Interrupts or Exceptions During Mode Switch

x86 Instruction Set Architecture
1120
Creation of Protected Mode IDT

Chapter 29: Transitioning to Protected Mode
1121
Other Protected Mode Structures
TSS

x86 Instruction Set Architecture
1122
Address Translation Mechanism

Chapter 29: Transitioning to Protected Mode
1123

x86 Instruction Set Architecture
1124
Optional Structure: LDT

Chapter 29: Transitioning to Protected Mode
1125
Enable A20 Gate
Load Initial Code and Handlers Into Memory
The Switch to Protected Mode
Loading Segment Registers With GDT Descriptors

x86 Instruction Set Architecture
1126

Chapter 29: Transitioning to Protected Mode
1127
Load TSS Descriptor Into TR
Enable Interrupts

x86 Instruction Set Architecture
1128
Load Application Into Memory
Create Tasks Address Translation Tables
Switching From OS Scheduler to First Task
Example: Linux Startup

Chapter 29: Transitioning to Protected Mode
1129
1. Bootsect
2. Setup

x86 Instruction Set Architecture
1130

Chapter 29: Transitioning to Protected Mode
1131
3a. Startup_32 in boot/compressed/head.s

x86 Instruction Set Architecture
1132
3b. Startup_32 in kernel/head.s

Chapter 29: Transitioning to Protected Mode
1133

x86 Instruction Set Architecture
1134

Chapter 29: Transitioning to Protected Mode
1135

x86 Instruction Set Architecture
1136

Chapter 29: Transitioning to Protected Mode
1137

x86 Instruction Set Architecture
1138

1139
The Previous Chapter
This Chapter
The Next Chapter

x86 Instruction Set Architecture
1140
No Need to Linger in Protected Mode
Entering Compatibility Mode

Chapter 30: Transitioning to IA-32e Mode
1141

x86 Instruction Set Architecture
1142
Switch to 64-bit Mode

Chapter 30: Transitioning to IA-32e Mode
1143

x86 Instruction Set Architecture
1144

The Previous Part
This Part


1147
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1148
The Next Chapter
Just an Introduction?
Detailed Coverage of Virtualization

Chapter 31: Introduction to Virtualization Technology
1149
The Intel Model
OS: I Am the God of All Things!

x86 Instruction Set Architecture
1150
Virtualization Supervisor: Sure You Are (:<)
Root versus Non-Root Mode

Chapter 31: Introduction to Virtualization Technology
1151
Detecting VMX Capability

x86 Instruction Set Architecture
1152
Entering/Exiting VMX Mode
Entering VMX Mode
Exiting VMX Mode

Chapter 31: Introduction to Virtualization Technology
1153
Virtualization Elements/Terminology

x86 Instruction Set Architecture
1154
Introduction to the VT Instructions

Chapter 31: Introduction to Virtualization Technology
1155

x86 Instruction Set Architecture
1156
Introduction to the VMCS Data Structure

Chapter 31: Introduction to Virtualization Technology
1157

x86 Instruction Set Architecture
1158

Chapter 31: Introduction to Virtualization Technology
1159

x86 Instruction Set Architecture
1160
Preparing to Launch a Guest OS

Chapter 31: Introduction to Virtualization Technology
1161
Launching a Guest OS

x86 Instruction Set Architecture
1162
Guest OS Suspension

Chapter 31: Introduction to Virtualization Technology
1163
Handling Timeslice Expiration
Handling a Sensitive Operation or a VMCALL
Resuming a Guest OS

x86 Instruction Set Architecture
1164

Chapter 31: Introduction to Virtualization Technology
1165
Some Warnings Regarding VMCS Accesses

x86 Instruction Set Architecture
1166

1167
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1168
The Next Chapter
What Falls Under the Heading of System Management?

Chapter 32: System Management Mode (SMM)
1169
The Genesis of SMM

x86 Instruction Set Architecture
1170
SMM Has Its Own Private Memory Space
The Basic Elements of SMM

Chapter 32: System Management Mode (SMM)
1171
A Very Simple Example Scenario
How the Processor Knows the SM Memory Start Address

x86 Instruction Set Architecture
1172
Normal Operation, (Including Paging) Is Disabled
The Organization of SM RAM
General

Chapter 32: System Management Mode (SMM)
1173
IA-32 Processor SM State Save Area

x86 Instruction Set Architecture
1174

Chapter 32: System Management Mode (SMM)
1175

x86 Instruction Set Architecture
1176

Chapter 32: System Management Mode (SMM)
1177

x86 Instruction Set Architecture
1178
Intel 64 Processor SM Save Area

Chapter 32: System Management Mode (SMM)
1179

x86 Instruction Set Architecture
1180

Chapter 32: System Management Mode (SMM)
1181

x86 Instruction Set Architecture
1182
Protecting Access to SM Memory

Chapter 32: System Management Mode (SMM)
1183
Entering SMM
The SMI Interrupt Is Generated
No Interruptions Please
General

x86 Instruction Set Architecture
1184
Exceptions and Software Interrupts Permitted but Not
Recommended
Servicing Maskable Interrupts While in the Handler
Single-Stepping through the SM Handler

Chapter 32: System Management Mode (SMM)
1185
If Interrupts/Exceptions Permitted, Build an IDT
SMM Uses Real Mode Address Formation

x86 Instruction Set Architecture
1186
NMI Handling While in SMM

Chapter 32: System Management Mode (SMM)
1187

x86 Instruction Set Architecture
1188
Informing the Chipset SM Mode Has Been Entered
General
A Note Concerning Memory-Mapped IO Ports
The Context Save
General

Chapter 32: System Management Mode (SMM)
1189
Although Saved, Some Register Images Are Forbidden
Territory
Special Actions Required on a Request for Power Down

x86 Instruction Set Architecture
1190
The Register Settings on Initiation of the SM Handler

Chapter 32: System Management Mode (SMM)
1191
The SMM Revision ID

x86 Instruction Set Architecture
1192
The Body of the Handler
Exiting SMM
The Resume Instruction

Chapter 32: System Management Mode (SMM)
1193
Informing the Chipset That SMM Has Been Exited
The Auto Halt Restart Feature

x86 Instruction Set Architecture
1194
Executing the HLT Instruction in the SM Handler

Chapter 32: System Management Mode (SMM)
1195
The IO Instruction Restart Feature
Introduction
An Example Scenario
The Detail

x86 Instruction Set Architecture
1196
Back-to-Back SMIs During IO Instruction Restart
Multiprocessor System Presents a Problem

Chapter 32: System Management Mode (SMM)
1197

x86 Instruction Set Architecture
1198
Caching from SM Memory
Background

Chapter 32: System Management Mode (SMM)
1199
The Physical Mapping of SM RAM Accesses

x86 Instruction Set Architecture
1200

Chapter 32: System Management Mode (SMM)
1201

x86 Instruction Set Architecture
1202

Chapter 32: System Management Mode (SMM)
1203
FLUSH# and SMI#
Setting Up the SMI Handler in SM Memory

x86 Instruction Set Architecture
1204
Relocating the SM RAM Base Address
Description
In an MP System, Each Processor Must Have a
Separate State Save Area

Chapter 32: System Management Mode (SMM)
1205
Accessing SM Memory Above the First MB
SMM in an MP System
SM Mode and Virtualization

x86 Instruction Set Architecture
1206

1207
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1208
The Next Chapter

Chapter 33: Machine Check Architecture (MCA)
1209
Why This Subject Is Included
MCA = Hardware Error Logging Capability

x86 Instruction Set Architecture
1210
The MCA Elements
The Machine Check Exception

Chapter 33: Machine Check Architecture (MCA)
1211
The MCA Register Set

x86 Instruction Set Architecture
1212
The Global Registers
Introduction
The Global Count and Present Register

Chapter 33: Machine Check Architecture (MCA)
1213
The Global Status Register

x86 Instruction Set Architecture
1214
The Global Control Register
The Extended MC State MSRs

Chapter 33: Machine Check Architecture (MCA)
1215

x86 Instruction Set Architecture
1216

Chapter 33: Machine Check Architecture (MCA)
1217
The Composition of a Register Bank
Overview
The Bank Control Register
General

x86 Instruction Set Architecture
1218
P6 and Core Processors
The Bank Status Register
General

Chapter 33: Machine Check Architecture (MCA)
1219

x86 Instruction Set Architecture
1220
Error Valid Bit
Overflow Bit

Chapter 33: Machine Check Architecture (MCA)
1221
Uncorrectable Error Bit
Error Enabled Bit
Miscellaneous Register Valid Bit
Address Register Valid Bit

x86 Instruction Set Architecture
1222
Processor Context Corrupt Bit
MCA Error Code and Model Specific Error Code
Other Information
The Bank Address Register
The Bank Miscellaneous Register
Control 2 Register

Chapter 33: Machine Check Architecture (MCA)
1223
The Error Code
The Error Code Fields
Simple MCA Error Codes

x86 Instruction Set Architecture
1224
Compound MCA Error Codes
General

Chapter 33: Machine Check Architecture (MCA)
1225
Correction Report Filtering Bit

x86 Instruction Set Architecture
1226

Chapter 33: Machine Check Architecture (MCA)
1227

x86 Instruction Set Architecture
1228

Chapter 33: Machine Check Architecture (MCA)
1229
Example External Interface Error Interpretation

x86 Instruction Set Architecture
1230

Chapter 33: Machine Check Architecture (MCA)
1231

x86 Instruction Set Architecture
1232
Cache Error Reporting
Green/Yellow Cache Health Indicator
Background
TES (Threshold Error Status) Feature

Chapter 33: Machine Check Architecture (MCA)
1233
Interrupt On Soft Error Threshold Match
Before CMCI, Soft Error Logging Required Periodic Scan

x86 Instruction Set Architecture
1234
CMCI Eliminates MC Register Scan

Chapter 33: Machine Check Architecture (MCA)
1235
Determining Processors CMCI Support
Determining a Banks CMCI Support
CMCI Interrupt Is Separate and Distinct From MC Exception
CMC Interrupt May Affect Multiple Cores/Logical Processors
CMC Interrupt Should Only Be Serviced Once

x86 Instruction Set Architecture
1236
MC Exception Is Generally Not Recoverable

Chapter 33: Machine Check Architecture (MCA)
1237
Machine Check and BINIT#
Additional Error Logging Notes
Error Buffering Capability
Additional Information for Each Log Entry

x86 Instruction Set Architecture
1238

1239
The Previous Chapter
This Chapter

x86 Instruction Set Architecture
1240
APIC and the IA-32 Architecture

Chapter 34: The Local and IO APICs
1241
Definition of IO and Local APICs
Hardware Context Is Essential
A Short History of the APICs Evolution
APIC Introduction
Pentium Pro APIC Enhancements

x86 Instruction Set Architecture
1242
The Pentium II and Pentium III
Pentium 4 APIC Enhancements: xAPIC

Chapter 34: The Local and IO APICs
1243
The x2APIC Architecture

x86 Instruction Set Architecture
1244
Before the APIC

Chapter 34: The Local and IO APICs
1245

x86 Instruction Set Architecture
1246
MP Systems Need a Better Interrupt Distribution
Mechanism
Legacy Interrupt Delivery System Is Inefficient

Chapter 34: The Local and IO APICs
1247

x86 Instruction Set Architecture
1248
The APIC Interrupt Distribution Mechanism
Introduction

Chapter 34: The Local and IO APICs
1249
Message Types

x86 Instruction Set Architecture
1250
Message Transfer Mechanism Prior to the Pentium 4
Message Transfer Mechanism Starting with the Pentium 4

Chapter 34: The Local and IO APICs
1251
Message Transfer Mechanism in Intel QPI-based Systems

x86 Instruction Set Architecture
1252

Chapter 34: The Local and IO APICs
1253
Processors Reside in Clusters

x86 Instruction Set Architecture
1254
Each Core/Logical Processor Has a Dedicated Local APIC
Introduction to the Message Addressing Modes

Chapter 34: The Local and IO APICs
1255
Detecting Presence/Version/Capabilities of Local APIC
Presence
Version

x86 Instruction Set Architecture
1256
x2APIC Capability Verification
Local APICs Initial State

Chapter 34: The Local and IO APICs
1257
Enabling/Disabling the Local APIC
General
Disabling Local APIC for Remainder of Power-Up
Session

x86 Instruction Set Architecture
1258
Dynamically Enabling/Disabling Local APIC

Chapter 34: The Local and IO APICs
1259

x86 Instruction Set Architecture
1260
Mode Selection

Chapter 34: The Local and IO APICs
1261
The Local APIC Register Set
Register Access in xAPIC Mode: MMIO
General
Local and IO APIC xAPIC Register Areas Are Uncacheable
xAPIC Register Access Alignment

x86 Instruction Set Architecture
1262
Register Access in x2APIC Mode: MSR
Introduction to the Local APICs Register Set

Chapter 34: The Local and IO APICs
1263

x86 Instruction Set Architecture
1264

Chapter 34: The Local and IO APICs
1265

x86 Instruction Set Architecture
1266

Chapter 34: The Local and IO APICs
1267

x86 Instruction Set Architecture
1268

Chapter 34: The Local and IO APICs
1269

x86 Instruction Set Architecture
1270

Chapter 34: The Local and IO APICs
1271

x86 Instruction Set Architecture
1272

Chapter 34: The Local and IO APICs
1273

x86 Instruction Set Architecture
1274

Chapter 34: The Local and IO APICs
1275

x86 Instruction Set Architecture
1276

Chapter 34: The Local and IO APICs
1277
Local APIC ID Assignments and Addressing
ID Assignment in xAPIC Mode
Introduction
Cluster ID Assignment

x86 Instruction Set Architecture
1278
Physical/Logical Processor and Local APIC ID Assignment

Chapter 34: The Local and IO APICs
1279

x86 Instruction Set Architecture
1280

Chapter 34: The Local and IO APICs
1281
xAPIC ID Register

x86 Instruction Set Architecture
1282
BIOS/OS Reassignment of xAPIC ID
Logical xAPIC Address Assignment
Maximum Number of xAPICs

Chapter 34: The Local and IO APICs
1283
ID Assignment in x2APIC Mode
Two Hardware-Assigned Local APIC IDs
x2APIC ID (Physical Local APIC ID)

x86 Instruction Set Architecture
1284

Chapter 34: The Local and IO APICs
1285
Logical x2APIC ID

x86 Instruction Set Architecture
1286

Chapter 34: The Local and IO APICs
1287
Local APIC Addressing
Physical Addressing: Single Target

x86 Instruction Set Architecture
1288
Logical Addressing: Multiple Targets

Chapter 34: The Local and IO APICs
1289

x86 Instruction Set Architecture
1290

Chapter 34: The Local and IO APICs
1291

x86 Instruction Set Architecture
1292
Message Addressing Summary

Chapter 34: The Local and IO APICs
1293

x86 Instruction Set Architecture
1294
Lowest-Priority Delivery Mode

Chapter 34: The Local and IO APICs
1295
General
Warnings Related to Lowest-Priority Delivery Mode

x86 Instruction Set Architecture
1296
Chipset-Assisted Lowest-Priority Delivery

Chapter 34: The Local and IO APICs
1297
Local APIC IDs Are Stored in the MP and ACPI Tables

x86 Instruction Set Architecture
1298
Accessing the Local APIC ID
An Introduction to the Interrupt Sources
Local Interrupts

Chapter 34: The Local and IO APICs
1299
Remote Interrupt Sources

x86 Instruction Set Architecture
1300
Introduction to Interrupt Priority
General

Chapter 34: The Local and IO APICs
1301
Definition of a User-Defined Interrupt

x86 Instruction Set Architecture
1302
User-Defined Interrupt Priority

Chapter 34: The Local and IO APICs
1303

x86 Instruction Set Architecture
1304

Chapter 34: The Local and IO APICs
1305
Definition of Fixed Interrupts
Masking User-Defined Interrupts
Task and Processor Priority
Introduction

x86 Instruction Set Architecture
1306
The Task Priority Register (TPR)
The Processor Priority Register (PPR)

Chapter 34: The Local and IO APICs
1307
The User-Defined Interrupt Eligibility Test

x86 Instruction Set Architecture
1308
CR8 (Alternative TPR)

Chapter 34: The Local and IO APICs
1309
Interrupt Message Format

x86 Instruction Set Architecture
1310

Chapter 34: The Local and IO APICs
1311

x86 Instruction Set Architecture
1312

Chapter 34: The Local and IO APICs
1313
IO/Local APICs Cooperate on Interrupt Handling
The Purpose of the IO APIC

x86 Instruction Set Architecture
1314

Chapter 34: The Local and IO APICs
1315

x86 Instruction Set Architecture
1316
Overview of Edge-Triggered Interrupt Handling
Assumptions
Description

Chapter 34: The Local and IO APICs
1317

x86 Instruction Set Architecture
1318

Chapter 34: The Local and IO APICs
1319

x86 Instruction Set Architecture
1320

Chapter 34: The Local and IO APICs
1321
Overview of Level-Sensitive Interrupt Handling
Assumptions

x86 Instruction Set Architecture
1322
Description

Chapter 34: The Local and IO APICs
1323

x86 Instruction Set Architecture
1324

Chapter 34: The Local and IO APICs
1325

x86 Instruction Set Architecture
1326
Higher-Priority Fixed Interrupt Preempts Handler

Chapter 34: The Local and IO APICs
1327

x86 Instruction Set Architecture
1328

Chapter 34: The Local and IO APICs
1329

x86 Instruction Set Architecture
1330

Chapter 34: The Local and IO APICs
1331
IO APIC Register Set
IO APIC Register Set Base Address

x86 Instruction Set Architecture
1332
IO APIC Register Set Description

Chapter 34: The Local and IO APICs
1333

x86 Instruction Set Architecture
1334

Chapter 34: The Local and IO APICs
1335
IRQ Pin Assertion Register

x86 Instruction Set Architecture
1336
IO APIC EOI Register and Shared Interrupts

Chapter 34: The Local and IO APICs
1337

x86 Instruction Set Architecture
1338

Chapter 34: The Local and IO APICs
1339

x86 Instruction Set Architecture
1340
IO APIC ID Register
IO APIC Version Register

Chapter 34: The Local and IO APICs
1341
IO APIC Redirection Table (RT) Register Set

x86 Instruction Set Architecture
1342

Chapter 34: The Local and IO APICs
1343

x86 Instruction Set Architecture
1344
IO APIC Interrupt Delivery Order Is Rotational

Chapter 34: The Local and IO APICs
1345
Message Signaled Interrupts (MSI)
General

x86 Instruction Set Architecture
1346
Using the IO APIC as a Surrogate Message Sender
Direct-Delivery of an MSI

Chapter 34: The Local and IO APICs
1347
Memory Already Syncd When Interrupt Handler
Entered
The Problem
Old Solution

x86 Instruction Set Architecture
1348
How MSI Solves the Problem
Interrupt Delivery from Legacy 8259a Interrupt Controller
Virtual Wire Mode A

Chapter 34: The Local and IO APICs
1349

x86 Instruction Set Architecture
1350
Virtual Wire Mode B

Chapter 34: The Local and IO APICs
1351
SW-Initiated Interrupt Message Transmission
Introduction

x86 Instruction Set Architecture
1352

Chapter 34: The Local and IO APICs
1353
Sending a Message From the Local APIC
ICR in xAPIC Mode
ICR in x2APIC Mode

x86 Instruction Set Architecture
1354

Chapter 34: The Local and IO APICs
1355

x86 Instruction Set Architecture
1356

Chapter 34: The Local and IO APICs
1357

x86 Instruction Set Architecture
1358

Chapter 34: The Local and IO APICs
1359
x2APIC Modes Self IPI Feature

x86 Instruction Set Architecture
1360
Locally Generated Interrupts
Introduction
The Local Vector Table

Chapter 34: The Local and IO APICs
1361
The Pentium Familys LVT
The P6 Familys LVT
The Pentium 4 Familys LVT
Core Processors LVT

x86 Instruction Set Architecture
1362
LVT Register State After Reset, INIT, or Software
Disable
Local Interrupt 0 (LINT0)
The Mask Bit
The Trigger Mode and the Input Pin Polarity

Chapter 34: The Local and IO APICs
1363
The Delivery Mode

x86 Instruction Set Architecture
1364
The Vector Field

Chapter 34: The Local and IO APICs
1365
The Remote IRR Bit
The Delivery Status
Local Interrupt 1 (LINT1)

x86 Instruction Set Architecture
1366
The Local APIC Timer
General

Chapter 34: The Local and IO APICs
1367
The Divide Configuration Register
One Shot Mode
Periodic Mode

x86 Instruction Set Architecture
1368
The Performance Counter Overflow Interrupt

Chapter 34: The Local and IO APICs
1369

x86 Instruction Set Architecture
1370
The Thermal Sensor Interrupt

Chapter 34: The Local and IO APICs
1371

x86 Instruction Set Architecture
1372
Correctable Machine Check (CMC) Interrupt

Chapter 34: The Local and IO APICs
1373
The Local APICs Error Interrupt
Local APIC Error LVT Register
Error Status Register (ESR) Operation in xAPIC Mode
Error Status Register Operation in x2APIC Mode

x86 Instruction Set Architecture
1374

Chapter 34: The Local and IO APICs
1375

x86 Instruction Set Architecture
1376
The Spurious Interrupt Vector
The Problem
Solution

Chapter 34: The Local and IO APICs
1377
Additional Spurious Vector Register Features

x86 Instruction Set Architecture
1378
Boot Strap Processor (BSP) Selection
Introduction

Chapter 34: The Local and IO APICs
1379
The BSP Selection Process
Pre-QPI BSP Selection Process

x86 Instruction Set Architecture
1380

Chapter 34: The Local and IO APICs
1381
Intel QPI BSP Selection Process
How the APs are Discovered and Configured

x86 Instruction Set Architecture
1382
AP Detection and Configuration
Introduction
BIOS AP Discovery Procedure

Chapter 34: The Local and IO APICs
1383

x86 Instruction Set Architecture
1384
Uni-Processor OS and the APs
MP OS and the APs

Chapter 34: The Local and IO APICs
1385

x86 Instruction Set Architecture
1386

Chapter 34: The Local and IO APICs
1387
The FindAndInitAllCPUs Routine

x86 Instruction Set Architecture
1388

Chapter 34: The Local and IO APICs
1389

x86 Instruction Set Architecture
1390

Glossary of Terms
1391

x86 Instruction Set Architecture
1392

Glossary of Terms
1393

x86 Instruction Set Architecture
1394

Glossary of Terms
1395

x86 Instruction Set Architecture
1396

Glossary of Terms
1397

x86 Instruction Set Architecture
1398

Glossary of Terms
1399

x86 Instruction Set Architecture
1400

Glossary of Terms
1401

x86 Instruction Set Architecture
1402

Glossary of Terms
1403

x86 Instruction Set Architecture
1404

Glossary of Terms
1405

x86 Instruction Set Architecture
1406

Glossary of Terms
1407

x86 Instruction Set Architecture
1408

Glossary of Terms
1409

x86 Instruction Set Architecture
1410

Glossary of Terms
1411

x86 Instruction Set Architecture
1412

Glossary of Terms
1413

x86 Instruction Set Architecture
1414

Glossary of Terms
1415

x86 Instruction Set Architecture
1416

Glossary of Terms
1417

x86 Instruction Set Architecture
1418

Glossary of Terms
1419

x86 Instruction Set Architecture
1420

Glossary of Terms
1421

x86 Instruction Set Architecture
1422

Glossary of Terms
1423

x86 Instruction Set Architecture
1424

Glossary of Terms
1425

x86 Instruction Set Architecture
1426

Glossary of Terms
1427

x86 Instruction Set Architecture
1428

Glossary of Terms
1429

x86 Instruction Set Architecture
1430

Glossary of Terms
1431

x86 Instruction Set Architecture
1432

Glossary of Terms
1433

x86 Instruction Set Architecture
1434

Glossary of Terms
1435

x86 Instruction Set Architecture
1436

Glossary of Terms
1437

x86 Instruction Set Architecture
1438

Glossary of Terms
1439

x86 Instruction Set Architecture
1440

Glossary of Terms
1441

x86 Instruction Set Architecture
1442

Glossary of Terms
1443

x86 Instruction Set Architecture
1444

Glossary of Terms
1445

x86 Instruction Set Architecture
1446

Glossary of Terms
1447

x86 Instruction Set Architecture
1448

Glossary of Terms
1449

x86 Instruction Set Architecture
1450

Glossary of Terms
1451

x86 Instruction Set Architecture
1452

Glossary of Terms
1453

x86 Instruction Set Architecture
1454

Glossary of Terms
1455

x86 Instruction Set Architecture
1456

Glossary of Terms
1457

x86 Instruction Set Architecture
1458

Glossary of Terms
1459

x86 Instruction Set Architecture
1460

Glossary of Terms
1461

x86 Instruction Set Architecture
1462

Glossary of Terms
1463

x86 Instruction Set Architecture
1464

Glossary of Terms
1465

x86 Instruction Set Architecture
1466

Glossary of Terms
1467

x86 Instruction Set Architecture
1468

























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