International Journal of Electronics

Vol. X, No. X, Month 200X, 000000

Running heads (verso) B.K. Upadhyaya and S.K. Sanyal.
(DO NOT INCLUDE THIS AT FIRST SUBMISSION FOR
BLIND REVIEW, BUT DO INCLUDE IT WHEN PREPARING
THE FINALLY ACCEPTED MANUSCRIPT FOR SUBMISSION)
(recto) International Journal of Electronics
VHDL Modelin o! Con"ol#$ion%l In$e&le%"e&' Dein$e&le%"e& !o& E!!i(ien$ FPGA I)*le)en$%$ion
BIJ! "#M$R #%$&'!$!$
a(
and )$*I* "#M$R )$N!$*
+
a
Department of Electronics and Telecommunication Engineering ,Tripura Institute of Technology, Agartala, India
+
Department Electronics and Telecommunication Engineering, Jada!pur Uni!ersity, Kol"ata, India.
(%*,$), )#%%*! TWO -I-*, %$.,) /R /IR)- )#BMI))IN0 N, 1I-'#- -', $BV,
$#-'R), 2RR,)%N&IN.
$#-'R, $//I*I$-IN $N& ,M$I* IN/RM$-IN 33 /R B*IN& R,VI,1 33 $N& $ ),2N&
2N-$ININ. -'I) IN/RM$-IN
/RM$--,& $) $BV,)
Interleaving along 4ith error correction coding is an e55ective 4a6 to deal 4ith di55erent t67es o5 error in
digital data co88unication. ,rror +urst due to 8ulti7ath 5ading and 5ro8 other sources in a digital channel
8a6 +e e55ectivel6 co8+ated +6 interleaving techni9ue. In this 7a7er 4e have 7ro7osed an e55icient techni9ue
to 8odel convolutional interleaver. $ hard4are descri7tion language 8odel o5 the techni9ue is 7re7ared and
i87le8ented on 5ield 7rogra88a+le gate arra6 (/%.$) 7lat5or8. ur techni9ue utili:es e8+edded shi5t
register o5 /%.$ chi7 to i87le8ent incre8ental shi5t register in the interleaver. )o5t4are si8ulation o5 the
8odel is 7resented. ur 7ro7osed techni9ue reduces consu87tion o5 /%.$ resources to a large e;tent
co87ared to conventional i87le8entation techni9ue using 5li735lo7. -his i87lies lo4er 7o4er consu87tion
and reduced dela6 in the interconnection net4or< o5 the /%.$. -his techni9ue is also e55icient in reducing
4astage o5 8e8or6 co87ared to 8e8or6 +ased i87le8entation techni9ue 5or digital audio +roadcasting
(&$B) a77lication. )i8ulation and /%.$ i87le8entation results are included.
+e,-o&d.: 2onvolutional Interleaver= V'&*= /%.$= e8+edded shi5t register= 8e8or6 4astage
>>>>>>>>>>>>>>>>>>>>>
(2orres7onding author. ,8ail0 +<u>?u@redi558ail.co8
/0 In$&od#($ion
-he error correction codes (,22) 7la6 ver6 i87ortant role in 8odern digital co88unication s6ste8s. Bit
error rate (B,R) o5 the trans8itted data can +e 8ini8i:ed using a good ,22, o5 course at the cost o5
redundanc6 (1ic<er ABBC). -o achieve lo4er B,R, co87le; coding sche8es li<e concatenated code
(den4alder ABDE) or -ur+o codes (Berrou, .lavieu; and -hiti8a?shi8a ABBF) can +e ado7ted. /or e;a87le,
+oth digital3audio +roadcasting (&$BG) and digital3video +roadcasting (&VB) (,-)I 200A) ado7t the
concatenated code. In this coding techni9ue the inner encoding sche8e is convolutional and the outer one is
Reed3)olo8on (R)). Bet4een these inner and outer encoding sche8es an interleaver is used 4hich has
i87ortant i87act on the error correction (/orne6 ABDA= Ra8se6 ABD0).
Interleaving techni9ue is traditionall6 used to enhance the 9ualit6 o5 digital trans8ission over a +urst6 channel
()hi, Hhang, Ni and $nsari 200I). Interleaving is a 7rocess to rearrange code s68+ols so as to s7read +urst o5
errors into rando8 li<e errors and therea5ter ,22 can +e a77lied to correct the8. Interleaving is achieved
4hen ad?acent code s68+ols are se7arated +6 8ore than the average duration o5 an error +urst. It i87roves
(/orne6 ABDA) the 7er5or8ance o5 digital trans8ission at the cost o5 increased 8e8or6 re9uire8ent, s6ste8
co87le;it6, and dela6. In 8ost o5 the a77lications increased 8e8or6 re9uire8ent and s6ste8 co87le;it6 can
+e acco88odated 4ith advance8ent in technolog6. 'o4ever the increased dela6 as a result o5 increased
8e8or6 re9uire8ent, 8a6 8a<e interleaving a non37ractical solution in so8e a77lications. )o, an interleaver
4ith lo4 dela6 is a 7ractical 4a6 to deal 4ith the error +urst. Man6 7a7ers in the literature have addressed the
issue o5 designing interleaver in order to achieve lo4 B,R (&aneshgaran, *addo8ada and Mondin 200I=
Ngu6en, and "uchen+ec<er 200A= -a<eshita 200E= )ad?ad7our, )loane, )alehi, and Ne+e 200A). n the
contrar6, ver6 5e4 7a7ers have addressed the e55icient i87le8entation issue o5 the interleavers ("i8, *i8 and
*ee 200A= !ang, Hhong and !ang ABBB) . Bloc< and 2onvolutional are the t4o 7o7ular interleavers e87lo6ed
in digital data trans8ission. -he 5or8er is si87le and eas6 to i87le8ent 4hereas the later o55ers advantages
li<e lesser end3to3end dela6 and reduced 8e8or6 re9uire8ent ('anna ABBF).
In this 7a7er 4e have 7ro7osed an e55icient and novel techni9ue to 8odel and i87le8ent convolutional
interleaver3deinterleaver 7air on 5ield 7rogra88a+le gate arra6 (/%.$) 7lat5or8. %ro7osed techni9ue
e87lo6s e8+edded shi5t register o55ered +6 di55erent /%.$ 8anu5acturers (Xilin; 200E= $ltera 200D) to
8odel the dela6 unit o5 the interleaver. 1e have 8odeled and i87le8ented J +it and F2 +it version o5
interleaver as 4ell as deinterleaver. Both these i87le8entation techni9ues are di55erent in the sense that the6
involve 5ull /%.$ +ased design leading to less resource re9uire8ent and there+6 8a<ing lesser 7o4er
consu87tion and interconnect dela6. 2o87arative anal6sis sho4s saving o5 /%.$ resources a+ove JA K in
co87arison to conventional techni9ue using 5li75lo7s. #se o5 lesser slices leads to reduced dela6 in the
interconnection net4or< inside the /%.$. -he o+vious i87lication is reduced 7o4er consu87tion. #se o5
e;ternal 8e8or6 as 7ro7osed in ("i8, *i8 and *ee 200A= !ang, Hhong and !ang ABBB) to 8odel
incre8ental shi5t register to design an interleaver increases dela6 as 4ell as 4aste 8e8or6. &ue to
insu55icienc6 o5 5li75lo7s in /%.$, "i8 et. al. ("i8, *i8 and *ee 200A) 7ro7osed a techni9ue to use 8e8or6
4ith reduced 4astage. 'o4ever, our 7ro7osed techni9ue eli8inates the need o5 using e;ternal 8e8or6,
there+6 avoiding longer 8e8or6 access ti8e and thus 8a<ing the s6ste8 8ore e55icient. In addition, the
8e8or6 4astage is 5urther lo4ered +6 F0.FJ K 5or &$B a77lication in co87arison 4ith ("i8, *i8 and *ee
200A). #sing our e55icient techni9ue, i87le8entation o5 convolutional de3interleaver used in advanced
television s6ste8s co88ittee ($-)2) digital -V receiver (!ang, Hhong and !ang ABBB) re9uires onl6 20.FAK
o5 total e8+edded shi5t registers and A0.AE K o5 total logic resources availa+le in Xilin; )7artan3F (device
X2F) I00) /%.$. -he 7ro7osed design techni9ue using /%.$ can also +e 8odi5ied easil6 5or the
i87le8entation o5 convolutional interleaver o5 di55erent s7eci5ications. -he rest o5 the 7a7er is organi:ed as
5ollo4s. )ection II discusses the +ac<ground o5 interleaving techni9ue. It also highlights the advantages o5
convolutional interleaver co87ared to +loc< interleaver. In )ection III, 4e +rie5l6 descri+e the e8+edded shi5t
register o5 )7artan3F /%.$ o5 Xilin; Inc. that 4as used to o+tain our i87le8entation results. )ection IV
7rovides 5unctional descri7tion o5 the 7ro7osed 8odel o5 convolutional interleaver. In )ection V, V'&*
8odel o5 the interleaver is narrated. )i8ulation result o5 the V'&* 8odel is e;7lained in )ection VI. )ection
VII 7er5or8s the critical anal6sis o5 /%.$ i87le8entation result. 2oncluding re8ar< is given in )ection VIII.
10 In$e&le%"in $e(2ni3#e
Interleavers are +roadl6 classi5ied into t4o categories ('anna ABBF)0 7eriodic interleavers and 7seudo3rando8
interleaver. In a 7eriodic interleaver, s68+ols o5 a code 4ord are scra8+led as a 7eriodic 5unction o5 ti8e. -he
7eriod, - deter8ines length o5 the error +urst that can +e e55ectivel6 s7read out into single +it error a5ter
deinterleaving. $ 7seudo3rando8 interleaver scra8+les the code 4ord s68+ols in rando8 5ashion +ut at a
distance greater than ), the se7aration threshold (&ivsalar and %ollara ABBE). $ 7seudo3rando8 se9uence is
generated 5or scra8+ling the code 4ord 4hich is to +e trans8itted to the receiver side 5or deinterleaving.
Bloc< and convolutional interleaving are the t4o 8ain t67es o5 7eriodic interleaving techni9ues.
2.1 Block interleaving
$ +loc< interleaver acce7ts the code 4ords in +loc< 5or8 5ro8 the encoder, scra8+les the code s68+ols and
then sends the8 to the 8odulatorLchannel ()<lar 200E). -he code 4ords se9uence is usuall6 5ed into the arra6
colu8n +6 colu8n 8anner and ta<en out ro4 +6 ro4 8anner. $t the receiver the deinterleaver 7er5or8s the
inverse o7eration. -he interleaved code 4ords entered the deinterleaver arra6 ro4 +6 ro4 8anner and
re8oved colu8n +6 colu8n. /or an interleaver o5 arra6 si:e M X N, 4here M and N re7resents nu8+er o5
ro4s and colu8ns, the deinterleaver arra6 should +e o5 si:e N X M. $n interleaver3deinterleaver 7air o5 such
arra6 si:e is ca7a+le o5 isolating N contiguous channel s68+ols errors. No4 i5 the ,22 e87lo6ed is ca7a+le
o5 correcting B code s68+ols then the interleaved code corrects an6 co8+ination o5 +ursts o5 length BN
s68+ols or less. -he dela6 ti8e, ti re9uired +e5ore an6 trans8ission to ta<e 7lace is given +6,
ti M M(N3A) G A code s68+ol (A)
$ corres7onding nu8+er needs to +e 5illed u7 at the deinterleaver +e5ore decoding can +egin. -hus the
8ini8u8 end to end dela6 due to the +loc< interleaver3deinterleaver 7air onl6 is
tee M (2MN 2M G 2) code s68+ol (2)
-he 8e8or6 re9uire8ent o5 such interleaver3deinterleaver 7air is
8r M 2MN s68+ols. (F)
2.2 Convolutional interleaving
$ convolutional interleaver (/orne6 ABDA= Ra8se6 ABD0) consists o5 N ro4s o5 shi5t registers, 4ith di55erent
dela6 in each ro4. -he 7eriod o5 such structure is called N. In general, each successive ro4 has a dela6 4hich
is J s68+ols duration higher than the 7revious ro4 as sho4n in /igure A(a) ("i8, *i8 and *ee 200A). -he
:eroth ro4 has no dela6 ele8ents. -he code 4ord s68+ol 5ro8 the encoder is 5ed into the arra6 o5 shi5t
registers, one code s68+ol to each ro4. 1ith each ne4 code 4ord s68+ol the co88utator s4itches to a ne4
register and the ne4 code s68+ol is shi5ted out to the channel. -he i3th (A N i N N3A) shi5t register has a
length o5 (i3A)J stages 4here J M MLN and the last ro4 has M3A nu8+ers o5 dela6 ele8ents.
-he convolutional deinterleaver 7er5or8s the inverse o7eration o5 the interleaver and di55ers in
structure o5 the arrange8ent o5 dela6 ele8ents as sho4n in /igure A(+). -he co88utator s4itch at the out7ut
o5 the interleaver and at the in7ut to the deinterleaver 8ust +e s6nchroni:ed. /or convolutional interleaving
tee M M(N3A) code s68+ol (I)
and
8r M M(N3A) s68+ols. (C)
It is o+served 5ro8 e9uations (2) to (C) that +oth end3to3end dela6 and 8e8or6 re9uire8ent 5or convolutional
interleaver3deinterleaver 7air is hal5 o5 the +loc< interleaver3deinterleaver 7air.
/igure A(a). )tructure o5 convolutional interleaver 4ith JMA. /igure A(+). )tructure o5 convolutional deinterleaver 4ith JMA.
40 H%&d-%&e de.(&i*$ion o! FPGA
In our e;7eri8entation, )7artan3F (device X2F) I00) 4ith I00" gate count /%.$ is used (Xilin; 200E). It
has total JBE nu8+ers o5 con5igura+le logic +loc<s (2*Bs) arranged in F2 X 2J 8atri; 5ashion. ,ach 2*B has
5our slices and t4o o5 the8 are na8ed as )*I2,M and rest t4o as )*I2,*. ,ach o5 the slices is having logic
5unction generator, 5li735lo7, 8ulti7le;er carr6 logic and arith8etic gates. Besides these, )*I2,M su77orts
t4o additional 5unctions0 storing data using distri+uted R$M (&R$M) and AE +it shi5t register ()R*AE). )o,
total JBE X 2 M ADB2 nu8+ers o5 )R* AE (e8+edded shi5t register) are availa+le in addition to other logic
resources. &$B a77lication re9uires a convolutional interleaver o5 arra6 si:e ("i8, *i8 and *ee 200A)= o5 AD
X ? (? M 0, A, O, AA) M AA22 nu8+ers o5 dela6 ele8ents. Nu8+ers o5 )R* AE re9uired to i87le8ent the
interleaver is DD 4hich is onl6 I.FK o5 availa+le )R*AE. -he arra6 si:e o5 the convolutional de3interleaver
used in $-)2 digital -V receiver is I X ? (? M 0, A, O, CA) (!ang, Hhong and !ang ABBB). Modeling this arra6
using our 7ro7osed techni9ue re9uires FEI nu8+ers o5 )R* AE 4hich is onl6 20.FAK o5 total )R* AE and
J
J J
J J J
J J J J
0

A

2
F
N3A
J J J J
J J J
J J
J
0



N3I
N3F
N32
N3A
&ela6
,le8ent
/ro8
,ncoder
-o
2hannel
/ro8
2hannel
-o
&ecoder
A0.AE K o5 total slices availa+le in Xilin; )7artan3F (device X2F) I00) /%.$. In +oth a77lications, +ecause
o5 our e55icient /%.$ i87le8entation techni9ue, su55icient /%.$ resources are 8ade availa+le 5or
i87le8enting other circuitr6 o5 the trans8itterLreceiver.
$n )R*2AE (Xilin; 200C) 4hich is cascada+le version o5 )R*AE is constructed 5ro8 a I +it *oo<3#7 -a+le
(*#-). $s sho4n in /igure 2, the )R*2AE is used to i87le8ent a 7rogressive dela6 line. )R*2AE is +asicall6
a AE +it shi5t register +ut its length can +e d6na8icall6 varied +6 changing value in M#X select in7ut (i.e.
$&&R). /or e;a87le, to i87le8ent D +it shi5t register $&&R M 0AA02. -o construct a shi5t register having
length higher than AE (e. g. F2 +it), cascading o5 t4o or 8ore )R*2AE is 7ossi+le either through 2AC out7ut
line or through #- line <ee7ing $&&R M AAAA2. 'o4ever cascading through 2AC o55ers lo4er dela6 than
through M#X.

/igure 2. Internal structure o5 )R*2AE.
50 P&o*o.ed )odel o! (on"ol#$ion%l in$e&le%"e&
/igure F. Bloc< diagra8 o5 7ro7osed J +it convolutional interleaver.
-he 7ro7osed 8odel o5 an J +it convolutional interleaver 4ith J M A is 7resented in /igure F. -he code 4ord
s68+ols received in serial 5or8 5ro8 an encoder is converted into an J +it 7arallel code 4ord +6 a )erial In7ut
%arallel ut7ut ()I%) register. -he J +it code 4ord is then su77lied to a dela6 unit through a +u55er register.
-he )I% out7ut changes its value 4ith each cloc< 4hich is not desira+le at the in7ut o5 the dela6 unit. -he
+u55er unit delivers a 4ord to the dela6 unit a5ter ever6 J cloc< c6cles. -he dela6 unit is co87rised o5 eight
ro4s and is having the structure as narrated in /igure A(a). ,ach code s68+ols o5 the J +it code 4ord is
a77lied to the res7ective ro4 o5 the dela6 unit. -he code 4ord gets scra8+led as it 7rogresses through the
dela6 unit. -a+le A sho4s the scra8+ling o7eration o5 the dela6 unit 4here the in7ut code 4ord a77lied is
& P
6
& P
/
& P
/7
M#X
&IN
2*"
#-
$&&R
2AC

)I%
R,.I)-,R
B#//,R
&,*$!
#NI-
J0A M#X
2*2" 2IR2#I- 2#N-,R
J J J
F
2ode
4ord
5ro8
encoder
Interleaved
code
s68+ols
2loc<
AAAAAAAA2 +e5ore an6 cloc< is a77lied. -he su+se9uent code 4ords are assu8ed to +e 000000002 5or clarit6.
-he scra8+led code 4ord then a77lied to the in7ut o5 an J line to A line 8ulti7le;er (M#X) 4hich converts it
into strea8 o5 serial data (interleaved code s68+ols). -he interleaver circuit re9uires a cloc< signal to drive
the )I% register, a cloc< circuit and a three +it counter. -he cloc< circuit +asicall6 divides the s6ste8 cloc<
5re9uenc6 +6 J 4hich is used to drive the +u55er and dela6 unit. -he F +it counter generates the select in7ut 5or
the M#X. -he out7uts o5 the counter or cloc< signal are also to +e trans8itted to the receiver circuitr6 along
4ith the scra8+led code 4ord as s6nchroni:ation signal to unscra8+le (deinterleave) the received code 4ord.
-a+le A. )cra8+ling o7eration o5 dela6 unit o5 convolutional interleaver.
In7ut to &ela6 #nit ut7ut o5 &ela6 #nit
2loc<
events
&D &E &C &I &F &2 &A &0 D E C I F 2 A 0
Be5ore -A A A A A A A A A A X X X X X X X
$5ter -A 0 0 0 0 0 0 0 0 0 A X X X X X X
$5ter -2 0 0 0 0 0 0 0 0 0 0 A X X X X X
$5ter -F 0 0 0 0 0 0 0 0 0 0 0 A X X X X
$5ter -I 0 0 0 0 0 0 0 0 0 0 0 0 A X X X
$5ter -C 0 0 0 0 0 0 0 0 0 0 0 0 0 A X X
$5ter -E 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A X
$5ter -D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A
-he +loc< diagra8 re7resentation o5 the deinterleaver is si8ilar to /igure F. -he onl6 di55erence lies in the
dela6 unit and is having the structure as de7icted in /igure A(+). -he 5unctional descri7tion can easil6 +e
e;tended to higher nu8+er o5 +its 4ith or 4ithout higher values o5 J.
70 VHDL )odelin
-his section descri+es the V'&* 8odeling (%err6 200A) o5 an J +it interleaver, deinterleaver and the
interleaver3deinterleaver 7air together using Xilin; Integrated )o5t4are ,nviron8ent (I),) so5t4are (Vi
Micros6ste8s 200I) and is 7resented in the 5or8 o5 5lo4 charts.
5.1 Interleaver
In /igure I the entit6 o5 the interleaver 8odel contains &>IN (in7ut code 4ord strea8) and 2*" (cloc<) as
in7ut signal and &>#- (scra8+led code 4ord strea8) as out7ut signal. -he in7ut code 4ord strea8 enters
the )I%>I +loc< one +it at a ti8e in s6nchroni:ation 4ith cloc<. -he 2*" signal is also read +6 t4o V'&*
7rogra8s= one 5or generating 2*"J (M 2*"QJ) s6nchroni:ation signal and the other 5or generating
2#N-FBI-, 5unctions as select in7ut signal to M#X. B#//,R>I is another V'&* 7rogra8 to i87le8ent
the J +it +u55er register and is s6nchroni:ed +6 2*"QJ signal. -he out7ut 5ro8 the B#//,R>I +loc< is
su77lied to &,*>#NI->I +loc<, a V'&* 7rogra8 to reali:e the dela6 unit re9uired in the interleaver. -his is
the heart o5 the interleaver. It consists o5 seven V'&* 7rogra8 internall6 to i87le8ent varia+le length shi5t
register. It is s6nchroni:ed +6 2*"J signal. -he out7ut o5 the &,*>#NI->I +loc< is su77lied to the V'&*
7rogra8 to i87le8ent J0A M#X (M#X>JXA) 4hich converts the J +it scra8+led code 4ord into serial
strea8 o5 code s68+ols and is 5inall6 ta<en out 5ro8 &>#- line.
/igure I. /lo4 chart o5 J +it 2onvolutional Interleaver
5.2 Deinterleaver
,;ternall6 the V'&* 8odel o5 the J +it convolutional deinterleaver is identical to that o5 the interleaver. But
internall6 the t4o 8odels di55er in the structure o5 the dela6 unit (5or deinterleaver it is &,*>#NI->&). -he
shi5t register 5or ro4 N3A in &,*>#NI->I is used in :eroth ro4 o5 the &,*>#NI->&. )i8ilarl6 shi5t register
o5 N32 ro4 in &,*>#NI->I is connected to A
st
ro4 o5 the &,*>#NI->& and so on.
5.3 Interleaver - deinterleaver pair
In order to veri56 the V'&* 8odels 5or the interleaver and deinterleaver the authors have develo7ed another
to7 level V'&* 8odel, IN-,R*,$V,R>&,IN-,R*,$V,R as sho4n in /igure C. -his 8odel consist o5
t4o V'&* 8odels internall6= IN-,R*,$V,R and &,IN-,R*,$V,R. -he scra8+led code 4ords 5ro8 the
out7ut o5 the IN-,R*,$V,R is a77lied as in7ut to the &,IN-,R*,$V,R +loc< along 4ith 2*" as
s6nchroni:ation signal. It is o+served that the scra8+led code 4ord is converted into its original 5or8 at the
out7ut o5 the &,IN-,R*,$V,R +loc<.
)tart
Read &>IN and 2*"
&eclare &>IN, 2*" as in7ut signals
and &>#- as out7ut signal
)I%>I
2#N-FBI- 2*"J
M#X>JXA
&,*>#NI->I
B#//,R>I
)to7
/igure C. V'&* 8odel o5 J +it 2onvolutional IN-,R*,$V,R>&,IN-,R*,$V,R 7air.
/igure E. )creen shot o5 Xilin; I), 4indo4 4ith a 7ortion o5 to7 level V'&* 7rogra8 5or J +it interleaver.
)tart
Read &$-$>IN and 2*"
&eclare &$-$>IN, 2*" as in7ut signals
and &$-$>#- as out7ut signal
IN-,R*,$V,R
&,IN-,R*,$V,R
)to7
80 Si)#l%$ion &e.#l$.
/igure D(a). )i8ulation result 4ith in7ut code 4ord M AAAAAAAA2
-he si8ulation result in the 5or8 o5 ti8ing diagra8 o+tained using Model)i8 Xilin; ,dition3III, version E.0a
is sho4n in /igure D(a) and (+). -he s6ste8 cloc< 5re9uenc6 a77lied to the 8odel is C M': 5or si8ulation.
In7ut set u7 ti8e and out7ut valid dela6 ti8e are chosen to +e A0ns each. -he J +it (MAAAAAAAA2 ) in7ut signal
is a77lied at data>in in7ut o5 the interleaver as sho4n in /igure D(a). -he interleaver 7roduces scra8+led
out7ut at d>out. -his scra8+led out7ut is 5ed as in7ut to the deinterleaver 4hich arranges the8 in such a 4a6
that the original code 4ord is generated at its out7ut (data>out). /igure D(+) sho4s another ti8ing diagra8
4ith in7ut code 4ord M AAA0AAAA2.
/igure D(+). )i8ulation result 4ith in7ut code 4ord M AAAA0AAA2
-he authors have also 8odeled, si8ulated and tested F2 +it 2onvolutional interleaver and
deinterleaver 7air, ho4ever to 8aintain clarit6 the si8ulation result o5 the sa8e is not 7rovided.
90 C&i$i(%l %n%l,.i. o! FPGA i)*le)en$%$ion &e.#l$.
-he V'&* 8odel o5 2onvolutional interleaver3deinterleaver 7airs (+oth J +it and F2 +it) are i87le8ented and
tested into Xilin; )7artan3F (&evice0 X2F)I00) /%.$ 7lat5or8 in the la+orator6. -he /%.$ i87le8entation
o5 the convolutional interleaver3deinterleaver 7air 4ithout )R*2AE 5eature is a ver6 register3intensive
a77lication. -a+le 2 sho4s a co87arative anal6sis o5 the /%.$ resource re9uire8ent in the dela6 units o5
interleaver and deinterleaver ta<en together 5or the t4o i87le8entations0 4ith and 4ithout )R*2AE 5or +oth J
+it and F2 +it version.
-a+le 2. 2o87arative anal6sis +et4een various i87le8entations
Interleaver
4ord length
A +it dela6 units
re9uired
/%.$ slices re9uired )lice saving in
K 4ithout )R*2AE 4ith )R*2AE
J +it J X D M CE CE Q 2 M 2J AI C0.00 K
F2 +it F2 X FA M BB2 BB2 Q 2 M IBE B2 JA.IC K
-a+le 2 clearl6 signi5ies that our 7ro7osed i87le8entation techni9ue saves C0 K and a+ove JA K o5 /%.$
resources co87ared to i87le8entation techni9ue 4ithout )R*2AE 5or J +it and F2 +it res7ectivel6. #se o5
lesser slices leads to reduced dela6 in the interconnection net4or< inside the /%.$. -his 5urther i87lies
reduction in 7o4er consu87tion too.
-a+le F 8a<es co87arison o5 our 7ro7osed techni9ue 4ith "i8 et. al. ("i8, *i8 and *ee 200A) in the issue
o5 reduction in 8e8or6 4astage 5or interleaver i87le8entation. It is 5ound that our 7ro7osed techni9ue
5urther reduces 8e8or6 4astage +6 F0.FJ K 5or &$B a77lication. In addition, o+viousl6 the access ti8e o5
e8+edded shi5t register is lo4er than that o5 e;ternal 8e8or6.
-a+le F. 2o87arative anal6sis 4ith res7ect to 8e8or6 4astage
ro4 no. A +it dela6
units
re9uired
using "i8 et. al. techni9ue our 7ro7osed techni9ue
R$M si:e 4asted
8e8or6
no. o5 )R*2AE
re9uired
4asted 8e8or6
A AD A2J (RAGRF) E0 2 AC
2 FI 2CE (R2GRJ) JE F AI
F CA 8erged 4ith RA 333 I AF
I EJ 2CE (RIGRAA) A C A2
C JC 2CE (RCGRA0) A E AA
E A02 2CE (REGRB) A D A0
D AAB A2J B J B
J AFE 8erged 4ith R2 333 B J
B ACF 8erged 4ith RE 333 A0 D
A0 AD0 8erged 4ith RC 333 AA E
AA AJD 8erged 4ith RI 333 A2 C
-otal 4astage ACJ AA0
$ +ar chart co87arison on 4astage o5 8e8or6 +its in each ro4 using .eneral )tructure ("i8, *i8 and *ee
200A), "i8 et. al. and our 7ro7osed techni9ue is sho4n in /igure J. /igure B 7resents 7ictorial re7resentation
o5 8e8or6 4astage 5actor nor8alised against our 7ro7osed techni9ue. It is evident 5ro8 /igure B that our
7ro7osed techni9ue is 8ost e55icient as 5ar as 8e8or6 4astage is concerned.
/igure J. Bar chart sho4ing ro4 4ise 8e8or6 4astage o5 the three i87le8entation techni9ues
/igure B. Me8or6 4astage 5actors o5 the three i87le8entation techni9ues
-he '&* )6nthesis Re7ort and &evice utili:ation su88ar6 generated using X)- (Xilin; )6nthesis
-echnolog6), version .. FC, a Xilin; tool that s6nthesi:es '&* designs 5or the V'&* 8odels (+oth J +it and
F2 +it) are given in -a+le I and C res7ectivel6. -he F2 +it design needs t4o C +it adders in the C +it counters o5
interleaver and deinterleaver each. $s evident 5ro8 -a+le I that J +it and F2 +it interleaver3deinterleaver 7air
needs AI and B2 nu8+ers o5 )R*2AE, 4hich 8atches 4ith -a+le 2. ther registers are re9uired 5or
constructing )I%s, internal storage in counters and in cloc< circuits.
-a+le I. '&* s6nthesis re7ort
'&* )6nthesis Re7ort
/or J +it /or F2 +it
R $dderL)u+tractor 2 R $dderL)u+tractor 2
F +it adder 2 C +it adder 2
R Registers 2J R Registers J0
A +it register 2I A +it register DE
J +it register 2 F2 +it register 2
F +it register 2 C +it register 2
R )hi5t Registers AI R )hi5ter Register B2
)R*2AE>A AI )R*2AE>A B2
R Multi7le;er 2 R Multi7le;er 2
J3to3A 8ulti7le;er 2 F23to3A 8ulti7le;er 2
-a+le C. &evice utili:ation su88ar6
De"i(e U$ili:%$ion S#))%&, ()elected &evice 0 FsI007920J3C)
/%.$ Resources /or J +it /or F2 +it
Nu8+er o5 )lices0 FA out o5 FCJI 0.JEK AFF out o5 FCJI F.DAK
Nu8+er o5 )lice /li7 /lo7s0 IE out o5 DAEJ 0.EIK ACA out o5 DAEJ 2.AAK
Nu8+er o5 I in7ut *#-s0 FI out o5 DAEJ 0.IDK AIE out o5 DAEJ 2.0IK
Nu8+er o5 +onded IBs0 F out o5 AIA 2.A2K F out o5 AIA 2.A2K
Nu8+er o5 .2*"s0 A out o5 J A2.CK A out o5 J A2.CK
-he &evice #tili:ation )u88ar6 sho4s that the 2onvolutional interleaver3deinterleaver 7air uses ver6 5e4
/%.$ resources thus 8a<ing roo8 5or other associated circuitr6 to +e i87le8ented on the sa8e /%.$ chi7.
-he esti8ated 7o4er consu87tion o5 the F2 +it 8odel is 5ound to +e A2C81 (using Xilin; X%o4er
)o5t4areVersion0..FC) 8a<ing the circuit suita+le 5or +atter6 7o4ered a77lications also.
/igure A0 sho4s the i87le8entation o5 convolutional interleaver in Xilin; )7artan F /%.$ <it in the
la+orator6. In7ut toggle s4itches along 4ith *,& indication are 7rovided on the +otto8 o5 the 7icture. -he
second le5t8ost s4itch is used to enter data to the interleaver. -he *,&s on the to7 o5 the 7hotogra7h are used
5or out7ut indication. -he interleaved code 4ord one +it at a ti8e is o+served at the C
th
*,& 5ro8 the le5t. In
order to veri56 success5ul o7eration o5 the interleaver the s6ste8 cloc< 5re9uenc6 is lo4ered 5ro8 J M': to
a77ro;i8atel6 A ': +6 using another V'&* 7rogra8 5or 5re9uenc6 division +6 2
2F
. -his A ': cloc< signal is
also 8ade availa+le at J
th
out7ut *,& to s6nchroni:e the 8anual data in7ut to the interleaver.
/igure A0. %hotogra7h sho4ing i87le8entation o5 convolutional interleaver into /%.$ <it
;0 Con(l#.ion
In this 7a7er 4e have e87hasi:ed the use o5 convolutional interleaving techni9ues to 8aintain data 5idelit6
against +urst errors in digital co88unication. $n e55icient 8odel o5 convolutional interleaver is 7ro7osed. $
V'&* coding o5 the 7ro7osed 8odel is 7re7ared using Xilin; I), tool 4hich is s6nthesi:ed and do4nloaded
into Xilin; )7artan F /%.$. )i8ulation result in the 5or8 o5 ti8ing diagra8 using Model)i8 si8ulation
so5t4are is 7resented 4hich endorses the success5ul o7eration o5 the 8odel. %h6sical veri5ication o5 the 8odel
is 7er5or8ed using in7ut s4itch and out7ut *,&s attached to the in7ut3out7ut 8odule o5 the /%.$ <it. -he
cloc< 5re9uenc6 is lo4ered to a77ro;i8atel6 A ': 5or this 7ur7ose. -he 8odel e55icientl6 utili:es e8+edded
shi5t register o5 /%.$. -his techni9ue reduces /%.$ resource utili:ation u7 to JA K co87ared to other
i87le8entation techni9ue. *esser 7o4er consu87tion and reduced /%.$ interconnection dela6 are the
o+vious i87lications o5 the techni9ue. It also lo4er the 8e8or6 4astage +6 F0 K co87ared to a 7o7ular
i87le8entation techni9ue 5or &$B a77lication. In addition, i87le8entation o5 convolutional de3interleaver
5or $-)2 digital -V receiver also consu8es s8all a8ount o5 /%.$ resources due to our e55icient
i87le8entation techni9ue.
Re!e&en(e
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FIC.
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and a77lication,T IEEE Transactions on Information Theory, vol. C0, no. E, 77. AADD3AAJJ.
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'TS ()th 'ehicular Technology #onference, U.S.A, 77. ID0.
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Theory, Seattle, USA, 77. ABJF ABJD.
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Areas in #ommunications, !ol. *+, no (, 77. JFA3JFD.
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C2C.
!ang, '., Hhong, !., and !ang, *.(ABBB), S$n /%.$ %rotot67e o5 a /or4ard ,rror correction (/,2) &ecoder 5or $-)2 &igital -V,T
IEEE Transaction on #onsumer Electronics, vol. IC, No.2, 77. FJD3FBC.
'anna, ).$.(ABBF), S2onvolutional interleaving 5or digital radio co88unicationsT, Second IEEE International #onference on
,ersonal #ommunications- .ate/ay to the 0*st #entury, vol.0 A, 77. IIF3IID.
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$ltera (200D), S26clone III &evice 'and+oo<, vol. A,T ///.altera.com.
&ivsalar, &., and %ollara, /.(ABBE), SMulti7le -ur+o 2odes 5or &ee73)7ace 2o88unications,T TDA ,rogress 2eport, Jet ,ropulsion
3a%oratory, #alifornia, USA. 77. I23A2A.
)<lar, B.(200E), Digital #ommunications- 4undamentals and Applications, ,ngle4ood 2li55s, NJ0 %rentice 'all.
Xilin; (200C), S#sing *oo<3#7 -a+les as )hi5t Registers ()R*AE) in )7artan3F .eneration /%.$3X$%% IEC,T
http-55///.1ilin1.com
%err6 &.(200A), '$D3- ,rogramming %y E1ample, Frd ,dition, -ata Mc.ra4 'ill, Ne4 &elhi.
Vi Micros6ste8s (200I), SXilin; )7artan F /%.$ -rainer (VV)M30D) #ser Manual,T Version A.0, 2hennai, India.