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Prathamesh Mantri 2818, Ellendale Place, Apt #3 | Los Angeles, CA 90007 | (213) 308-2833 | pmantri@usc.

Master of Science in Electrical Engineering, May 2014
University of Southern California GPA: 3.4
Emphasis: Circuit design/ASIC design and verification
Courses: Mixed Signal IC design, VLSI System Design, Computer Systems Organization,
Management of engineering teams.
Bachelor of Engineering in Electronics and Telecommunications, 2008-12
University of Mumbai, India. GPA: 3.8
EDA tools : Virtuoso Cadence, ModelSim, Xilinx, LTSpice, Synopsis, TetraMax, Primetime, STA
Languages : C, C++, Verilog, Perl, Python, System Verilog.
General Electronics : PCB Designing, Etching and Soldering, Programming of 8051, AVR and PSoC 3 Cs.
Design Concepts : Processor Architecture- Single cycle, Multi-cycle and Pipelined, SRAM, DRAM, CLA,
Decoders, FIFO, sense amplifiers, Op-Amp, Band gap reference.
Student Technical Lead USC ITS LE Jan 2013May 2014
Started as a Student Technical Assistant and was promoted within four months of joining because of my
communication skills and mastery of technology.
Was entrusted the responsibility of training new hires, mentoring Assistants and their periodic evaluations,
interacting with professors and directors of different departments.
Design and synthesis of DDR2 memory controller (Verilog, Synopsis) Dec 2013
Collaborated and conceptualized design of the initial engine, FIFO, scalar and block read/ write functionality
of a DDR2 controller in Verilog and was synthesized and optimized to work in 45nm with a clock of 500MHz.
Verification and Debugging of various designs using industry standard software Dec 2013
Created test bench in Verilog and System Verilog and verified designs.
Learnt various aspects of DFT using TetraMax.
Implemented Automation of verification using Python.
Explored Prime time tool to carry out Static timing analysis.
Developed a code to find-out shortest path between two points (Verilog) Sept 2013
Developed code to read array from SRAM and after developing the shortest path write it back to SRAM.
Achieved the results with lesser no of clocks by reading from and writing to only the cells which are required.
Design and Layout of 8 bit Flash ADC (Virtuoso) June 2013
Created 1.1V high speed low power flash ADC in 45nm technology using CMOS dynamic clocked comparators
and with ESD protection.
Design and Layout of band gap reference (Virtuoso) June 2013
Designed a band gap reference to give a reference voltage of 1.1 V with PVT variations of not more than 5mV.
Design of 2 stage Op-Amp(LTSpice) April 2013
Implemented a 2 stage Op-Amp with a GBW of 1Ghz and a phase margin of 65 dB.
Design and layout of 16-bit pipelined RISC processor. (Virtuoso, Perl) April 2013
Worked in team to design a processor with best area-delay-power product rating.
Integrated Perl scripts to automate the generation of test files and verification of results.
Design and layout of 16-bit wide SRAM. (Virtuoso) March 2013
Achieved minimum area by designing a 16-bit wide 4 banked SRAM with Column Interleaving
Design and layout of 16 bit CLA. (Virtuoso) Feb 2013
Implemented a 16 bit CLA with two levels of dynamic look ahead circuitry.
Design of 5 stage linear pipelined processor (Verilog) Dec 2012
Actualized a MIPS ISA processor with Early branch implementation in Verilog HDL in ModelSim.
Devised a Hazard detection unit and forwarding unit to solve data hazards.
Neural Network of Human Limb (Under Prof. Alice Parker) Spring 2013
Member of research team which was involved in engineering a PID control system in artificial hand using
digital neural circuits.
Director for Publicity, Association of Indian Students , USC
President, Electronics and Telecommunications Students Association 11-12, Vidyalankar Inst. of Tech.