Field Programmable Gate Array

Tutorial
&
SystemVue implementation
Dang Pham
EMLab
Part 1: Tutorial on FPGA
Tutorial on FPGA
Programmable (= reconfigurable) Digital System
Component
o Basic components
Combinational logics (CL)
Flip Flops (FF)
o Macro components
Multiplier ( large combinational logic)
Random Access Memory RAM (Large Density)
Read Only memory ROM (Large Density)
CPU
o Programmable Interconnection
o Programmable Input/Output circuit
o Programmable Clock Generator
FPGA Combination Logic

What is Combination Logic


If output f, g are function of only inputs (A, B, C, D)
then the circuit is combinational circuit.
In another word, output signal is determined by only the combination of
input signals.
o f = func1(A, B, C, D)
o g = func2(A, B, C, D)

Combinational logic does NOT include memories such as Flip-Flops.
Combinational logic can be constructed by just primitive gates such as NOT,
NAND, NOR, etc. (But no feedback loop).
CL
A
B
C
D
f
g
A, B, C, D, f, g are all binary signal.
FPGA Combination Logic






There is no signal loop in the circuit.
In combinational logic, signal loop is prohibited
since the loop makes states (Memory).
Function is not configurable.

FPGA Clock D Latch
1 bit memory by NOR cross-loop
When CLK=1, Q = D, /Q=not(D)
When CLK=0, Q holds previous data.
D
CLK
Q
Q
Q
Q
When CLK=1
D
Q
Q
When CLK=0
D Q
CLK
CIRCUIT SYMBOL:
Master-Slave D Flip-Flop
2 LATCHES in series
Still work as 1 bit memory
CLK edge Trigger Operation
Most commonly used memory element in the
state-of-the-art synchronous Digital Design.
Q only changes CLK edge (once in one cycle).
D Q
D Q
CLK
D Q
CLK
CLK
D
Q
CIRCUIT SYMBOL:
CLK
D
Q 1 1 0 1 0
FPGA = CL + FF
FPGA supports such digital circuit with configurability.
FPGAs basic element is CL + FF

CL
D Q
D Q
D Q
D Q
CL
CL
D Q
D Q
CL
Xilinx XC3000 FPGA structure
XC3000 used original FPGA structure with IOB, CLB, Memory
Xilinx XC3000 IOB
Summary of I/O Options
Inputs
- Direct
- Flip-flop/latch
- CMOS/TTL threshold (chip
inputs)
- Pull-up resistor/open circuit

Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable
(inverse)
Xilinx XC3000 CLB
Each CLB includes a combinatorial logic
section, two flip-flops and a program
memory controlled multiplexer selection of
function. It has the following:
- 5 logic variable inputs A, B, C, D, and E
- a direct data in DI
- an enable clock EC
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and Y
Xilinx XC3000 CLB Interconnection
Xilinx XC3000 CLB Interconnection
Xilinx Virtex Structure
Xilinx introduces Virtex structure with new FPGA products: including
Virtex-4, Virtex-5 upto Virtex-7.
CLB contains of 2 slices
- No connection between slices in
same CLB
- Each slice connect to Switch matrix
to route the sequence.

Xilinx Virtex structure
Xilinx Virtex structure
Slice contains of:
- 4 LUT for logical function
generator
- MUXs
- Carry logic

Slice can provide:
- logic, arithmetic, ROM
function.
- Store data using Block
RAM and shift data with
32bit reg
Xilinx Virtex structure
Xilinx Virtex structure
To increase performance of FPGA in DSP, Xilinx provides Macro
Block, such as: DSP48 Slice, CLK Management and PLL, Low
Power Gigabit Transceivers, Interface with PCIe

Digital Signal Processing DSP48 Slice
Some highlights of the DSP functionality include:
o 25 18 two's complement multiplier/accumulator high-resolution
(48 bit) signal processor
o Power saving pre-adder to optimize symmetrical filter
applications
o Advanced features: optional pipelining, optional ALU, and
dedicated buses for cascading
Summary of Xilinx Virtex-7
Part 2: FPGA prototyping
with Agilent SystemVue
Fixed-Point Representation
SystemVue FixedPoint Data Type has the computational behavior of
SystemC
TM
2.2 fixed point type based on IEEE Std. 1666
TM
Language
Reference Manual (LRM). The fixed point representation based on that
standard is as follows:
FxpDataType<WL, IWL, IsSigned, Q_mode, S_mode, n_bits>
where,
o WL - total wordlength,
o IWL - integer wordlength,
o IsSigned - Unsigned number for Zero and Signed Number for One.
o Q_mode - Quantization mode; determines the behavior when the number to be represented
requires more precision than is available
o S_mode - Saturation mode; determines the behavior when the number to be represented is
outside the dynamic range covered
o n_bits - number of saturated bits (used by Saturation mode)

Fixed-Point Representation
FxpDataType<WL, IWL, IsSigned, Q_mode, S_mode, n_bits>
Fixed-Point Representation
Same bits, different fixed-point representation
interprets to different value!

Read more on Saturation and Quantization in SystemVue Tutorials
Fixed-Point HDL Block
in Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrain
MuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxp
OR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Simple Combination logic Block
- Bit Manipulation
- Fixed-Point Conversion
- LUT


Fixed-Point HDL Block
in Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrain
MuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxp
OR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
HDL Block with different Clock
of Data Input and Data Output
Fixed-Point HDL Block
in Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrain
MuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxp
OR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Complex HDL Block with pre-
designed function:
- Multiply
- FFT
- RAM, ROM, Register
Fixed-Point HDL Block
in Agilent SystemVue
Fixed-Point for CL Fixed-Point for Multirate Fixed-Point for Macro Hdl Cosimulation
ABS Fxp DownSampleFxp CORDIC RotationFxp HDL
BitMergeFxp UpSampleFxp CORDIC VectoringFxp HIL
CompareConstFxp CounterFxp XilinxIPIntegrator
CompareFxp ParToSerFxp FFT Fxp
ConstFxp SerToParFxp FIR Fxp
ExtractFxp PulseTrain
MuxFxp TriggeredWaveFormFxp
LookUpTableFxp
MapperFxp SPRamFxp
AND Fxp MpyFxp
NAND Fxp DivFxp
NOR Fxp GainFxp
NOT Fxp SqrtFxp
OR Fxp AddFxp
XNOR Fxp AddCarryFxp
XOR Fxp AccumulatorFxp
LatchFxp SubFxp
RegisterFxp
FloatToFxp ShiftFxp
FxpToFloat DPRamFxp
FxpToFxp DelayFxp
Co-simulation block:
- To use available HDL code
- To co-simulation IP from
Vendor.
HDL Code Generation
with Fixed-Point
The HDL Code Generation capability in SystemVue provides an easy
path from schematic design to hardware. The flow starts by creating
SystemVue sub-network model using synthesizable Fixed-Point parts
from Hardware Design Library, as well as imported HDL code through
the HDL cosim block and XilinxIPIntegrator.
1. HDL only: generates the HDL files of the synthesizeable fixed point parts inside the sub-
network in addition to several additional HDL files for simulation, clock and reset handling.
2. Xilinx FPGA: in addition to the HDL files, a Xilinx ISE project is created to target Xilinx FPGA
devices (Virtex 4/5/ and 6)
3. Altera FPGA: in addition to the HDL files, a Quartus II project is created to target Altera FPGA
devices (Cyclone IV E/GX,Stratix IV, Stratix V).

E.g: HDL Code Generation
with Fixed-Point
Modulo Counter
If (Reset = 1)
Output = 0;
else
if(En = 0)
Output(n) = Output(n-1);
else
Output(n) = Output(n-1) + CountStep;
if (Output > Count2Thres)
Output = 0;
endif
endif
endif
Parameter:
CountStep: Increase value (default=1)
Count2Thres: Count from 0 to this value
IntLen: number of bit
E.g: HDL Code Generation
with Fixed-Point
Modulo Counter
E.g: HDL Code Generation
with Fixed-Point
Modulo Counter Subnetwork
E.g: HDL Code Generation
with Fixed-Point
Modulo Counter Timing
E.g: HDL Code Generation
with Fixed-Point
HDL Code Generation.
Target:
1. HDL file only
2. Xilinx FPGA
3. Altera FPGA

Select Xilinx FPGA and
detail option to trigger
Xilinx ISE Project.

More detail information in Help and
Examples
E.g: HDL Code Generation
Setup and Config
Paths of Mentor Graphics
Modelsim and Xilinx ISE
for HDL Code Generation,
Co-simulation.

!Note:
- Modelsim Student Edition cannot
be used for co-simulation.
- SystemVue only uses ModelSim
SE 32-bit for Cosimulation.
E.g: HDL Code Generation
Setup and Config
SystemVue:
- Fixed-point design and simulation
- Generate VHDL/Verilog codes
- Cosimulate custom VHDL/Verilog code
- Export project to Xilinx ISE for FPGA Prototype
ModelSim
- Verify HDL codes with testbed
- To program custom
VHDL/Verilog
Xilinx ISE Design Suite
- FPGA Prototype
- Timing Constrains and
Area Constrain
- Floor Planning
- I/O pins
- Interfaces: UART, PCIe,
DDR.
- XilinxIP Cores: FFT, Error
Corrections..
E.g: HDL Code Generation
with Fixed-Point
ModelSim Project.
Test Vector and Testbed generated by SystemVue
E.g: HDL Code Generation
with Fixed-Point
Xilinx ISE -> View RTL Schematic
View with HDL block and Macro
E.g: HDL Code Generation
with Fixed-Point
Xilinx ISE -> View Technology Schematic
View with actual CLB
E.g: HDL Code Generation
with Fixed-Point
Xilinx ISE -> Design Summary
Slices used = 18
4LUT = 32
Read more
[1]. SystemVue 2013.01 Tutorial
[2]. FPGA Prototype with Agilent SystemVue
[3]. Examples in SystemVue

Practice more!
Enjoy more!