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Lab Manual February 3, 2006
Encounter
RTL Compiler
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Table of Contents Encounter RTL Compiler
February 3, 2006 Cadence Design Systems, Inc. iii
Table of Contents
Encounter RTL Compiler
Module 1 Introduction to the Encounter RTL Compiler
Lab 1-1 Exploring the Design Hierarchy ...................................................................................... 1-1
Setting Up the Environment....................................................................................... 1-2
Navigating the Hierarchy........................................................................................... 1-4
Reading Constraints and Running Synthesis ............................................................. 1-6
Using the Graphical Interface .................................................................................... 1-7
Module 2 Design Constraints
Lab 2-1 Applying Design Constraints........................................................................................... 2-1
Setting Up the Environment....................................................................................... 2-1
Setting Load and Design Rule Checks....................................................................... 2-2
Setting Clocks ............................................................................................................ 2-3
Applying External Delays.......................................................................................... 2-4
Applying Path Exceptions.......................................................................................... 2-5
Module 3 Synthesis Flow
Lab 3-1 Exploring the Synthesis Flow.......................................................................................... 3-1
Setting Up the Environment....................................................................................... 3-1
Defining Cost Groups ................................................................................................ 3-2
Estimating Physical Wire Delays............................................................................... 3-2
Running a Generic Synthesis..................................................................................... 3-3
Mapping to a Target Library...................................................................................... 3-3
Running Incremental Synthesis ................................................................................. 3-3
Analyzing Reports ..................................................................................................... 3-5
Module 4 Low Power Synthesis
Lab 4-1 Running Low Power Synthesis........................................................................................ 4-1
Using Clock Gating.................................................................................................... 4-1
Setting Up the Environment....................................................................................... 4-2
Setting Up for Low Power Synthesis......................................................................... 4-2
Annotating RTL-Switching Activity ......................................................................... 4-3
Running Low Power Synthesis.................................................................................. 4-5
Annotating Gate-Switching Activity (Optional)........................................................ 4-6
Reporting Power ........................................................................................................ 4-7
Encounter RTL Compiler Table of Contents
iv Cadence Design Systems, Inc. February 3, 2006
Module 5 Design for Testability
Lab 5-1 Running Low Power and Scan Synthesis ........................................................................ 5-1
Setting Up the Environment....................................................................................... 5-1
Estimating Physical Wire Delays............................................................................... 5-2
Setting Up for Scan Synthesis.................................................................................... 5-2
Inserting Shadow DFT............................................................................................... 5-3
Fixing DFT Violations............................................................................................... 5-4
Running Scan Synthesis............................................................................................. 5-4
Annotating Switching Activity .................................................................................. 5-5
Configuring the Scan Chains ..................................................................................... 5-5
Running Incremental Synthesis ................................................................................. 5-5
Connecting Scan Chains ............................................................................................ 5-6
Generating Reports .................................................................................................... 5-6
Saving the Design ...................................................................................................... 5-7
Module 6 Interface to Other Tools
Lab 6-1 Interfacing with Other Tools............................................................................................ 6-1
Changing Names of Design Objects.......................................................................... 6-1
Removing Assign Statements from the Netlist.......................................................... 6-2
Adding Isolation Buffers on Input and Output .......................................................... 6-2
Controlling the Bit-Blasting of Bus Ports.................................................................. 6-3
Ungrouping the Hierarchy ......................................................................................... 6-3
Terminology Conventions
2/3/06 Cadence Design Systems, Inc. v
Mouse Use and Terminology
The basic uses of mouse buttons are shown in this graphic.
Term Action Icon Example
click Quickly press and release the specied mouse button.
On menus and forms, you use the left mouse button
most of the time.
double click Rapidly press the specied mouse button twice.
Shift-click
Control-click
Shift-Control-click
Hold down the appropriate key or keys and click a
specied mouse button.
draw through Dene a box by clicking the mouse at one corner of the
box, moving to the diagonally opposite corner with the
mouse button held down, and releasing the button.
pop up Press the middle mouse button.
pull down Move the mouse cursor to the menu name on the menu
banner, press and hold the left mouse button, move the
cursor down to highlight the menu selection, release the
mouse button to execute the selection.
Enter Type a command in a window and press Return to
execute the command.
Select Position the cursor over a command and press the left
mouse button. Choose or pick are synonyms for select.
Click left
Double
click
2
Shift
Shift- click right
Draw
through
Click
middle
To repeat last command
To undo points in a graphic
Click or select button
To choose commands
To select options on forms
Pop-up menu button
To pop up menus
To pop up options windows by double clicking
To draw objects
To select menu command on pop-up menus
Conventions Terminology
vi Cadence Design Systems, Inc. 2/3/06
Labs for Module 1
Introduction to the Encounter RTL Compiler
2/3/06 Encounter RTL Compiler 1-1
Lab 1-1 Exploring the Design Hierarchy
Lab 1-1 Exploring the Design Hierarchy
Objective: To run synthesis, to explore the design hierarchy,
and to analyze reports.
The example design provided with this module is a Verilog
description of a
Dual Tone Multi-Frequency (DTMF) receiver. In a telephone network,
DTMF is a common in-band signaling technique used for transmitting
information between network entities. DTMF signals are commonly
generated by touch-tone telephones.
Figure 1-1. DTMF Chip
1-2 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
You need the following files to run the synthesis:
I Synthesis library
I Verilog or VHDL netlist, preferably at RTL level.
I Constraints
This is the lab directory structure.
Figure 1-2. Lab Directory Structure
Setting Up the Environment
1. Change to the work directory by entering this command:
cd rc52lab/work
2. Start the tool by entering this command:
rc -gui -logfile dtmf_chip1.log
This command opens up the graphical interface.
You can type any command interactively at the rc:/> shell prompt.
Important
You must view files in a separate xterm window, and not in the rc shell.
library
rc52lab
rtl
tcl
Verilog files
Tcl scripts
Library files
Lab run directory
work
Simulation files
sim
Additional files
etc
2/3/06 Encounter RTL Compiler 1-3
Lab 1-1 Exploring the Design Hierarchy
3. Using the rc:/> shell prompt, hide the graphical interface by
entering:
gui_hide
Tip: When you enter gui* at the rc shell, you see a list of graphical
interface (GUI) commands.
4. View the setup.g file under the tcl directory.
5. Set the environment by entering:
include ../tcl/setup.g
6. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
set_attr avoid true SDFF*
You do not have to specify the path. The library search path was set
using the setup.g script.
7. Read the Verilog
HDL by entering:
read_hdl ${FILE_LIST}
8. Elaborate the design by entering:
elaborate dtmf_chip
The log displays a message related to creating a control flow graph
of your design. In a real design scenario, you typically attend to the
messages in detail. In this lab, you will look for any unresolved
instances.
Most typical messages, you see are CWD-#, DW-# or CDFG-#.
The CWD and DW messages are implementations of ChipWare or
DesignWare.
You can find these messages later in the /messages directory of the
rc:> shell.
The elaboration must finish with the message Done elaborating....
9. In the log file, find any unresolved instances.
Answer: ___________________________________
1-4 Encounter RTL Compiler 2/3/06
Exploring the Design Hierarchy Lab 1-1
Navigating the Hierarchy
Use the navigational commands to explore the hierarchy and to view the
attributes of design objects.
This figure illustrates the hierarchy of the design objects.
Figure 1-3. Design Hierarchy
Important
The directory structure within the compiler shell is similar to the UNIX
directory structure. Make sure you are entering your compiler commands in
the rc shell.
1. List all the attributes possible on a design object in the design
hierarchy by entering:
ls -l -a [find / -design dtmf_chip]
Notice that this ls command works just like the UNIX command.
2. As in the previous step, find the attributes of the following design
objects:
subdesign tdsp_core
instance EXECUTE_INST
port refclk
port reset (top-level port)
pin reset in the EXECUTE_INST instance
3. Change to the dtmf_chip directory under the designs directory.
cd /designs/dtmf_chip
libraries
/ (ROOT)
HDL Information (GTECH, DW...)
Design Information
Library Information (cells, wire loads...)
Printed Message Information
hdl_libraries
designs
messages
2/3/06 Encounter RTL Compiler 1-5
Lab 1-1 Exploring the Design Hierarchy
4. Navigate through the design hierarchy and the subdirectories and list
the attributes of some of the design objects.
5. Open a separate window and examine the list_subdes.tcl file under
the tcl directory.
The Tcl-based script finds all the subdesigns in the top-level design.
6. In the compiler shell, change back to the root directory:
cd /
7. Load the list_subdes.tcl script into the compiler by entering:
include list_subdes.tcl
You do not have to specify the path. The Tcl search path was set
using the setup.g script.
8. Enter the following command:
list_subdes
This command returns a list of all the instances with their directory
paths in the design hierarchy. Many such commands are in the
load_etc.tcl file under the software installation directory.
9. Some instances in this output are datapath components inferred by
the Encounter
RTL defined in
the setup.g file.
6. Elaborate the design.
dtmf_chip is the top-level module.
2-2 Encounter RTL Compiler 2/3/06
Applying Design Constraints Lab 2-1
7. Check the design for any problems.
check_design
What type of problems are reported?
Answer: _________________________________________
In a normal design scenario, you identify and fix the design
problems. None of the problems in this design are worth attending
to.
Therefore, go to the next step.
Setting Load and Design Rule Checks
1. Set the capacitance loading on all output ports at the top level to 2
times the load capacitance on the PAD pin of the PDIDGZ library
cell.
A nested set of find commands locates the load attribute of the pin
and assigns it to a variable called cap.
The Tcl expression [expr x * y] specifies the capacitance load on the
external_pin_cap attribute of the output ports.
2. Use ls -l -a and/or get_attribute on the tdigit_flag output port and get
the value of the external pin capacitance.
Answer: _____________________________________
What is the unit for capacitance?
Answer: _____________________________________
3. The external driver attribute on all input ports point to the
PDO04CDG library cell.
set cap [get_attr load [find [find /lib* -libcell PDIDGZ] -libpin PAD]]
set_attr external_pin_cap [expr 2*$cap] [all_outputs]
set_attr external_driver [find [find /lib* -libcell PDO04CDG] \
-libpin PAD] [all_inputs]
2/3/06 Encounter RTL Compiler 2-3
Lab 2-1 Applying Design Constraints
4. Remove the driver settings from the reset and the refclk pins.
This is usually done to prevent the buffering of the large nets during
design rule fixing. You might want to add clock trees for these nets
later in the design cycle.
5. Set max_fanout of 15 on all input pins by entering:
set_attr max_fanout 15 [all_inputs]
6. Remove the max_fanout setting from refclk and reset pins by
entering:
The max_fanout setting is a design rule check that will create a
violation for nets that exceed a specified fanout limit.
Setting Clocks
1. Set up the top-level clock.
2. Define the internal clocks of the design.
The system clock refclk goes to a PLL that produces the generated
clocks clk1x at the same frequency and clk2x at half the frequency
of the port clock refclk.
These clocks feed the TEST_CONTROL_INST, which selects
between the scan and regular clock for each of the modules in the
design.
set_attr external_driver "" [find /des* -port ports_in/reset]
set_attr external_driver "" [find /des* -port ports_in/refclk]
set_attr max_fanout "" [find /des* -port ports_in/reset]
set_attr max_fanout "" [find /des* -port ports_in/refclk]
set refclk [define_clock -p 6000 -n refclk [find /des* -port \
ports_in/refclk]]
set m_clk [define_clock -name m_clk -period 6000 \
[find [find / -instance TEST_CONTROL_INST] -pin m_clk]]
foreach CLOCK {m_rcc_clk m_spi_clk m_dsram_clk m_ram_clk m_digit_clk} {
set clock [define_clock -name ${CLOCK} -period 12000 \
[find [find / -instance TEST_CONTROL_INST] -pin ${CLOCK}]] }
2-4 Encounter RTL Compiler 2/3/06
Applying Design Constraints Lab 2-1
3. Create a latency of 2000 ps on the internal clocks by entering:
4. Model an uncertainty of 250 ps on all clocks by entering:
5. Model a fall transition and rise transition on the refclk of 20 ps on
the rise and fall edges by entering:
set_attr slew_fall 20 $refclk
set_attr slew_rise 20 $refclk
Applying External Delays
1. Set the input delay of 500 ps on all input ports and an output delay
of 500 ps on all output ports with respect to refclk.
2. Find the external output delay on the port tdigit[0] from a suitable
report of timing.
Answer: _____________________________________
Tip: Use report timing -to [find / -port port_name].
3. Set the refclk to ideal driver to avoid applying design rule constraints
to it.
In the Encounter
-XL
simulator in a separate terminal window.
However, in this case, the TCF file is generated for you.
3. View the ../sim/top.hier.rtl.tcf file.
The generated TCF contains two sets of numbers. One represents the
probability of the signal, and the other represents the number of
times the signal has toggled. The net and instance probabilities are
given separately.
set_attr lp_clock_gating_style latch /designs/dtmf_chip
4-4 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
4. Read the RTL TCF file into the compiler.
read_tcf ../sim/top.hier.rtl.tcf
5. From the log file, gather the following information:
What is the number of pins in the TCF file?
Answer: _________
What is the coverage of this TCF?
Answer: _________
What is the total number of nets in the design?
Answer: _________
6. Report the power consumption of the design by entering:
report power -depth 1
What is the total leakage power consumption of the design?
Answer: ___________________________
What is the total switching power consumption of the design?
Answer: ___________________________
What is the total internal power consumption of the design?
Answer: ___________________________
What is the total net power consumption of the design?
Answer: ___________________________
What is the relationship between Net power, Internal power and
Switching power?
Answer: ___________________________
What is the total power consumption of the design?
Answer: ___________________________
What are the top-level blocks of the design?
Answer: ___________________________
2/3/06 Encounter RTL Compiler 4-5
Lab 4-1 Running Low Power Synthesis
7. Change the unit of power by entering:
set_attr lp_power_unit uW /
Do a report power and verify the units and data.
Note: The power annotation during mapping is not affected by the
lp_power_unit attribute.
Running Low Power Synthesis
Low power synthesis is included as part of the synthesis process.
1. Set the maximum leakage power attribute.
2. Set the maximum dynamic power attribute.
3. Synthesize the design:
synthesize -to_mapped -effort medium
Multi-VT optimization and leakage power optimization are run at
this stage.
This step takes about 5 minutes in Linux and 15 minutes in Solaris.
To get the CPU run time use the runtime root attribute.
4. Save the mapped netlist by entering:
write_hdl > dtmf_chip.lps.v
5. Report the power consumption of the gates by entering:
report gate -power
How many instances are from the slow_highvt library?
Answer: _____________________
How many instances are from the slow_normal library?
Answer: _____________________
set_attr max_leakage_power 100 /designs/dtmf_chip
set_attr max_dynamic_power 100 /designs/dtmf_chip
set_attr lp_power_optimization_weight 0.5 /designs/*
4-6 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
6. Report the power consumption of the design by entering:
report power -depth 1
7. Report the datapath information by entering:
report datapath
The compiler automatically runs datapath operations unless you turn
them off using the dp_perform_* root attributes.
Are there any datapath modules? If so what type?
Answer: __________________________
8. Run incremental optimization.
synthesize -incr -effort high
Incremental optimization maps the logic added prior to this stage
and runs some additional delay and area transformations.
9. Write out the mapped netlist.
write_hdl > dtmf_chip.lps1.v
Annotating Gate-Switching Activity (Optional)
At this stage, you run the gate-level simulation of the design. You use
gate-level switching activity to better analyze and estimate the power.
1. View the ../sim/sim_gate.opt file.
2. Normally at this stage, you run a simulation with the Verilog-XL
simulator in a separate terminal window.
However, in this case, the TCF file is generated for you.
3. View the ../sim/top.hier.gates.tcf file.
4. Read the gate-level TCF file into the compiler.
From the log file, gather the following information:
What is the coverage of this TCF?
Answer: _________
2/3/06 Encounter RTL Compiler 4-7
Lab 4-1 Running Low Power Synthesis
Reporting Power
1. Report the clock gating.
report clock_gating
2. Report the power.
report power -depth 2
3. Close the software.
End of Lab
4-8 Encounter RTL Compiler 2/3/06
Running Low Power Synthesis Lab 4-1
Labs for Module 5
Design for Testability
2/3/06 Encounter RTL Compiler 5-1
Lab 5-1 Running Low Power and Scan Synthesis
Lab 5-1 Running Low Power and Scan Synthesis
Objective: To insert clock gating for power optimization. To
insert scan chains to improve the testability. To
optimize the leakage power.
Setting Up the Environment
In this section, you set the environment of the synthesis session, load the RTL
files, and elaborate the top-level design.
1. Change to the work directory:
cd rc52lab/work
2. Start the tool by entering and set the environment by entering:
rc -f -gui ../tcl/setup.g -logfile
dtmf_chip.dft.log
3. Enable clock-gating features before elaboration by entering the
following commands:
set_attr lp_insert_clock_gating true /
4. Read the libraries and specify the cells to avoid by entering:
set_attr library $LIBRARY /
The SDFF* cells avoided in previous sessions will now be required
for scan insertion.
5. Load the Verilog