Sept.

13, 2014 to Oct 19, 2014

Course Objectives:
This is an introductory course in VLSI Systems and Design. At the completion of this
course, a student should be able to design and analyze digital circuits, incorporating into a
VLSI chip. They should be able to design for performance, work in small groups and bring
together design components into a full custom chip.
Workshop Details:
Section1: Introduction to VLSI basics. (1 Week)
MOS Devices, CMOS Inverter
Basic MOS transistors, Enhancement
Mode transistor action, Depletion
Mode transistor action, NMOS and
CMOS fabrication.
Ids versus Vds relationship, Aspects
of threshold voltage. The nMOS
inverter, Pull up to Pull-down ratio
for aNMOS Inverter and CMOS
Inverter (Bn/Bp), MOS transistor
circuit Model, Noise Margin.
Combinational logic
The inverter, Combinational Logic,
NAND Gate NOR gate, Compound
Gates, 2 input CMOS Multiplexer,
Memory latches and registers,
Transmission Gate, Gatedelays,
CMOS-Gate Transistor sizing, Power
dissipation.
Sequential logic
Latch, Flip flops, registers
CMOS logic
2 input CMOS Multiplexer, Memory
latches and registers, Transmission
Gate, Gatedelays, CMOS-Gate
Transistor sizing, Power dissipation.
Adders, Multipliers, Memory structures
Section2: Introduction to Verilog basics.
Class: (2 Days)
Language Introduction
Understanding of language basics
HDL building blocks including
modules, ports, processes and
assignments.
Understanding of behavioral code
style and structural code style.
Understanding and use of Operators,
Control statements, Variable
assignments, Task and functions
Labs: (5 Days)
Write RTL for assigned project
Section 3: Introduction to Logical Synthesis
basics.
Class: (2 Days)
Understanding of Library Files
Understanding of Technology Files
Understanding of IO Constraints
Understanding of Synopsys Design
Constraints
Different EDA tools and its file
formats
Understanding of Logic synthesis.
Labs: (5 Days)
Complete RTL synthesis for assigned
project

Section 4: Introduction to Physical Design.
Class: (3 Days)
Module 1: Floorplanning
Why floorplanning goals and
objectives
Aspect Ratio
I/O Core Clearance
Flip/Abut
Macro Placement
Module 2: Power Planning
Why power planning, Various
methods
Power mesh
Core Power Rings
Macro Power Rings
Straps and trunks
Layers for power planning
Module 3: Placement
What is placement goals, and
objectives
Basics of Placement
Inputs/Outputs
Placement flow/Placement steps
Placement Constraints
Pre place and In placement
Optimization Techniques
Congestion Analysis
QOR Checks & Final Checks

Module 4: Clock Tree Synthesis
What is CTS, Goals, and Objectives
Inputs, and Outputs
Optimization Procedures
Clock Buffers, Skew, Latency, Clock
DRV
Timing Checks
Post Clock Optimization
Clock Routing
Hold Fixing
QOR Checks
Module 5: Routing
What is routing
Different types of Routing
Timing Driven Routing, Congestion
Driven Routing, Global Routing
Track Assignment
Detail Routing
DRC, Search and Repair
Post Route Optimization
QOR Checks
Module 6: Timing
Why Timing Analysis
What is STA
Parasitic Extraction, Extraction
Corners
Performing Analysis
Setup and Hold Timing
Wireload Models
Net and Cell Delay Calculation
Source and Network Latency
QOR Checks
Module 7: Physical verification
Post Layout Verification
DRC, LVS, ERC.
Labs: (2 Weeks)
Complete Physical design for
assigned project.
Complete project documen

Learning Outcomes:
By completing this course, the students are expected to have obtained
Knowledge of fundamentals of VLSI Design principles,
Experience of designing a full custom Integrated circuit chip working in a design team
Skills to communicate their design experience through a detailed report and a short
presentation to the class