Department of Electrical

Engineering
King Fahd University of Petroleum and Minerals
Dhahran - Saudi Arabia
Laboratory Manual
EE 200 Digital Design
August 2003
PREFACE
his document has been prepared to serve as a laboratory manual for EE !"" Digital
Design course for electrical engineering students# he manual consists of a set of
e$periments designed to allo% students to build& and verify digital circuits and systems#
his set of e$periments cover relevant topics prescribed in the syllabus and are designed
to reinforce the theoretical concepts taught in the classroom %ith practical e$perience in
the lab# 'y the end of the course& students are e$pected to have a good understanding of
digital logic design and implementation %ith SS( and MS( devices#
2
)(S *F E+PE,(ME-S
EXP
#
0
1
2
3
4
5
6
7
8
9
10
11
EXPERIMENT PAGE
INTRODUCTION TO LAB EQUIPMENT 6
BINARY AND DECIMAL NUMBERS 10
DIGITAL LOGIC GATES 12
INTRODUCTION TO LOGIC WORKS 17
BOOLEAN ALGEBRA 18
SIMPLIFICATION 22
CODE CONVERSION 25
ADDERS/SUBTRACTORS 29
MULTIPLEXERS 34
DESIGN WITH ROM`S 38
FLIP-FLOPS 39
COUNTERS AND SEQUENTIAL LOGIC 42
APPE-D(+ (LABORATORY REGULATIONS AND SAFETY 46
RULES)
3
EE-200 DIGITAL LOGIC DESIGN INTRODUCTION
LAB GUIDELINES
PRE-LAB
Each student %ill do his o%n pre-lab# (t is intended in this course to increase the
student.s utili/ation of P01 therefore& the pre-lab %rite up must be typed# his same
%rite up should be modified to be submitted as the )ab report#
Starting from )ab 2& all pre-lab must be done using )ogic3or4s simulation pac4age#
During the )ab& each student may be as4ed about the simulation results# All circuit
parts %ith pin numbers should be included in the pre-lab so that you %ill be ready to
start connecting the hard%are in the lab# ry to investigate all possible changes on the
circuit to ac5uire full 4no%ledge about your design# All 5uestions in the )ab handout
should be ans%ered based on the )ogic3or4s results# he pre-lab %ill ma4e 267 of
the total grade of the )ab e$periment#
THE LAB
During the lab& the students should %or4 as a group# he Pre-)ab results from each
student in the group %ill compared and the circuit the produces the best results %ill
be implemented using hard%are parts# Elaborate on your conclusion about the
observations about the simulated and obtained results# Punctuality of attendance to
the )ab is %orth 67 and the active participation on the e$periment %ill count as 2"7
of the total grade#
THE LAB REPORT
Each student should have his o%n report# he lab reports are intended to serve t%o
e5ually important purposes# First& they indicate your technical comprehension of the
topics addressed in the labs& and second& they indicate your ability to present and
discuss your results in a clear and concise manner# 8ou %ill be graded on both
aspects of your report#
he suggested format for your lab report is given belo%#
1. Objectives: State clearly %hat you set out to achieve in this lab# (f this differs
from %hat you finally achieved& e$plain it in the 90onclusions9 section# Please
do not copy the ob:ectives verbatim from the lab handout# hin4 about it&
interpret it& and e$plain it the best you can& in your o%n %ords#
2. Parts: )ist all the parts you used in the design#
3. Design and Test Procedure: For each subsection of the lab& e$plain the
follo%ing;
4
(1)Step-by-step description of %hat you did# (nclude as many details
as possible& and once again& %rite it in your o%n %ords#
(2) All necessary calculations as %ell as all pin-to-pin circuit diagrams
of your design# Please ma4e sure your figures are consistent& legible
and %ell labeled#
(3)8our testing procedure# E$plain ho% you %ent about testing
your design# Did you try testing critical individual bloc4s first<
4. Results and Answers to Questions: For each subsection of the lab& present
your results in a clear and concise manner =label graph a$es& include all units
of measurement># -ote do%n all your observations& even if you %ere not
specifically as4ed for them in the handout# (nterpret your results and discuss
the accuracy of your measurements# Additionally& ans%er all 5uestions listed
in the lab handout#
5. Conclusions; (n this section you should attempt to ans%er the 5uestions;
3hat did you learn from this lab< 3hat did you do %rong =or %hat %ent
%rong>< ?o% could you have improved upon your design and test
procedures< 3ere your results as e$pected or did you find something
unusual# ry not to include information that you have included in previous
sections# Present the significance of your results conceptually& if applicable&
=e#g# he 0AD tool does not capture the glitching behavior accurately#>
he )ab ,eport %ill count as 2"7 of the grade and is due at the beginning of the
subse5uent lab e$periment#
5
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #0
(-,*DU0(*- * )A' E@U(PME-
OB1ECTIVE:
1 o get ac5uainted %ith the breadboard and the cathode ray oscilloscope#
APPARATUS:
1- Dual Atrace oscilloscope
2- Digital Proto-'oard
THEORY:
See sections B-!& and B-C in the boo4#
PB-503-C Analog/Digital Proto-Board:
he P'-6"2-0 AnalogDDigital Proto-'oard is a self-contained digital logic
laboratory# (t includes a E6 volt po%er supply that provides operation po%er to the
circuits under test& and also serves a F.B.. logic level for ) =transistor-transistor
logic> integrated circuits# he F.".. logic level is represented by connection ground#
)ocated on the front panel =see Fig B> is a 'readboarding Soc4et that contains over
!6"" tie points# hese tie points are divided into 2GH sets of five electrically
interconnected solderless tie points& G sets of !6 interconnected solderless tie points
along the right and left edges& and H sets of 6" interconnected solderless tie points on
the top of the board# ie points are spaced "#B inch apart and %ill accommodate the
pins of D(P Idual-in-line pac4age> integrated circuits& as %ell as a %ide variety of
other circuit components# he four groups of tie points =6" tie points each> at the top
of the breadboarding are connected to E6J& an ad:ustable =E6& B6J>& an ad:ustable =-
6& -B6J>& and a ground connection& respectively# (n the EE!"" )ab e$periments& %e
%ill only use the E6J ro% and the ground ro% of tie points# he eight larger groups
of tie points =!6 tie points each> are handy %here large number of connections are to
be made to a common circuit point& e#g#& e$tending the ground& E6volt& etc#
*ther useful features of the P'-6"2 include;
1- Function Kenerator; he multi-%aveform function generator provides
continuously variable fre5uency signals from "#B?/ to B""K?/# he fre5uency is
selected in three ranges& %ith each range covering t%o-decades# he generator
produces& sine& triangle& and s5uare %aveforms#
2- )ogic (ndicators; A ban4 of eight )EDs is provided for use as built-in logic
indicators# he )EDs are active high =they light> to indicate a Llogic oneM
condition#
3- Debounced Pushbuttons =Pulsers>; t%o manual& bounceless =digitally conditioned>
pulser buttons P'B and P'!#
4- S%itches; An eight-pole D(P s%itch provides a convenient source of digital outputs#
All eight s%itches have one side connected to a common lead& %hich may be
s%itched to either E6 volts or ground# he remaining sides of all eight s%itches are
separate& available& and uncommitted# his arrangement ma4es connecting special
digital circuitry such as an eight-bit input port 5uic4 and easy# (n addition to
6
the eight-pole s%itch& there are t%o single pole& double thro% =SPD> s%itches
provided for general s%itching functions#
1- Potentiometers; %o potentiometers are provided on the P'-6"2# he resistance
values chosen =B K and B" K ohms> may be used in common circuit applications#
2- '-0 0onnectors; he P'-6"2 may be connected to other pieces of e5uipment via
t%o '-0 connectors '-0 NB and '-0 N!# hese allo% the use of shielded cable
to minimi/e noise and interference#
Fig#B P'-6"2 Panel layout#
IC PIN CONNECTIONs:
he (0 type OHP2 is in a BH-pin dual in-line case# he base pins progress in a counter-
cloc4%ise direction as seen from the side a%ay from the pins& as sho%n Fig !# Pin B
is located by an identifying symbol& or the location of pins B and BH are identified by
an inde$ notch at the end of the case %here pins B and BH are located#
BH B2 B! BB B" P G
(nde$ op vie%
notch
B ! 2 H 6 C O
a%ay from pins
Fig.2 IC pin location, 14 pin dual-in-line (TO-116) cae
PROCEDURE:
7
THE PB-503
1. 0onnect the P'-6"2 line cord into the A0 po%er supply and turn on the po%er
s%itch#
2. 0onnect the )*K(0 (-D(0A*,S =lamp monitor> =B& !& Q&G> to E6 volts# he
lamps monitors should light %hen connected E6 volts and this L*-M lamp
condition %ill represent a LlM logic level in your e$periments#
3. -o% connect the lamp monitors to ground# hey should all be off at this time#
his L*FFM; lamp condition %ill represent a L"M logic level in your e$periments#
4. 0onnect one side of a resistor =!" ohms& to B"" K> to ground and the other side to
D(P s%itch SB-B and s%itch the 6 JDK-D s%itch to 6 volts position =hese steps
are already done for you># 0onnect SB-B to )ED-B# -o%& %hen the SB-B is
pushed up to the closed position )ED-B %ill light& and %hen the SB-B is brought
bac4 to the open position the )ED %ill be off# ,epeat these steps for SB-!
through SB-G and observe the resultant condition of the lamp monitors#
Switch position lamp logic level
0)*SED *- B
*PE- *FF "
he s%itches can& thus& be used to supply logic level inputs to e$perimental
circuits#
5. PU)SE, 'U*-S# 0onnect one side of a resistor =!" ohms& to B"" K> to
E6 volts and the other side to P'B-B& the -0 point# hen connect P'B-B =the
other lead of -0 point> to )ED-B# he )ED should light %hen P'B is pressed
and e$tinguish %hen P'B is released# -e$t& move the connections from P'B-B
to P'B-!& the -* point# -o% the )ED should be lit %hen P'B is not pressed
and go off %hen P'B is pressed# ,epeat these steps for P'!# hese buttons
%ill be used to enter momentary pulses of L*M and LBM logic levels#
6. Single Pole& Double hro% =SPD> s%itches# 0onnect one side of a resistor
=!" ohms& to B"" K> to E6 volts and the other side to lead B of S!# hen
connect lead ! to )ED-B and )ead 2 to )ED-!# 3hen the s%itch is brought to
the up position then )ED-B and )ED-! %ill be *- and %hen the s%itch is
brought do%n& the t%o )ED.s %ill be off# ,epeat these steps on S2# hese
s%itches are provided for general s%itching functions#
7. 0)*0K output# 0onnect the FU-0(*- KE-E,A*, output ) to )ED-
B# Set the function generator to Ltimes BM position and move the fre5uency
control all the %ay to the top# Set the fre5uency selector to ?/# )ED-B should
flash on and off& alternately at about B cycle per second# Move the function
generator to Ltimes B"M position =setting the fre5uency to B" ?/># he lamp
monitors should flash on and off at a faster rate& too high to count# ?igher
fre5uency settings Ltimes B""M should cause the lamps to appear to be on
continuously& at about half-normal brilliance
8. 0onnect the FU-0(*- KE-E,A*, output ) to an oscilloscope# 8ou
should observe a s5uare %ave having fairly steep sides and a pea4-to-pea4
8
amplitude of H to 6 volts# 0hange the selection to S5uare& triangle& Sine and
observe the %aves on the oscilloscope#
9
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #1
'(-A,8 A-D DE0(MA) -UM'E,S
OB1ECTIVE:
1 o demonstrate the count se5uence of binary number and the binary-coded
decimal ='0D> representation#
APPARATUS :
1 (0 type OHP2 H-bit ripple counter
BINARY COUNT
1. urn off the po%er s%itch#
2. 0onnect the (0 type OHP2 as sho%n in Fig# 2 Pin BH is connected to P'B#
3. urn the po%er on and observe the four indicator lamps# he H-bit number in
the out is incremented by one for every pulse generated by pushing the pulser
button P'B
4. Disconnect the input of the counter at pin BH from P'B and connect it to the
FU-0(*- KE-E,A*, =lead )>#
5. Set fre5uency selector to Ltime BM =B ?/># his %ill provide an automatic
binary count#
THE BCD COUNT
1. urn off the po%er s%itch#
2. 0onnect the (0 type OHP2 as sho%n in Fig#H Pin BH is connected to P'B#
3. urn the po%er on and observe the four indicator lamps# he H-bit number in
the lambs is incremented by one for every pulse generated by pushing the
pulser button P'B follo%ing the se5uence "& B& !& 2& H& 6& C& O& G& P& B& !& 2& Q#
4. Disconnect the input of the counter at pin BH from P'B and connect it to )#
Set fre5uency selector to Ltime BM =B ?/># his %ill provide an automatic
binary count#
10
6 6
Push
Push J
J
button BH
B!
BH B!
A
button
A
Pulser or
@A @A
P Pulser or P
cloc4 B ' B ' cloc4
@' @'
! (0R OHP2 G ! (0R OHP2 G
,B @0 ,B @0
2
2 ,! @D
BB
,! @D BB
B" B"
Fig#2 'inary 0ounter Fig#H '0D counter
11
EE 200DIGITAL LOGIC DESIGN EXPERIMENT #2
DIGITAL LOGIC GATES
OB1ECTIVE:
1 o study the basic logic gates; A-D& *,& (-JE,& -A-D& and -*,#
2 o study the representation of these functions by truth tables& logic diagrams
and 'oolean algebra#
3 o observe the pulse response of logic gates#
4 o measure the propagation delay of logic gates#
APPARATUS:
1 (0 ype OH"" @uadruple !-input -A-D gates
2 (0 ype OH"! @uadruple !-input -*, gates
3 (0 ype OH"H ?e$ (nverters
4 (0 ype OH"G @uadruple !-input A-D gates
5 (0 ype OH2! @uadruple !-input *, gates
6 (0 ype OHGC @uadruple !-input +*, gate
7 (0 ype OHP2 H-bit ripple counter
8 Digi-Designer )ogic 'oard
9 Dual-trace oscilloscope
THEORY:
AND A multi-input circuit in %hich the output is B only if all inputs are
B#he symbolic representation of the A-D gate is sho%n in Fig# Ba#
OR A multi-input circuit in %hich the output is B %hen any input is B#
he symbolic representation of the *, gate is sho%n in Fig# Bb#
INVERT he output is " %hen the input is B& and the output is B %hen the
input is "# he symbolic representation of an inverter is sho%n in Fig#
Bc#
NAND A-D follo%ed by (-JE,# he symbolic representation of the
-A-D gate is sho%n in Fig Bd#
NOR *, follo%ed by (-JE, as sho%n in Fig Be#
EX-OR he output of the E$clusive A*, gate& is " %hen it.s t%o inputs are
the same and it.s output is B %hen its t%o inputs are different#
12
Truth Table ,epresentation of the output logic levels of a logic circuit for every
possible combination of levels of the inputs# his is best done by
means of a systematic tabulation#
a. Two input AND gate
b. Two input OR gate c. Inverter
. Two input NAND gate e. Two input NOR gate
!. Two input "OR gate
Fig#B Symbols for digital logic gates
Part 1: Logic Fnctions
9. A-D& *,& -A-D& and -*, gates#
1. Use one gate for each (0 OH"" =-A-D>& OH"! =-*,>& OH"G =A-D>& OH2!
=*,>& OHGC =+*,># Each has input pins& B and !& and output pin 2#
2. 0onnect pin B to s%itch SB-B& pin ! to s%itch SB-!& and pin 2 to )ED-B
for every gate as sho%n in Fig ! as an e$ample for the -A-D gate#
#$%$
$
#$%2
2
&

LED%
$
Fi
g#
!

%
o
in
p
ut
-
A
-
D
gate
2# Using
logic
s%itch
es SB-
B and
S-!&
apply
the
logic
levels
" and
B to
levels =see lamp )ED-
B> in table B# ,epeat
the recordings for
each gate#
,emember; )amp *- S
)ogic B& =?igh>
)amp *FF S
)ogic "
=)o%>
13
able B
Pin B Pin ! Pin 2
4. Use an inverter gate from (0 OH"H %hose input pin is pin B and %hose
output pin is pin !#
#$%$
$ 2
LED %$
Fig#2 (nverter gate
5. Using logic s%itches SB-B& apply the logic levels " and B in the
se5uence sho%n in table !# ,ecord the output logic levels in table !
able !#
Pin B Pin !
"
B
Part-2:Response of Logic Gates:
Connect the circuits of figures 4 and 5 and write the corresponding truth tables 3 and
4, respectively.
A
' (
A
D
E
(
D
'
Fig# H Fig# 6
14
able 2#
A ' 0 D E
" "
" B
B "
B B
able H#
A ' 0 D
" "
" B
B "
B B
Part-3:
Propagatio
n Delay in
Logic
Gates:
0onnect all
inverters
inside t%o
OH"H (cs in
cascade#
he output
%ill be the
same as the
input
e$cept that
it %ill be
delayed by
the time it
ta4es the
signal to
propagate
through all
si$
inverters#
Set S! to
B"" 4?/
and apply
cloc4
pulses to
the input of
the first
inverter
=connect
pin B to
:BH>
record the
%ave
forms and
determine
the time
delay
from the
input to
the si$th
inverter#
his is
done %ith
a dual
trace
oscillosco
pe by
applying
the input
cloc4
pulses to
one of the
channels
and the
output of
the si$th
inverter to
the
second
channel
and
measurin
g the
delay
bet%een
the t%o
signals as
sho%n in
Fig C# 'y
using measured delay bet%een t%o signals
calculate the propagation delay for each
inverter gate#
(nput
*utput

i
m
e

d
e
l
a
y
Fig# C
Propagation
delay
15
Part 4: Review Questions:
B# 3rite a truth table for each circuit# Derive 'oolean e$pressions for all outputs#
"$
)
"$
"2
"$
"$
) "2
"2
)
"$
"$
"2
)$
)2
2. A burglar alarm for a car has a normally lo% s%itch on each of four doors# (f
any door is opened the output of that s%itch goes ?(K?# he alarm is set off
%ith an active-)*3 output signal# 3hat type of gate %ill provide this logic<
Support your ans%er %ith an e$planation#
16
EE 200DIGITAL LOGIC CIRCUIT DESIGN EXPERIMENT #3
INTRODUCTION TO LOGICWORKS
=?andouts %ill be given to students>
17
EE 200DIGITAL LOGIC CIRCUIT DESIGN EXPERIMENT #4
BOOLEAN ALGEBRA
OB1ECTIVE:
1 o verify the rules and regulations of 'oolean Algebra
2 o simplify and modify 'oolean logic functions by means of Demorgan.s
theorem#
3 o design and implement a logic circuit#
APPARATUS:
1 P'-6"2
2 OH"" @uadruple ! input -A-D gates#
3 OH"! @uadruple ! input -*, gates
4 OH"G @uadruple ! input A-D gates
5 OH2! @uadruple ! input *, gates
6 OH"H ?e$ inverters
7 OHBB riple 2-input A-D gate
THEORY: =See chapter ! of the te$tboo4>
1. AE" S A
2. AEB S B
3. A #" S "
4. A #B S A
5. AEA S A
6. AEA. S B
7. A#A S A
8. A#A. S "
9. =A.>. S A
10. AEA' S A
11. AEA.' S AE'
12. =AE'>=AE0> S AE'0
13. A.# '. S =AE'>.
14. A.E'. S =A#'>.
Procedure 1:
1. Prove rule B using )ogic3or4s# he procedure
is; (# *pen a ne% design %indo%
35. 0hoose LA)) )(',A,8M in the Parts Palette
61. Put L*,M in the Filter %indo%
(J#Select and double clic4 on *,-!
22. Move to the cursor bac4 into the circuit %indo%# he
cursor on the screen %ill no% be replaced by a moving
image of an *, gate#
18
J(# Position the *, gate near the center of the circuit %indo%
J((#
and clic4 the mouse button#
Press the spacebar to return to point mode#
J(((# Move again to the Parts Palette and type on the Filter
(+#
Ls%itchM or part of the %ord s%itch e#g# Ls%M#
Select 'inary s%itch and connect it to an input of the *,
gate in the design %indo%# =(f you %ant to move the binary
s%itch around& press the shift 4ey %hile moving it>#
24. Move again to the Parts Palette and select ground to be
connected to the other input of the *, gate#
+(# Using the same method get a 'inary Probe and connect it
to the output of the *, gate
+((# 0lic4 on the binary s%itch to change it bet%een " and B
and notice ho% the rule AE" S A is satisfied#
(n the lab connect the circuit as sho%n in the figure using the s%itch
SB-B and )ED-B to verify the rule#
1 $
$
0
&
*o
2
Fig#B Jerifying ,ule B
2. 0onnect the circuit of Fig#! Using )ogic3or4s# 3hich rule does this
circuit illustrate<
$
0
1
&
*o
0
2
Fig#!
(n the lab connect the circuit as sho%n in the figure using the s%itch
SB-B and )ED-B to verify the rule#
3. Design a circuit that illustrates rule B"# Use cloc4 generator of the P'-
6"2 for A and one of the logic s%itches of SB for '# 0opy the circuit
from )ogic3or4s and paste it in your lab report#
4. ,ule C illustrates that AEA. could be replaced %ith a %ire to Jcc# 3hat
does rule G illustrate<
5. ,ule BB states that AEA.' S AE'# Using )ogic3or4s design a circuit
that illustrates each of these e$pressions#
AEA.'
AE'
Prove that these t%o circuits perform e5uivalent logic# =0onnect t%o
circuits and sho% that their outputs are the same>#
19
Procedure 2: Demorgan`s Theorem
Proof of e5uation =B>
Using )ogic3or4s construct the t%o circuits given in Figs#2 and H corresponding to
the functions A.# '.and =AE'>. respectively#
Sho% that for all combinations of A and '& the t%o circuits give identical results#
1
A
$
A+
A
0 &
2
$&
1
$0
$$
2
, 0 $
0
1
$
- $2
A+.(+
&
.A/(0+
1 0
1
2
(
0 (
3
(+
Fig#2 Fig#H
Proof of e5uation =!>
Using )ogic3or4s construct t%o circuits given in Figs# 6 and C& corresponding to the
functions A.E'. and =A#'>. A#'& respectively#
Sho% that& for all combinations of A and '& the t%o circuits give identical results#
(n the lab connect these circuits and verify their operations#
1
A
$
A+
0
2
&
1
A
$
A+/(+
$
0 & .A.(0+
$
1
$
2 & 2
1
1 2 0 (
0 (
3
(+
Fig# 6 Fig# C
II. Design of a Digital Circuit
0onsider the follo%ing problem;
Four chairs A& '& 0& and D are placed in a ro%# Each chair may be occupied =LlM> or
empty =L"M># A 'oolean function F is LlM if and only if there are t%o or more ad:acent
chairs that are empty#
1. Kive the truth table defining the 'oolean function F
2. E$press F as a minterm e$pansion =standard sum of product>
3. E$press F as a ma$term e$pansion =standard product of sum
20
4. Using postulates and theorems of 'oolean algebra& simplify the minterm
e$pansion of F to a form %ith as fe% occurrences of each as possible#
5. (mplement on )ogic3or4s for the pre-lab and then on P'-6"2& the simplified
'oolean function %ith logic gates and chec4 the operation of the circuit#
-otes;
1 (n )ogic3or4s use 'inary S%itches to represent the four chairs and
connect the output of the circuit to a 'inary Probe# 0hec4 that the Probe is
LBM if and only if there are t%o or more ad:acent chairs that are empty#
2 For the hard%are circuit in the lab& use logic s%itches SB-B& SB-!& SB-
2& and SB-H to represent the chairs and connect the output of the circuit
to )ED-B
Result:
Sho% all truth tables& circuits =using )ogic3or4s>& etc# used in completing this
e$periment#
21
EE 200 DIGITAL LOGIC CIRCUIT DESIGN EXPERIMENT #5
SIMPLIFICATION OF BOOLEAN FUNCTIONS USING K-MAP
TECHNIQUES
OB1ECTIVE:
1 To develop the truth table for a combinational logic problem
2 o use Karnaugh map to simplify 'oolean e$pressions#
3 o dra% and simplify sum of products e$pressions#
4 o dra% logic diagrams using -A-D gates#
APPARATUS:
1 P'-6"2
2 OH"" @uadruple ! input -A-D gates#
3 OH"H ?e$ inverters
4 OHB" riple 2-input -A-D gates
5 OH!" Dual H-input -A-D gates
THEORY:
See chapter 2 of the te$t&M simplification of 'oolean functionsM
Procedure:
Part 1: BC invalid code detector
'0D is a H-bit binary code representing the decimal numbers " through P#
he binary numbers B"B" through BBBB are not used in '0D#
1) 0onstruct a truth table containing all possible inputs and desired output#
Assume that the desired output for a valid code is a B& and for an invalid
code is "# 0omplete the truth table as sho%n in able B# A is the most
significant bit& and D is the least significant bit#
2) Dra% the Karnaugh map& and %rite the simplified 'oolean e$pression for
the valid codes as sum of products#
22
A B C D X
" " " "
" " " B
" " B "
" " B B
" B " "
" B " B
" B B "
" B B B
B " " "
B " " B
B " B "
B " B B
B B " "
B B " B
B B B "
B B B B
3) Dra% the circuit for the above simplified 'oolean e$pression#
4) Using the universal property of the -A-D gate connect an
e5uivalent circuit for these codes that uses only -A-D gates#
Part !: Boolean "unctions #1$
1. Simplify the follo%ing t%o 'oolean functions by means of
Karnaugh maps#
F
B
=A& '& 0& D> S 4m ="&B&H&6&G&P&B"&B!&B2>
F
!
=A& '& 0& D>S 4m =2&6&O&G&B"&BB&B2&B6>
2. Dra% the logic diagrams for outputs F
B
and F
!
in terms of the inputs A&
'& 0& and D#
3. (mplement and dra% the t%o functions F
B
and F
!
together by using
minimum number of -A-D gates#
4. 0onnect the circuit and verify it.s operation by preparing a truth table
for F
B
and F
!
similar to able B#
23
Part 3: Boolean "unctions #!$
1. Derive a truth table for the follo%ing 'oolean Functions#
"%&'(B'(BC(&B'
2. Dra% a Karnaugh map#
3. 0ombine all the B.s to obtain the simplified function for "#
4. 0ombine all the ".s to obtain the simplified function for "'#
5. Using logic3or4s& implement both F and F. using -A-D gates and connect
t%o circuits to the same input s%itches but to separate output )ED.s# Prove
that both circuits are complement of each other# (n the lab implement and
verify the operations of the circuit#
6. Dra% both circuits#
Part 4: & )a*ority
A nine member legislative committee re5uires a !D2 vote to spend a billion
dollars# he vote is tabulated and converted to '0D code# (f !D2 of the committee
is in favor& the vote %ill be the '0D representation of C& O& G& or P#
1. Derive a truth table for the problem& able !#
2. Derive a minimum sum of products e$pression from the map# IEnter
the invalid '0D codes on the map as don.t cares =$>T#
3. Using )ogic3or4s& design a circuit that lights an )ED if a ma:ority
has voted in favor of spending the billion dollars# (mplement this
circuit and verify its operation in the lab using hard%are#
24
EE 200 DIGITAL LOGIC CIRCUIT DESIGN EXPERIMENT #6
DES(K- *F 0*DE 0*-JE,E,S
OB1ECTIVE:
1. Design and build gray code to binary converter#
2. Design and build '0D-to-O segment converter#
APPARATUS:
1 Seven segment display#
2 S- OH"" 5uad !-input -A-D gates =B>
3 S- OHB" triple 2-input -A-D gates =H>
4 S- OH!" dual H-input -A-D gates =H>
5 S- OH"H ?E+ inverter =B>
6 S- OHHC '0D-to-seven segment decoder#
THEORY:
he conversion from one code to another is common in digital systems#
Sometimes the output of a system is used as the input to the other system# A
conversion circuit is necessary bet%een ! systems if each system uses different
codes for the same information#
(n this e$periment you %ill design and construct 2-combinational circuit
converters;
See section H-6 in your boo4 for further information#
Procedure:
1. !"a# code to $ina"# con%e"te"&
Kray code is one of the codes used in digital systems# (t has the advantage
over binary numbers that only one bit in the code %ord changes %hen going
from one number to the ne$t# =See able B>#
Design a combinational circuit %ith H inputs and H outputs that converts a four-
bit gray code number into an e5uivalent four-bit 'inary number# Use Karnaugh
map techni5ue for simplification# Use )ogic3or4s for pre-lab demonstrations#
Select the library LOH""dev#clfM in the Parts Palette and then select the +*, chip
OH-GC# his %ould give you a set of H +*,.s as sho%n in Fig# B& :ust li4e the
hard%are chip OH-GC# 8ou could use as many as needed from these +*, gates in
your design# Ket bac4 to A)) )(',A,(ES and select s%itches for the inputs and
'inary Probes as indicators of the outputs# Jerify your design in the pre-)ab#
During the )ab construct the circuit and verify its operations#
25
Decimal
able B
Binary Gray
" """" """"
B """B """B
!"
$
&
! ""BB ""B"
2
2 ""B" ""BB
H "BB" "B""
1
2
6 "BBB "B"B
3
C "B"B "BB"
-
O "B"" "BBB
, G BB"" B"""
$0
P BB"B B""B
$2
B" BBBB B"B"
$$
BB BBB" B"BB $&
B! B"B" BB""
Figure# B +*, chipOH-GC
B2 B"BB BB"B
BH B""B BBB"
B6 B""" BBBB
2. $C'-to-e%en (eg)ent con%e"te"&
A light emitting Diode =)ED> is a P- :unction diode# 3hen the diode is
for%ard biased& a current flo%s through the :unction and the light is emitted#
See Fig#!#
Figure#!
A seven segment )ED display contains O )EDs# Each )ED is called a
segment and they are identified as =a& b& c& d& e& f& g> segments# Figure 2#
Figure 2# Digits represented by the O segments
26
he display has O inputs each connected to an )ED segment# All anodes of
)EDs are tied together and :oined to 6 volts =this type is called common anode
type># A limiting resistance net%or4 must be used at the inputs to protect the
O-segment from overloading#
'0D inputs are converted into O segment inputs =a& b& c& d& e& f& g> by using a
decoder& as sho%n in Fig#H#
Figure# H
A decoder is a combinational circuit that converts binary information from n
input lines to a ma$imum of !
n
output lines# he input to the decoder is a
'0D code and the outputs of the systems are the seven segments a& b& c& d& e&
f& and g# For further information and pin connections& consult the specification
sheet for decoder and O-segment units#
First design a combinational circuit %hich %ould simulate the decoder
function for only the segment LaM& of the display# his can be done in the
follo%ing steps;
1) 3rite do%n the truth table %ith H inputs and O outputs =able !>
2) For only the output LaM& obtain a minimum logic function# ,eali/e
this function using -A-D gates and inverters only# For e$ample if
decimal P is to be displayed a& b& c& d& f& g must be " and the others
must be B =For common anode type display units>& if decimal 6 is to
be displayed then a& f& g& c& d must be " and the others must be B#
3) 0onnect the output LaM of your circuit to appropriate input of O-
segment display unit# 'y applying '0D codes verify the displayed
decimal digits for that segment for LaM of the display#
4) ,eplace your circuit by a decoder (0 OHHO for all of the seven
segments# *bserve the display and record the segments that %ill
light up for invalid inputs se5uence#
5) 0omment on the design if you don.t %ant to see any digit for
invalid input se5uence#
27
able !
Dec. BCD Outputs
A B C D a b c d e f g
" " " " "
B " " " B
! " " " "
2 " " B B
H " B " "
6 " B " B
C " B B "
O " B B B
G B " " "
P B " " B
/3*
$2
15 O67
#$
1 $
ot
'A
(I8R(O $1
9
g
3
$&
$1
R(I $3
& :
LT - $0
E
input
2
D
$0 ,
2
D
$$ 5 !ro7 ' '
switc6es
$ ( ( $2 2
5 A, A $& $$ a
,
('D%to%#even #eg7ent Decoer an 5%seg7ent isplay
Note; In an actual 5%seg7ent isplay t6e ot is on t6e le!t
28
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #7
ADDERS, SUBTRACTORS AND MAGNITUDE COMPARATORS
Objectives:
1 o construct and test various adders and subtractor circuits#
2 o construct and test a magnitude comparator circuit#
Apparatus:
1 (0 type OHGC 5uad !-input +*, gates
2 (0 type OH"G 5uad !-input A-D gates
3 (0 type OH"H ?E+ inverter
4 (0 type OHG2 H-bit binary adder
5 (0 type OHG6 H-bit magnitude comparator#
Theory:
See Sections B-6&H-2&6-!&6-H of your te$tboo4#
1) &ddition:
(0 type OHG2 is a H-bit binary adder %ith fast carry# he pin assignment is sho%n in
Fig B# he t%o H-bit input binary numbers are A
B
through A
H
and '
B
through '
H
# he
H-bit sum is obtained from S
B
through S
H
# 0
i
is the input carry and 0
o
the out carry#
his (0 can be used as an adder-subtractor as a magnitude comparator#
6
B
AH
Jcc
0o
BH
2
A2
B6
SH
G
A!
!
B"
S2 AB
OHG2
C
BC
'H
S!
H '2
SB
P
O '!
BB 'B
B2
0i K-D
B!
Fig#B (0 type OHG2 H-bit adder
29
2) +ubtraction:
he subtraction of t%o binary numbers can be done by ta4ing the !.s complement
of the subtrahend and adding it to the minued# he !.s complement can be
obtained by ta4ing the B.s complement and adding B#
o perform A - '& %e complement the four bits of '& add them to the four bits of
A& and add B to the input carry# his is done as sho%n in Fig !#
6
B AH
Jcc
BH
2 A2
0o
(nput A
B6
G A!
SH
!
B" AB
OHG2
S2
BC 'H C
H '2
S!
P
(nput ' O '!
SB
BB 'B
K-D 0i
B2
B!
M
M S " for add and M S B for subtract
Fig# ! H-bit adderDsubtractor
Four +*, gates complement the bits of ' %hen the mode select M S B = because
$ BS$.> and leave the bits of ' unchanged %hen M S " =because $ "S$>
thus& %hen the mode select M is e5ual to B& the input carry 0
i
is e5ual to B and the
sum output is A plus the !.s complement of '# 3hen M is e5ual to "& the input
carry is e5ual to " and the sum generates A E '#
c> )agnitude co,parison
he comparison of t%o numbers is an operation that determines %hether one
number is greater than& e5ual to& or less than the other number#
30
he (0 OHG6 is a H bit magnitude comparator# (t compares t%o H-'it binary
numbers =labeled as AU'> generates an output of B at one of three outputs
labeled A V '& A W '& A S '# hree inputs are available for cascading
comparators# see Fig#2#
B
AH
Jcc
A V '
2
A2
G
A!
B" A S '
AB
OHG6
BC
'H
H
'2
A W '
O
'!
BB
'B
K-D
Fig# 2 H-bit magnitude comparator
Procedure:
1) Design using )ogic3or4s a half adder circuit using only +*, gates and -A-D
gates# hen during the )ab construct the circuit and verify its operation#
2) Design using )ogic3or4s a full adder circuit using only +*, gates and -A-D
gates# hen during the )ab construct the circuit and verify its operation#
3) Use (0 OHG2 to add the t%o H-bit numbers A and ' sho%n in ableB# (n
)ogic3or4s& select the chip OH-G2 and use 'inary s%itches for the bits of the
t%o numbers and the input carry and use 'inary Probe for the sum and carry
out#
able B#
A3 A2 A1 A0 B3 B2 B1 B0 Sum Carry
out
B " " B " " B "
" B B " B " B B
B B " " B " B "
(nput carry 0i is ta4en as logic "# Sho% that if the input carry is B& it adds B to
the output sum#
(n the )ab use s%itches SB-B to SB-G for the t%o numbers and use the SPD
S! for the input carry 0i# For sum and carry out& use )ED-B to )ED-6#
31
4) 0onnect the adder-subtractor circuit as sho%n in Fig !# Perform the follo%ing
operations and record the values of the output sum and the output carry 0
o
#
able !#
Decimal Output sum Carry
A B Out C
o
P E 6
P - 6
P E B2
P - P
B" E C
C - B"
1 Sho% that 0
o
SB %hen sum e$ceeds B6#
2 0omment on sum and 0
o
for the subtraction operations %hen A V '
and A W '#
5) Use (0OHG6 to compare the follo%ing t%o H bit numbers A and '# ,ecord the
outputs in table 2# -ote that in )ogic3or4s you need to connect =A S '> input
to logic B =as an indication that previous stages are e5ual in multi-digit
numbers> for correct results %hile this is not necessary for the hard%are#
able 2#
A B Outputs
B""B "BB"
BB"" BBB"
""BB "B"B
"B"B "B"B
6) A magnitude comparator can be constructed by using a subtractor as in Fig !# and
an additional combinational circuit# his is done %ith a combinational circuit %hich
has 6 inputs S
B
& S
!
& S
2
& S
H
& and 0
o
& and three outputs +& 8& X see Fig#H
+ S B if A S ' 3here S S """"
8 S B if A W ' 3here 0
o
S "
X S B if A V ' 3here 0
o
S B S Y """"
32
Design and construct this logic circuit %ith minimum number of gates# 0h
ec4 the comparator action using Part =e># (n the )ab verify your )ogic3or4s
simulation#
6
B AH
Jcc
BH
2 A2
0o
(nput A
B6 Design this
G A!
SH 0ombinational
!
B" AB 0ircuit
OHG2
S2
BC 'H
C
S!
(nput ' H '2 P
O '!
SB
BB 'B
K-D
Mode Select M
0i
B2
Jcc B!
=M S B for subtract>
Fig#H A magnitude comparator using a subtractor
$
y
/
3
3
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #8
DESIGN WITH MULTIPLEXERS
Objectives:
o design a combinational circuit and implement it %ith multiple$ers# o use a
demultiple$er to implement a multiple output combinational circuit from the
same input variables#
Apparatus ;
1 (0 type OH"H ?E+ inverter
2 (0 type OH"G 5uad !-input A-D gate
3 (0 type OHB6B G$B multiple$er =B>
4 (0 type OHB62 dual H$B multiple$er =!>
5 (0 type OHHC '0D-to-Seven-Segment decoder =B>
6 ,esistance net%or4 =B>
7 Seven-Segment Display =B>
Theory: see section 6#C of your te$t#
IC Description:
OHB6B is a G line-to-B line multiple$er# (t has the schematic representation sho%n
in Fig B# Selection lines S
!
& S
B
and S
"
select the particular input to be multiple$ed
and applied to the output#
Strobe S acts as an enable signal# (f strobe SB& the chip OHB6B is disabled and output
y S "# (f strobe S " then the chip OHB6B is enabled and functions as a multiple$er#
able B sho%s the multiple$ function of OHB6B in terms of select lines#
able B#
O
BC G
Strobe Select )ines *utput Strobe S Jcc K-D
S S
!
S
B
S
"
8 H
D"
6 B + + + " 2
8
8
DB
" " " " D"
!
D!
" " " B DB
OHB6B B
D2
C
8.
" " B " D!
(nput data
3
B6
DH " " B B D2
BH
D6 " B " " DH
B2
" B " B D6 DC
B!
" B B " DC DO
S! SBS"
" B B B DO
P B" BB
Fig#B (0 type OHB6B Multiple$er G<B
34
OHB62 is a dual H line-to-B line multiple$er# (t has the schematic representation sho%n
in Fig !# Selection lines SB and S" select the particular input to be multiple$ed and
applied to the output (8IB S B& !T#
Each of the strobe signals - . I( S B& !T acts as an enable signal for the corresponding
multiple$er#
able !# sho%s the multiple$ function of OHB62 in terms of select lines# -ote that
each of the on-chip multiple$ers act independently from the other& %hile sharing the
same select lines S
B
and S
"
#
able !
Multiple$er B
Strobe Select lines *utput
BK SB S" B8
B + + "
" " " BD
"
" " B BD
B
" B " BD
!
" B B BD
2
Multiple$er !
Strobe Select lines *utput
!K SB S" !8
B + + "
" " " !D
"
" " B !D
B
" B " !D
!
" B B !D
2
BC G
B
J cc K-D
B
. Strobe
C BD" MU+B
6
BDB
(nput data
H
Fig#! 0hip OHB62
(0
OHHC
is a
'0D
to
seven
segme
nt
decod
er
driver#
(t is
used
to
conve
rt the combinational circuit
outputs in '0D forms into
O segment digits for the O
segment )ED display units#
See e$periment R6#
35
Procedure:
Part -: Parity .enerator:
1) Design a parity generator by using a OHB6B multiple$er# Parity is an e$tra bit
attached to a code to chec4 that the code has been received correctly#
*dd parity bit means that the number of B.s in the code including the parity bit is an
odd number# Fill the output column of the truth table in able ! for a 6-bit code in
%hich four of the bits =A&'&0&D> represents the information to be sent and fifth bit
=$>& represents the parity bit# he re5uired parity is an odd parity#
he inputs '&0 and D correspond to the select inputs of OHB6B# 0omplete the truth
table in able 2 by filling in the last column %ith "&B&A or A.#
b> Simulate the circuit using )ogic3or4s& use OH-B6B multiple$er and 'inary
(nputs *utputs 0onnect data to
A ' 0 D +
" " " "
" " " B
" " B "
" " B B
" B " "
" B " B
" B B "
" B B B
B " " "
B " " B
B " B "
B " B B
B B " "
B B " B
B B B "
B B B B
s%itches for inputs and 'inary Probes for outputs# he OHB6B has one output for
8 and another inverted output 3# Use A and A. for providing values for inputs
"-O# he internal values LA& '& 0M are used for selection inputs '&0& and D#
Simulate the circuit and test each input combination filling in the table sho%n
belo%# (n the )ab connect the circuit and verify the operations# 0onnect an )ED
to the multiple$er output so that it represents the parity bit %hich lights any time
%hen the four bits input have even parity#
36
=art 2; *ote 'ounter;
A committee is composed of a chairman =0>& a senior member =S>& and a member
=M># he rules of the committee state that;
1 he vote of the member =M> %ill be counted as ! votes
2 he vote of the senior member %ill be counted as 2 votes#
3 he vote of the chairman %ill be counted as 6 votes#
Each of these persons has a s%itch to close =LlM> %hen voting yes and to open =L"M>
%hen voting no#
(t is necessary to design a circuit that displays the total number of votes for each
issue# Use a seven segment display and a decoder to display the re5uired number#
(f all members vote no for an issue the display should be blan4# =,ecall from
E$periment R6& that a binary input B6 into the OHHC blan4s all seven segments>#
(f all members vote yes for an issue& the display should be "# *ther%ise the display
sho%s a decimal number e5ual to the number of ZyesZ votes# Use t%o OHB62 units&
%hich include four multiple$ers to design the combinational circuit that converts the
inputs from the members. s%itch to the '0D digit for the OHHC#
(n )ogic3or4s use E6J for )ogic B and ground for )ogic " and use s%itches for 0&
S& and M# Use t%o chips OHB62 and one decoder OHHC verify your design and get a
copy of your circuit %ith the pin numbers to )ab so that you could connect the
hard%are in e$actly the same %ay#
37
EE 200DIGITAL LOGIC DESIGN EXPERIMENT #9
DESIGN WITH ROM`S
=?andout %ill be provided>
38
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #10
FLIP-FLOPS
Objectives:
1. o become familiar %ith flip-flops#
2. o implement and observe the operation of different flip-flops#
Apparatus ;
1 (0 type OH"" 5uad !-input -A-D gate
2 (0 type OHB" triple 2- input -A-D gate
3 (0 type OHOC dual NK master-slave flip-flops#
4 (0 type OHOH dual D positive-edge-trigged flip-flops#
5 Dual trace oscilloscope#
Theory: See sections C-! and C-2 of your te$t#
Procedure:
1. (n the pre-lab using )ogic3or4s construct the circuit sho%n in Fig#B
/3*
$
0
/3*
3here %e could use generic -A-D gates or OH-"" and 'inary Probes to
simulate )EDs# Finally& %e use SPD for the bouncing s%itch# Using the
simulated circuit fill in the truth table#
39
S , @ @.
B "
B B
" B
B B
" "
(n the )ab& 'uild the ,S latch sho%n in fig#!# Use SPD s%itch S! as a
bouncing s%itch# @ and @. *utputs are connected to )ED.S of the P'-6"2#
Jerify the truth table e$perimentally#
E6
J
B
K
>
22">
E
6

J
BK>
22">
Fig# !
2. Modify the basic ,-S into a D latch by adding the steering gates and the
inverter sho%n in Fig 2#
0onnect the D input to the pulse generator of the digi designer and set it at B
?/#
0onnect the enable input to a high through B4 resistor# *bserve the output1
obtain the truth table e$perimentally then change the enable to a lo%#
(s the enable an active high or an active< )eave the enable lo% and
place a momentary short to ground first on one output and then on the
other# 3hat happens<
D
@
BK>
22">
Pulse E6J
Kenerator
E6
J
@. 22">
3. he OHOC is a dual NK master-slave flip-flopsFig# 2%ith preset and clear inputs#
he function table given in table B defines the operation of the flip-flop# he
Eve transition of the 0)*0K =0P> pulse changes the master flip-flop& and the =-
ve>
40
transition changes the slave flip-flop as %ell as the output of the circuit# (n
)ogic3or4s the chip OHOC is not available& ho%ever& the generic NK flip-flop
behave in e$actly the same %ay as the OHOC# he LSM represents the Preset& the
L,M represents the 0lear& and 0 represents the cloc4 pulse =0P># Jerify the table
by connecting 'inary s%itches to ,& S& N& K& and 0# -otice that only the
negative edge of the cloc4 affects the outputs =@& and @.>#
able B
(nput *utput
Preset 0lear 0loc4 N K @ @.
" B + + + B "
B " + + + " B
" " + + + B B
B B " " -o change
B B " B " B
B B B " B "
B B B B oggle
N
P
@
, 22">
0
E6J
P
K
0),
@
. 22">
Fig# H
(n the )ab& 0onstruct the circuit of Fig H# )oo4 at the data sheet for the OHOC and
determine the inactive logic re5uired at the P,E and 0), inputs#
0onnect the OHOC for the SE mode by connecting N S B& K S "# 3ith 0)*0K
=0P> S "1 test the effect of P,E& 0), by putting a " on each& one at a time#
Put 0), S "& then pulse the cloc4 =0P> by putting a ?(K? then a )*3& on the cloc4#
Does the 0), input override N input<
Jerify the operation of the NK flip flop by e$perimentally obtaining the characteristic
table# ! O
H
B6
P
BB
N
P,
@ N
P,
@
Jcc S pin 6
B C
0P 0P
K-D S pin B2
BC K
@.
BH B! K
@.
B"
0), 0),
2 G
41
EE 200 DIGITAL LOGIC DESIGN EXPERIMENT #11
CLOCKED SEQUENTIAL CIRCUITS AND COUNTERS
OB1ECTIVE:
1 o design& build and test synchronous se5uential circuits#
2 o design& build& and test synchronous counters
3 o design& build and test asynchronous counters
APPARATUS:
1 (0 type OHOC dual NK master-slave flip-flops
2 (0 type OH"" 5uad !-input -A-D gates
THEORY:
See sections C-C& C-O& C-G& O#! and O#6 of your o%n te$t#
PROCEDURE:
1. +/0C123034+ +564507-&8 C-2C4-7+&
1) Design& construct and test a se5uential circuit %hose state is sho%n in Fig#B#
Use NK flip-flops in the design#
""
"D"
BDB
BD"
"D" "B B" "D"
BDB
Fig# B
he circuit has t%o flip-flops A& '& one input $ and one output y# he circuit is to be
designed by treating the unused states as don.t care conditions# he final circuit must
be analysed to ensure that it is self-correcting# (f not suggest a solution#
b> 0omplete the e$citation table sho%n in able B#
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able B#
Present state (nput -e$t state *utput Flip-flop input functions
A ' + A ' 8 NA KA N' K'
" " " " B " " + B +
" " B B " B B + " +
" B "
" B B
B " "
B " B
B B "
B B B
3) Using Karnaugh maps obtain minimal e$pressions for the flip-flop input
functions NA& Q& K0
4) Simulate the circuit using )ogic3or4s# )ogic3or4s does not have the NK
master-slave flip-flop (0 OHOC# Use instead the generic NK flip-flop as you
did in e$periment P# (n the )ab& build the circuit and chec4 the output to
verify the state table values#
2. +ynchronous Counters
Synchronous counters have all cloc4 lines tied to a common cloc4 causing all
flip-flops to change at the same time# he count se5uence of a counter can be
analysed by placing the counter into every possible number in the se5uence and
determining the ne$t number in the se5uence state diagram is developed as the
analysis proceeds# =A state diagram is an illustration of the transitions that occur
after each cloc4 pulse>#
1) (n the pre-lab using )ogic3or4s and then in the lab using hard%are chips&
design a !-bit gray code counter using NK flip-flops# he re5uired se5uence is
the binary e5uivalent of ="-B-2-!-"># A state diagram for this counter is given
in Fig# !#
""
"B B"
BB
Fig# !
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2) 0omplete the e$citation table =able !> for the counter and obtain
logic e$pression for the NK flip-flop input functions#
able !#
Present state -e$t state Flip-flop input functions
A ' A ' NA KA N' K'
" "
" B
B B
B "
Flip-flop input functions are;
NAS KAS
N'S K'S
3) (n the lab& build the circuit and test it by pulsing it from the P'-6"2# 0hec4
that the output is the designed se5uence
3. & +ynchronous Counters
Asynchronous counters are a series of flip-flops each cloc4ed by the previous
state& one after the other# Since all the stages of the counter are not cloc4ed
together& a ripple effect propagates as various flip-flops are cloc4ed# For this
reason they are called ripple counters# he modulus of a counter is the number
of different output states the counter may ta4e =i#e# Mod H means the counter
has four output states>#
1) (n the pre-lab construct a H-bit asynchronous counter sho%n in Fig#2# =(t is
also called binary ripple counter># Use four generic NK flip-flops# 0onnect
four 'inary Probes to @ outputs# 0onnect all , and S inputs to )ogic B and
connect a s%itch to the 0P input#
B B B B
N N N N
cp
@ @ @ @
Fig# 2 H-bit ripple counter
2) (n the )ab use t%o OHOC (0s to implement the design# 0onnect @ outputs of
flip-flops to indicator lamps of the P'-6"2# 0onnect all clear =0),> and
preset =P,E> inputs to logic B# 0onnect the 0P input to the pulse output of the
P'-6"2 and chec4 the counter for proper operation#
44
3) 3rite do%n the count se5uence in able 2# (dentify this count se5uence =up or
do%n># 0omment on %hat happens after the application of B6 pulses to 0P
input#
able 2# 0ount se5uence for the H-bit ripple counter#
A ' 0 D
45
Appendix
(LABORATORY REGULATIONS AND SAFETY RULES)
he follo%ing ,egulations and Safety ,ules must be observed in all
concerned laboratory location#
1. It is the duty of all concerned who use any electrical laboratory to take all
reasonable steps to safeguard the HEALTH and SAFETY of themselves
and all other users and visitors.
2. Be sure that all equipment is properly working before using them for
laboratory exercises. Any defective equipment must be reported
immediately to the Lab. Instructors or Lab. Technical Staff.
3. Students are allowed to use only the equipment provided in the
experiment manual or equipment used for senior project laboratory.
4. Power supply terminals connected to any circuit are only energized with
the presence of the Instructor or Lab. Staff.
5. Students should keep a safe distance from the circuit breakers, electric
circuits or any moving parts during the experiment.
6. Avoid any part of your body to be connected to the energized circuit and
ground.
7. Switch off the equipment and disconnect the power supplies from the
circuit before leaving the laboratory.
8. Observe cleanliness and proper laboratory house keeping of the
equipment and other related accessories.
9. Wear proper clothes and safety gloves or goggles required in working
areas that involves fabrications of printed circuit boards, chemicals
process control system, antenna communication equipment and laser
facility laboratories.
10. Double check your circuit connections specifically in handling electrical
power machines, AC motors and generators before switching ~ON the
power supply.
11. Make sure that the last connection to be made in your circuit is the power
supply and first thing to be disconnected is also the power supply.
12. Equipment should not be removed, transferred to any location without
permission from the laboratory staff.
13. Software installation in any computer laboratory is not allowed without
the permission from the Laboratory Staff.
14. Computer games are strictly prohibited in the computer laboratory.
15. Students are not allowed to use any equipment without proper
orientation and actual hands on equipment operation.
16. Smoking and drinking in the laboratory are not permitted.
All these rules and regulations are necessary precaution in Electrical
Laboratory to safeguard the students, laboratory staff, the equipment and other
laboratory users.
46