BULETINUL INSTITUTULUI POLITEHNIC DIN IAI

Publicat de
Universitatea Tehnic Gheorghe Asachi din Iai
Tomul LV (LIX), Fasc. 1, 2009
Secia
AUTOMATIC i CALCULATOARE






A FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP
FOR DC MOTOR CONTROL

BY

BOGDAN ALECSA and ALEXANDRU ONEA


Abstract. The paper proposes a way of implementing a phase locked loop (PLL)
motor speed controller. The main emphasis is on the FPGA implementation of the digital
PLL. The closed loop sensing element is an optical tachometer, which outputs an impulse
train with a frequency proportional to the motor rotational speed. This impulse train will
be synchronized by the PLL to a reference impulse train of a given precise frequency,
generated inside the FPGA from a quartz crystal oscillator. The phase difference between
the two impulse trains is measured by a phase detector. The phase detector converts the
phase difference to a numerical value that can be processed digitally by the loop filter.
The loop filter acts as a regulator.
The novelty of the design is the phase detector, which allows digital processing of
the signals. The design of the PLL can be done only with digital logic. The whole digital
controller can be easily implemented in an FPGA.
Simulation results show the behaviour of the designed digital circuits.
Key words: PLL, ADPLL, FPGA, motor control.
2000 Mathematics Subject Classification: 93C83.



1. Introduction

Control techniques based on the phase-locked loop (PLL) have been
proposed since the 70s and they proved to provide highly accurate speed
control. One usual application for PLL control is the speed control of DC
motors [1], [2]. Digital PLLs are also not a new field: when digital signals have
to be synchronized, a digital phase detector can easily be used to measure the
phase error. Usually, in a PLL system, the output of a digital phase detector is
filtered by an analog filter, to provide an analog control signal to a voltage
controlled oscillator (VCO). These are the so-called classical digital PLLs
(CDPLL) [4].
10 Bogdan Alecsa and Alexandru Onea

A new class of digital PLLs has emerged with the development of the
digital circuits: the all-digital PLL (ADPLL) [4]. This type of loop consists of a
digital phase detector, a digital filter and a numerically controlled oscillator. In
this case, the system consists exclusively of logical devices. Furthermore, the
signals within the system are also digital.
The ADPLL has the advantage of using only digital circuits, getting
away from the problems that usually accompany analog circuits: parts spread,
parasitic capacitors, temperature drift and aging.
Another advantage of the ADPLL is the fact that it can be implemented
by using reconfigurable devices, making the testing and prototyping very easy.
In this paper, a method for designing an ADPLL for speed control will
be presented. The loop will be implemented in a FPGA reconfigurable device,
and the experimental results are presented in section 4. The details of the
original circuitry acquiring the phase error are emphasized.
The paper is organized as follows. Section 2 describes in general a PLL
based motor speed controller. The designed ADPLL is presented in Section 3,
giving details about the parts of the system, the implementation and the
simulations, where appropriate. The experimental results are commented in
Section 4. Finally, in Section 5, several conclusions are formulated.

2. PLL Control System

2.1. Block Diagram

As an usual example of a PLL control application, the motor speed
control system will be considered.
In the case of motor speed control using PLL, the motor must be
included in the loop: the driver, the motor and the optical encoder form the
digitally controlled oscillator (DCO) in the PLL. The difference from a normal
DCO or VCO is that the motor-encoder combination is a second order system,
and this must be taken into consideration when designing the loop.
The block diagram of the PLL motor speed control system is shown in
Fig. 1. It consists of the phase-frequency detector (PFD), the loop filter and the
motor with the rotary encoder (optical tachometer).

Fig. 1 Block diagram of the PLL motor control system.
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 11

2.2. Motor Modelling

The transfer function of the motor-encoder block is determined
according to [5] as a second order system:

(1)
) 1 (
) (
m
m
sT s
K
s H
+
= ,

where
m
K is the motor gain and
m
T is the motor time constant. It includes the
integral property of the encoder.
In this design the reference signal is generated to be compared with the
encoder output signal. The programmable divider at the encoder output allows
to indirectly change the reference signal. It also allows adjustment of the overall
loop gain.

2.3. Loop Filter

The motor speed control system is a third order system, if a first order
loop filter is considered, which is usually used. Because the closed loop system
has three poles, a filter with a zero must be specified for the loop filter.
Otherwise, the phase of the closed-loop transfer function would exceed 180 at
higher frequencies and the system would become unstable.
A PI filter was chosen for the loop filter. The transfer function of the
filter is:

(2)
s
s
s
K
K s F
I
P
1
2
1
) (

+
= + = ,

where
1
2

=
P
K ,
1
1
I
K

= .

3. ADPLL Controller Design

In this section, the implementation details of an all digital PLL control
system are outlined. Each part of the PLL model is depicted and explained.

3.1. Phase-Frequency Detector

The phase-frequency detector (PFD) designed for this application is
based on sequential logic. It resembles the PFD presented in [5], but it has a
numeric output. The PFD detects the phase error and converts it into a numeric
value.
The block diagram of the PFD is presented in Fig. 2.
12 Bogdan Alecsa and Alexandru Onea

The reference signal to which the motor must be synchronized is
generated inside the FPGA from a 50 MHz quartz oscillator.



Fig. 2 PFD block diagram.

The 50 MHz signal is divided to a suitable frequency by a
programmable divider, which allows the easy change of the reference signal.
The output of the programmable divider is fed to a divider by 65536,
implemented by a 16 bit counter. This 2 stage divided frequency signal is the
reference signal. The second divider is used also to measure the phase
difference: the encoder output rising edge will save the contents of the counter
into a register. In this way, the higher the phase difference between the
reference and the encoder signal, the higher will be the value saved from the
counter.
The 16 bit number can be seen as a signed number, this way providing
information about the direction of the phase error: when the rising edge of the
encoder output comes in the first half-period of the reference signal, the number
saved from the counter will be smaller than 8000h, which means the MSB will
be 0. This corresponds to a lag between the controlled signal and the
reference signal. The magnitude of the lag is given by the rest of the bits.
When the rising edge of the encoder output comes in the second half-
period of the reference signal, the counter contents will be higher than 7FFFh,
which means the MSB will be 1. This corresponds to a lead condition. The
magnitude of the phase error is given by the difference to FFFFh, which means
the contents of the register is exactly the twos complement representation of
the numeric negative value.
In order for the PFD to detect also the frequency error, it must give a
corresponding output when the reference signal period passes without a rising
edge of the encoder output being observed. For this, a flip-flop memorizing the
fact that a rising edge of the encoder signal has appeared in the current reference
signal period is used. In case the flip-flop is 0, a constant value corresponding to
a maximum lag condition is routed to the PFD output. The motivation for this
will be explained later on.
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 13

The actual implementation of the PFD was done using the Xilinx ISE
Webpack, at a schematic level. Mentor Graphics ModelSim was used for
simulation of an 8 bit implementation, and the results are presented in Figs. 3 to
5.
In Fig. 3, the numeric output of the PFD is constant and small positive.
This corresponds to the same frequency of the signals and a small phase lag.



Fig. 3 ModelSim simulation of 8 bit PFD: small phase error, same frequency.

In Fig. 4, a big change in the encoder ENC signal is simulated. This is
observed by the PFD, and the output changes accordingly. The numeric value is
still positive, but it has a high value.



Fig. 4 ModelSim simulation of 8 bit PFD: big phase error, same frequency.

In Fig. 5, the phase error is increased even more. The output of the PFD
will be a negative number, corresponding to a phase lead condition, as the
positive edge of the ENC signal comes after more than half-period from the
positive edge of the reference signal.
14 Bogdan Alecsa and Alexandru Onea


Fig. 5 ModelSim simulation of 8 bit PFD: phase lead error, same frequency.

The loop should control the motor position, meaning the phase
synchronization between the encoder output and the reference signal, but it
should also adapt the motor angular speed if it does not match the frequency of
the reference signal. To do this, the PFD must also signal the frequency error to
the following circuitry. This is accomplished by the presented design in the
following way: if the frequency of the encoder output is higher than the
frequency of the reference signal, there will be more pulses coming from the
encoder in a sample period, which is the reference signal period. The PFD will
output the phase difference between the rising edge of the last pulse and the end
of the sample period. This difference will be smaller than half a period, so the
output will be a negative number, which means a lead signal. The loop will
work to minimize the lead difference by decreasing the voltage over the
motor, and so decreasing the frequency, because the leading phase condition
will be maintained as long as there is a frequency error.
If the frequency of the encoder output is lower than the frequency of the
reference signal, there will be sample periods where no pulse from the encoder
output will be observed. In this case, the PFD will output a numeric value
corresponding to a maximum phase lag. Trying to minimize the phase lag,
the loop will increase the voltage over the motor, thus increasing the frequency,
as the maximum phase lag condition will continue to appear at the PFD
output as long as there is a frequency error.
The simulation of this behavior of the PFD is presented in Figs. 6 and 7.


Fig. 6 ModelSim simulation of 8 bit PFD: lag frequency error.
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 15



Fig. 7 ModelSim simulation of 8 bit PFD: lead frequency error.

The PFD output is linear for the input interval [-; +), as presented in
[5], and nonlinear in the frequency error case. Anyway, regardless of the loop
filter type, the loop will acquire frequency lock because of the described PFD
behavior.
The transfer function of the PFD and ADC in the interval [-; +) is:

(3)
65536
2
d
K

= .

3.2. Loop Filter Design

The loop filter is digital because the phase error is converted to a
numeric representation. Also, as will be shown in the next section, the motor
voltage is controlled numerically by a PWM signal.
The filter constants are chosen for maximum stability of the loop and
best dynamic performance, by the Bode diagram. The method is presented in
[5]. The loop stability is analyzed in the near-lock state, so the linear model for
the PFD presented above is considered.
The discrete correspondent of Eq. (2), including the zero-order holder of
the ADC, is:

(4)
(

=
)
`

=
2 2
) 1 ( 1
1 1
) (
z
Tz K
z
z K
z
z
s
K
s
K
Z
z
z
z F
I P I P
,

which leads to:

(5)
1
) (

+ =
z
T K
K z F
I
P
,

where T is the sampling period.
When expressing Eq. (5) in
1
z , the next form is obtained:
16 Bogdan Alecsa and Alexandru Onea

(6)
1
1
1
) (

+ =
z
Tz K
K z F
I
P
.

If the filter output is denoted as u[k] and the input as [k], then a
relation to compute u[k] can be derived from equation (5):

(7)

+
=

1
1
1
) (
) (
) (
z
z K T K K
z
z U
P I P


(8)

+ =

) ( ) ( ) ( ) ( ) (
1 1
z E z K T K z E K z U z z U
P I P


(9)

] 1 [ ) ( ] [ ] 1 [ ] [ + + = k K T K k K k u k u
P I P
.

The equation Eq. (9) can be obtained directly from the time domain,
approximating the integral by using the left rectangle method.
The block diagram of the digital filter is presented in Fig. 8. The filter is
implemented using the Spartan-3E FPGAs integrated 18 bit multipliers and
adders implemented by combinatorial logic.


Fig. 8 Digital filter block diagram.

To find the proportional and integral gain constants, the stability of the
system was analyzed: the zero in the transfer function must be placed such that
the phase stays below 180 at the frequency where the magnitude curve goes
through the 0-dB line. A phase margin of at least 30 will be considered, so the
break frequency of the zero term ) 1 (
2
s + must be well bellow the break
frequency
m
T / 1 .

(10)
m
aT =
2
, ( 1 > a ).
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 17

A factor of 10 = a will be used. So, having s T
m
1 = for the motor,
2
was set at s 10
2
= .
The next step is to find
1
, which is only a gain factor. For the
magnitude to be 0dB at the break frequency
m
T / 1 = , the overall gain K of the
open loop must be, according to [6]:

(11)
2 / ) 1 (
1
2 2
+
=
a T
K
m
.

A value of K=0.14 was found from Eq. (11).
The phase margin is in this case [6]:

(12)
1
1
arctan
+

=
a
a
PM [deg].

Eq. (12) leads to a phase margin of 39.28, which is enough.
Knowing the other gain factors (
d
K , the PFD gain;
m
K , the motor
gain;
a
K , the DAC and amplifier gain, discussed in the Section 3.3;
z
K , the
encoder gain;
N
K , the programmable divider gain), the value of
1
was
determined.


(13) 146
14 . 0
50
1
60
60
320
65536
20
2
65536
1


= =

K
K K K K K
N z m a d
.

The parameters of the PI regulator are:

(14)
068 . 0
146
10
1
2
= = =

p
K ,
(15)
0068 . 0
146
1 1
1
= = =

I
K .

The encoder divisor value N = 50 was selected, meaning 50 / 1 =
N
K .
For the experiment, it was considered a motor speed reference of
approximately 600 rot/min, equivalent of 12 Hz. The reference signal generated
inside the FPGA from the 50MHz quartz oscillator was 11.92 Hz. It was
obtained by dividing the quartz signal by
22
2 , implemented by a 22 bit divider.
So, the sampling period of the system is T=0.084 s, which leads to a multiplying
factor for the second multiplier of:
18 Bogdan Alecsa and Alexandru Onea

(16) 0674288 . 0 068 . 0 0005712 . 0 = =
P I
K T K .

Taking into account the form of the factors, a better implementation
results considering the next form of Eq. (9):

(17) ] 1 [ ] 1 [ ] [ ] 1 [ ] [ + + = k T K k K k K k u k u
I P P
.

In this way, it can be used the fact that the factor ] 1 [ k K
P
has been
computed at the previous step, save it into a register and subtract it from the
currently computed value.
The modified block diagram of the filter is presented in Fig. 9.


Fig. 9 Modified digital filter block diagram.

This implementation separates the proportional and integral gain paths
and allows easy experimentation with different gain factors. It consumes more
resources of the FPGA, but it is better for prototyping and experiments.
Besides the shown blocks in the block diagram of the filter, additional
logic was implemented to saturate the numeric results at every computational
stage in case of overflow. This allows for the design to work even if the
processed numeric values are very high or very low, close to the limit of the 16
bit representation.
Taking into account that the multiplication factors are less than one and
the PFD output is an integer value, integer multiplication is applied after scaling
down the values. The scaling is done by an appropriate number of right shifts.
This scaling means the filter is effectively ignoring some of the bits of
the error signal. This increases the stability of the system, at the expense of a
slowly oscillating stationary regime: the error never gets effectively to zero.
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 19

3.3. Amplifier

The motor is controlled by the voltage supply variation provided by a
PWM signal delivered by the FPGA. The digital output of the FPGA is
configured to use the LVTTL standard. Logic value 1 is represented by 3.3 V.
This voltage is amplified to 10V by an operational amplifier in the Leybold
Didactic 73419 Gain and Offset Adjust Block. This voltage is applied to the
motor by a Leybold Didactic 73413 Power Amplifier Block. The bipolar output
of this block is used to drive the motor. So, logic one at the FPGA output means
20 V applied to the motor. Because of the integrator characteristic of the motor,
the PWM signal is converted to a voltage applied to the motor. The PWM
circuitry can be seen as a 16 bit DAC: the numeric value loaded into the PWM
register is converted to a voltage across the motor. For the experiments, a 24 V
Leybold Didactic Motor-Generator Set was used.
The filter output is a 16 bit signed integer number. The value will
converge to a positive number, because the motor is spinning only in one
direction. The PWM circuitry can use only unsigned integer numbers. The value
loaded into the PWM register is saturated to zero if a negative number is
supplied by the filter output. Also, to make use of the whole PWM register
range, the number is multiplied by 2 by shifting left one position upon loading
into the PWM register. This multiplication appears as a multiplication by 2 in
the DAC transfer function.
The transfer function of the DAC is:

(18)
65536
20
2
10 2
16
=

=
a
K .

The motor parameters identification was done by applying voltages to
the power amplifier input and observing the motor response using a frequency
to voltage converter. So the
m
K gain includes the gain of the power amplifier.

4. Experimental Results

The PLL controller was implemented using a Spartan-3E FPGA device.
The filter implementation was verified in open loop by applying a step
error input and observing the PWM output, filtered to obtain a voltage response.
The whole design was then tested in closed loop. The filter output
register was designed to be initialized to a value that would output a motor
speed close to the reference frequency.
The loop proved to achieve and maintain phase lock. Fig 10 presents the
reference signal generated inside the FPGA and the encoder signal divided by N
inside the FPGA. The two signals are maintained in lock.
20 Bogdan Alecsa and Alexandru Onea



Fig. 10 Reference signal and divided encoder signal in phase lock.

Experiments proved the phase detector to be very well suited for
keeping the phase lock and for achieving phase lock in the case of signals of
close frequencies. The phase detector is not so good in the case of a consistent
frequency difference between the signals.

5. Conclusions

A method to implement an all digital PLL controller in one FPGA chip
was presented. The major contribution in the design is the PFD, which gives a
numeric output. This allows the use of a digital filter as the loop regulator. This
is one of the main advantages of the design procedure: it offers the possibility to
experiment with different filters in the loop.
This type of PFD design gives the possibility to implement the whole
loop in a FPGA. This is different from usual ADPLL with numeric processing
presented in [5], where an ADC is needed to get a numeric error signal.
The circuit parts were verified by simulation and implemented in the
FPGA. The method for computing the PLL parameters was adapted to discrete
time. Experimental results show the effectiveness of the design method.
Future work must be done to investigate the performance of the
described controller and to experiment with other types of loop filters. Also, the
PFD can be improved to output the magnitude of the frequency error.

Received: January 12, 2009 Gheorghe Asachi Technical University of Iai,
Department of Automatic Control and
Applied Informatics
e-mails: balecsa@ac.tuiasi.ro
aonea@ac.tuiasi.ro
Bul. Inst. Polit. Iai, t. LV (LIX), f. 1, 2009 21

R E F E R E N C E S

1. Moore A.W., Phase-Locked Loops for Motor Speed Control. IEEE Spectrum, 61-67,
Apr. 1973.
2. Geiger D., Phaselock Loops for DC Motors. John Wiley, New York, 1981.
3. Hsieh G.C., Hung J.C., Phase-Locked Loops Techniques a Survey. IEEE Trans. On
Industrial Electronics, Vol. 43, 6, December 1996.
4. Abramovitch D., Phase-Locked Loops: a Control Centric Tutorial. Proceedings of
the American Control Conference, Anchorage, AK, May 8-10, 2002.
5. Best R.E., Phase-Locked Loops: Design, Simulation and Applications. McGraw-Hill,
5
th
Ed., 2003.
6. Machida H., Kobayashi F., PLL/PID Motor Control System by Using Time Domain
Operation of PWM Signal. SICE Annual Conference 2007, Kagawa
University, Sept 17-20, 2007.



IMPLEMENTARE N FPGA A UNEI BUCLE CU CALARE PE FAZ PENTRU
CONTROLUL MOTOARELOR DE CURENT CONTINUU

(Rezumat)

Aceast lucrare propune o metod de implementare a unei bucle digitale cu
calare pe faz (PLL) pentru controlul motoarelor de curent continuu. Controlul
motorului se realizeaz prin impulsuri PWM. Viteza motorului este detectat folosind
un tahometru optic ce produce un tren de impulsuri digitale. Bucla PLL este total
digital, ceea ce permite implementarea ei folosind doar circuite logice. Implementarea
este realizat ntr-un dispozitiv programabil FPGA Spartan-3E produs de Xilinx.
Contribuia principal este detectorul de faz cu ieire numeric, ce permite procesarea
numeric a semnalului mai departe. Aceasta este realizat prin proiectarea unui filtru
digital, implementat n FPGA folosind sumatoare i multiplicatoare. Rezultatele
experimentale obinute arat funcionalitatea sistemului. Resursele folosite din
dispozitivul FPGA sunt sub 10% din disponibil.