NAND GATE

NAND logic table

Input
Output
A B
0 0 1
0 1 1
1 0 1
1 1 0
The TTL 7400 chip, containing four NANDs. The two additional
pins supply power (! "# and connect the ground in digital
electronics, a NAND gate (Negated AND or NOT AND# is a logic
gate which produces an output that is false only if all its inputs are
true. A L$% (0# output results only if &oth the inputs to the gate
are '()' (1#* if one or &oth inputs are L$% (0#, a '()' (1#
output results. (t is +ade using transistors.
The NAND gate is significant &ecause any &oolean function can
&e i+ple+ented &y using a co+&ination of NAND gates. This
property is called functional co+pleteness.
Digital syste+s e+ploying certain logic circuits ta,e ad-antage of
NAND.s functional co+pleteness. (n co+plicated logical
e/pressions, nor+ally written in ter+s of other logic functions
such as AND, $0, and N$T, writing these in ter+s of NAND
sa-es on cost, &ecause i+ple+enting such circuits using NAND
gate yields a +ore co+pact result than the alternati-es.
112
The function NAND (a
1
, a
3
,..., a
n
# is logically e4ui-alent to N$T
(a
1
AND a
3
AND ... AND a
n
#.
Symbols
There are three sy+&ols for NAND gates5 the .distincti-e.
(6(L7AN8(# sy+&ol and the .rectangular. (9: sy+&ol, as well as a
deprecatedD(N sy+&ol so+eti+es found on old sche+atics. ;or
+ore infor+ation see logic gate sy+&ols.
MIL/ANSI Symbol IEC Symbol DIN Symbol
Hardware description and pinout
NAND gates are &asic logic gates, and as such they are
recognised in TTL and :6$8 (:s.
This sche+atic diagra+ shows the arrange+ent of NAND gates
within a standard 4011 :6$8 integrated circuit.
CMOS version
The standard, 4000 series, :6$8 (: is the 4011, which includes
four independent, two<input, NAND gates.
Availability
These de-ices are a-aila&le fro+ +ost se+iconductor
+anufacturers such as ;airchild 8e+iconductor, =hilips or Te/as
(nstru+ents. These are usually a-aila&le in &oth through<
hole D(L and 8$(: for+at. Datasheets are readily a-aila&le in
+ost datasheet data&ases.
The standard 3<, ><, 4< and ?<input NAND gates are a-aila&le5
:6$8
40115 @uad 3<input NAND gate
403>5 Triple ><input NAND gate
40135 Dual 4<input NAND gate
40A?5 6ono ?<input NAND gate
TTL
74005 @uad 3<input NAND gate
74105 Triple ><input NAND gate
74305 Dual 4<input NAND gate
74>05 6ono ?<input NAND gate
Implementations
The NAND gate has the property of functional co+pleteness. That
is, any other logic function (AND, $0, etc.# can
&e i+ple+ented using only NAND gates. An entire processor can
&e created using NAND gates alone. (n TTL (:s using +ultiple<
e+itter transistors, it also re4uires fewer transistors than a N$0
gate.
N6$8 NAND gate
:6$8 NAND gate TTL NAND gate
The physical layout of a :6$8 NAND