Modeling Memory Lab

Overview:
In this lab you will learn how to write a model to infer a simple single-port memory. You
will also learn how to instantiate a complex memory structure using CORE Generator
application. In both cases, you will model the memory as ROM.

Outcome:
You will understand how to access ISE language assistant to write an inferable model.
ISE also has CORE Generator system which allows configure complex function. Once
the desired function is created, you will learn how to access instantiation template and
use it to instantiate in your design. You will learn how to create a model using ISE create
project wizard. You will use ISE simulator to simulate the design. You will add user
constraint file (ucf) to assign pins so the design can be targeted to National Instruments
(NI) Digital Electronics FPGA Board. You will implement the design and create a
bitstream file using ISEs implementation tools. Once bitstream is created, you will
download using ISEs iMPACT program and verify the design functionality.

Background (to be completed after discussion):
Describe Language Assistant capability of ISE and the advantages and use of CORE
Generator to access and configure simple to complex functions

Design Procedure (to be discussed):
(should we have this section to show how the circuit is designed?)

References:
1. National Instruments Digital Electronics FPGA Board user manual
2. Verilog HDL books
Stephen Brown, Zvonko G. Vranesic, Fundamentals of Digital Logic with Verilog Design, 2002
Zainalabedin Navabi, Verilog Digital Systems Design: RT Level Synthesis, Testbench, and
Verification, 2005
Samir Paltinkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2003
Joseph Cavanagh, Verilog HDL: Digital Design and Modeling, 2007
Michael D. Ciletti, Modeling, Synthesis, and Rapid Prototyping with Verilog HDL, 2003
Douglas J. Smith, HDL Chip Design: A Practical Guide for Designing, Synthesizing and Simulating
ASICs and FPGAs using VHDL or Verilog, 1996
3. On-line references:
Verilog HDL Reference Card: http://www.stanford.edu/class/ee183/
handouts_win2003/VerilogQuickRef.pdf

Problem Statement:
Part A: Develop an inferable code to model a 16x4 ROM whose content is defined with
some random values. You then include that model to develop logic that will search the
content for the desired combination provided by switches input (a FSM is provided to
generate the address and detect GO). The design will wait for GO input before start
comparing. It will stop searching when either the desired content is found (asserting
DONE and SUCCESS) or end of memory has reached (asserting DONE and FAIL).
Part B: Use CORE Generator tool to generate 28x8 single port ROM with initialized data
(provided). You then include that memory to develop logic that will search the content
for the desired combination provided by switches input (a FSM is provided to generate
the address and detect GO). The design will wait for GO input before start comparing. It
will stop searching when either the desired content is found (asserting DONE and
SUCCESS) or end of memory has reached (asserting DONE and FAIL).

Implementation:
In Part A, you will use the Language Assistant of ISE to model a small ROM which is
implemented in LUT. In Part B you will use the CORE Generator system to model ROM
using BlockRAM. Though the BlockRAM you will model is 2kx8, you will use only
first 16 locations to search the content for illustration purpose.

Procedure:
Extract resources.zip file in c:\NI\Verilog_Labs folder
Part A- ROM Memory
1. Create a I SE project
Launch ISE: Select Start Programs Xilinx ISE Design Suite 10.1
ISE Project Navigator
In the Project Navigator, select File New Project. The New Project Wizard
opens
For Project Location, use the button to browse to C:\NI\Verilog_labs, and
then click OK
For Project Name, type memory_lab
Click Next
Select the following options and click Next
Device Family: Spartan3E
Device: xc3s500E
Package: ft256
Speed Grade: 5
Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog

The Create New Source dialog will appear. Click New Source and New
Source Wizard form will appear
Select Verilog Module in the Source Type window (left) and enter
rom_memory in the filename field
Click Next and I/O Port window will be displayed
Enter clk, go, rst as single bit input port, cmp_data as 4-bit input; and done,
success, and fail as single bit output ports and then click Next
Click Finish and then Yes to create the module file
Click Next, again Next, and Finish buttons to close the wizard
A project will be created, rom_memory.v model will be added in the Sources
hierarchy window, and the same file will be opened in a editor window

Select rom_memory in the Sources window, and select New Source
Select Verilog Module and enter rom in File name field, and click Next

In Ports fields, enter clk and en as single bit input, and addr as 4 bit input;
and data as 4-bit output
Click Next and then Finish
Select Edit Language Assistant or click on
Expand Verilog Synthesis Constructs Coding Examples
Rom/Lookup Table and then select Using 4-bit Case Statement

Copy the code displayed in the right window and place it in rom.v file
Comment out parameter, and <address> and <outdata_data> definitions
Change output port data to define it as reg type as you will modify the
<output_data> to data in the always block
Modify the code to have it reflect as shown below (the memory locations are
initialized with some random values)

Save and close the rom.v file
Click on rom_memory in Sources window, right-click, and select Add Copy
of Source
Browse to c:\NI\Verilog_labs\resources\memory_lab, select memory_fsm.v,
and click open to add the file
Open the memory_fsm.v file and understand its functionality
Modify the rom_memory file to instantiate rom and memory_fsm modules,
and compares roms output data to cmp_data input data so the final model
looks like below

Save and close the model

2. Simulate the design using I SE
Right-click on the rom_memory entry in Sources window, right-click and
select Add Copy of Source
Browse to C:\NI\Verilog_labs\resouces\memory_lab and select
rom_memory_tb.v. Notice that the Sources for window changes to
Behavioral Simulation from Implementation
Select rom_memory_tb in the Sources window, expand the Xilinx ISE
Simulator process in Processes window
Select Simulator Behavioral Model, right-click and select properties

Change the simulation run time from 1000 to 3000 ns and then click OK

Double-click Simulator Behavioral Model to run simulator
The model will be compiled and the simulator will be run
Simulation results will be displayed as shown below

You can see that it in the first set the cmp_data to 0x4, the data which the
memory was not initialized with (see the rom.v file) and hence the counter
counts all addresses and results in fail. The second set has the cmp_data set to
0x6 which the rom meory has as initialized content (location 15) and hence
results in success
Close the simulator

3. I mplement the design
Select implementation in Sources for window
The UCF either must be created or added
Add the provided ucf file (rom_memory.ucf) from
c:\NI\verilog_labs\resources\memory_lab folder
Select rom_memory module in Sources window and double-click on
Synthesize
When the synthesis is complete, expand the process and double click on View
Synthesis Report to view the report

Scroll down the report and search for the section that describes the rom.v
synthesis and note that 1 rom is being inferred
Close the report
Select rom_memory module in Sources window and double-click on
Implement Design process in Processes window. This will go through
Implementation stages


4. Verify the design in hardware
Select rom_memory in Sources window and double-click on Generate
Programming File process to generate the bit file for the design

Expand Configure Target Device process and double-click on Manage
Configuration Project (iMPACT) process

Connect the board with the USB-JTAG cable
Power ON the board
Click Finish to use the JTAG chain
Select rom_memory.bit file to be assigned to xc3s500e device and click Open
Click Bypass button for xcf04s and then OK to use FPGA device
programming
Right-click on the FPGA and select Program
This will program the FPGA and DONE light will lit on the board
Once programmed successfully, verify that the design works by setting
SW3:SW0 to 0x4 and pressing BTN0 (go) to observe LD0 (DONE) and LD2
(FAIL) going ON indicating failed search. Change the SW3:SW0 to 0x6 and
press BTN0 (go) to observe LD0 (DONE) and LD1 (SUCCESS) going ON
indicating successful search. You can try different switch settings
combinations. You can also change the values in rom.v, re-implement, re-
configure and test your design
Once confirmed the functionality, power down the board and close ISE saving
project changes

Part B- Block Memory Using CORE Generator

1. Extend the I SE project
Right-click anywhere in Sources window and select New Source
A new source wizard will appear
Select IP(CORE Generator & Architecture Wizard) in the Source Type
window (left) and enter block_2k_8_sp (2kx8 single port memory) in the
filename field
Click Next
Expand Memories & Storage Elements folder, then RAMs & ROMs, followed
by selecting Block Memory Generator v2.7

Click Next and then Finish. Block Memory Generator GUI will be displayed
Configure the block memory
Specify the Memory name and type on Page 1 and click Next

Component Name: block_2k_8_sp
Memory Type: Single Port ROM
Specify Port A parameters on Page 2

Read Width: 8
Read Depth: 2048
Enable: Always Enabled
Click Load Init File, browse to c:\ NI\Verilog_labs\resouces\memory_lab and
select the memory_data.coe file
Click Show button and verify that the content is loaded properly

Click OK, then Next, and finally Finish to generate the core and get it added
to the project

Select File Open, and open block_2k_8_sp.veo entry from the memory_lab
folder. The file shows how to instantiate the block that you just have created

Right-click anywhere in Sources window and select New Source
A new source wizard will appear
Select Verilog Module in the Source Type window (left) and enter
block_memory in the filename field
Click Next and I/O Port window will be displayed
Enter clk, go, rst as single bit input port, cmp_data as 8-bit input; and done,
success, and fail as single bit output ports and then click Next
Click Finish and then Yes to create the module file
Click Next, again Next, and Finish buttons to close the wizard
A file will be opened in the editor window area. Notice that the file is not
automatically added to the project. It will have to be done manually
Click on rom_memory in Sources window, right-click, and select Add
Source
Select block_memory.v and click open
Click on block_memory.v in the Sources window, right-click and select Set
as Top Module

Click OK to make changes
Modify the block_memory file to instantiate block_2k_8_sp and memory_fsm
modules, and write a statement that compares memorys output data to
cmp_data input data so the final model looks like below

Save and close the model. Notice that the hierarchy is formed and also
memory_fsm.v (which was present in the project under rom_memory model)
is also part of the block_memory hierarchy


2. Simulate the design using I SE
Right-click on the block_memory entry in Sources window, right-click and
select Add Copy of Source
Browse to C:\NI\Verilog_labs\resouces\memory_lab and select
block_memory_tb.v. Notice that the Sources for window changes to
Behavioral Simulation from Implementation
Select block_memory_tb in the Sources window, expand the Xilinx ISE
Simulator process in Processes window
Select Simulator Behavioral Model, right-click and select properties

Change the simulation run time from 1000 to 3000 ns and then click OK

Double-click Simulator Behavioral Model to run simulator
The model will be compiled and the simulator will be run
Simulation results will be displayed as shown below

You can see that it in the first set the cmp_data to 0xFF, the data which the
memory was not initialized with (see the rom.v file) and hence the counter
counts all addresses and results in fail. The second set has the cmp_data set to
0xC6 which the rom meory has as initialized content (location 11) and hence
results in success
Close the simulator

3. I mplement the design
Select implementation in Sources for window
The UCF either must be created or added
Add the provided ucf file (block_memory.ucf) from
c:\NI\verilog_labs\resources\memory_lab folder
Notice that now the design has two ucf files; one must be removed. So
remove the memory.ucf file by selecting its entry in Sources, right-clicking,
and then select Remove
Select block_memory module in Sources window and double-click on
Synthesize
When the synthesis is complete, expand the process and double click on View
Synthesis Report to view the report

Scroll down the report and search Device utilization summary phrase that
describes resources being used by the design and note that 1 block RAM is
being inferred
Close the report
Select block_memory module in Sources window and double-click on
Implement Design process in Processes window. This will go through
Implementation stages


4. Verify the design in hardware
Select block_memory in Sources window and double-click on Generate
Programming File process to generate the bit file for the design

Expand Configure Target Device process and double-click on Manage
Configuration Project (iMPACT) process

Connect the board with the USB-JTAG cable
Power ON the board
Click Finish to use the JTAG chain
Select block_memory.bit file to be assigned to xc3s500e device and click
Open
Click Bypass button for xcf04s and then OK to use FPGA device
programming
Right-click on the FPGA and select Program
This will program the FPGA and DONE light will lit on the board
Once programmed successfully, verify that the design works by setting
SW7:SW0 to 0xFF and pressing BTN0 (go) to observe LD0 (DONE) and
LD2 (FAIL) going ON indicating failed search. Change the SW7:SW0 to
0xC6, press BTN1 (rst) and then press BTN0 (go) to observe LD0 (DONE)
and LD1 (SUCCESS) going ON indicating successful search. You can try
different switch settings combinations, making sure that you are pressing
BTN1 every time before pressing BTN0
Once confirmed the functionality, power down the board and close ISE saving
project changes

Conclusion:
In this lab exercise you learned how to model an inferable ROM which uses LUT and
also how to use CORE Generator to develop BlockRAM based ROM. You were able to
simulate the design with fast clock and then verify the complete design in hardware board
using the derived slow clock.