Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits

http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]

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J OHN APRIL - 19 - 2010 29 COMMENTS
Flip Flops
Basic Flip Flops
Thi s ar ti cle deals wi th the basi c fli p flop ci r cui ts li ke S-R Fli p Flop, J -K Fli p Flop, D Fli p
Flop, and T Fli p Flop along wi th tr uth tables and thei r cor r espondi ng ci r cui t symbols.
Before going to the topic it is important that you get knowledge of its basics. Click on the links below for
more information.
TAKE A LOOK : BOOLEAN LOGIC
TAKE A LOOK : LOGIC GATES
TAKE A LOOK : HALF ADDER AND FULL ADDER
Flip flops are actually an application of logic gates. With the help of Boolean logic you can create memory
with them. Flip flops can also be considered as the most basic idea of a Random Access Memory [RAM].
When a certain input value is given to them, they will be remembered and executed, if the logic gates are
designed correctly. A higher application of flip flops is helpful in designing better electronic circuits.
The most commonly used application of flip flops is in the implementation of a feedback circuit. As a
memory relies on the feedback concept, flip flops can be used to design it.
There are mainly four types of flip flops that are used in electronic circuits. They are
The basic Flip Flop or S-R Flip Flop
Delay Flip Flop [D Flip Flop]
J-K Flip Flop
T Flip Flop
1. S-R Flip Flop
The SET-RESET flip flop is designed with the help of two NOR gates and also two NAND gates. These flip
flops are also called S-R Latch.
S-R Flip Flop using NOR Gate
The design of such a flip flop includes two inputs, called the SET [S] and RESET [R]. There are also two
outputs, Q and Q. The diagram and truth table is shown below.
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Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
S-R Flip Flop using NOR Gate
From the diagram it is evident that the flip flop has mainly four states. They are
S=1, R=0Q=1, Q=0
This state is also called the SET state.
S=0, R=1Q=0, Q=1
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the value of Q
follows the value of S.
S=0, R=0Q & Q = Remember
If both the values of S and R are switched to 0, then the circuit remembers the value of S and R in their
previous state.
S=1, R=1Q=0, Q=0 [Invalid]
This is an invalid state because the values of both Q and Q are 0. They are supposed to be compliments of
each other. Normally, this state must be avoided.
S-R Flip Flop using NAND Gate
The circuit of the S-R flip flop using NAND Gate and its truth table is shown below.
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Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
S-R Flip Flop using NAND Gate
Like the NOR Gate S-R flip flop, this one also has four states. They are
S=1, R=0Q=0, Q=1
This state is also called the SET state.
S=0, R=1Q=1, Q=0
This state is known as the RESET state.
In both the states you can see that the outputs are just compliments of each other and that the value of Q
follows the compliment value of S.
S=0, R=0Q=1, & Q =1 [Invalid]
If both the values of S and R are switched to 0 it is an invalid state because the values of both Q and Q are
1. They are supposed to be compliments of each other. Normally, this state must be avoided.
S=1, R=1Q & Q= Remember
If both the values of S and R are switched to 1, then the circuit remembers the value of S and R in their
previous state.
Clocked S-R Flip Flop
It is also called a Gated S-R flip flop.
The problems with S-R flip flops using NOR and NAND gate is the invalid state. This problem can be
overcome by using a bistable SR flip-flop that can change outputs when certain invalid states are met,
regardless of the condition of either the Set or the Reset inputs. For this, a clocked S-R flip flop is designed
by adding two AND gates to a basic NOR Gate flip flop. The circuit diagram and truth table is shown below.
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Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
Clocked S-R Flip Flop
A clock pulse [CP] is given to the inputs of the AND Gate. When the value of the clock pulse is 0, the
outputs of both the AND Gates remain 0. As soon as a pulse is given the value of CP turns 1. This makes
the values at S and R to pass through the NOR Gate flip flop. But when the values of both S and R values
turn 1, the HIGH value of CP causes both of them to turn to 0 for a short moment. As soon as the pulse
is removed, the flip flop state becomes intermediate. Thus either of the two states may be caused, and it
depends on whether the set or reset input of the flip-flop remains a 1 longer than the transition to 0 at
the end of the pulse. Thus the invalid states can be eliminated.
2. D Flip Flop
The circuit diagram and truth table is given below.
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
D Flip Flop
D flip flop is actually a slight modification of the above explained clocked SR flip-flop. From the figure you
can see that the D input is connected to the S input and the complement of the D input is connected to the
R input. The D input is passed on to the flip flop when the value of CP is 1. When CP is HIGH, the flip flop
moves to the SET state. If it is 0, the flip flop switches to the CLEAR state.
To know more about the triggering of flip flop click on the link below.
TAKE A LOOK : TRIGGERING OF FLIP FLOPS
TAKE A LOOK : MASTER-SLAVE FLIP FLOP CIRCUIT
3. J-K Flip Flop
The circuit diagram and truth-table of a J-K flip flop is shown below.
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
J-K Flip Flop
A J-K flip flop can also be defined as a modification of the S-R flip flop. The only difference is that the
intermediate state is more refined and precise than that of a S-R flip flop.
The behavior of inputs J and K is same as the S and R inputs of the S-R flip flop. The letter J stands for
SET and the letter K stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switch to the complement state. So, for a
value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.
The circuit includes two 3-input AND gates. The output Q of the flip flop is returned back as a feedback to
the input of the AND along with other inputs like K and clock pulse [CP]. So, if the value of CP is 1, the
flip flop gets a CLEAR signal and with the condition that the value of Q was earlier 1. Similarly output Q of
the flip flop is given as a feedback to the input of the AND along with other inputs like J and clock pulse
[CP]. So the output becomes SET when the value of CP is 1 only if the value of Q was earlier 1.
The output may be repeated in transitions once they have been complimented for J=K=1 because of the
feedback connection in the JK flip-flop. This can be avoided by setting a time duration lesser than the
propagation delay through the flip-flop. The restriction on the pulse width can be eliminated with a master-
slave or edge-triggered construction.
4. T Flip Flop
This is a much simpler version of the J-K flip flop. Both the J and K inputs are connected together and thus
are also called a single input J-K flip flop. When clock pulse is given to the flip flop, the output begins to
toggle. Here also the restriction on the pulse width can be eliminated with a master-slave or edge-triggered
construction. Take a look at the circuit and truth table below.
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
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T Flip Flop

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29 Responses to Flip Flops
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Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
Sir
In Clocked R S flip,Somewhere Two AND gate with clock or Two NAND gate with clock pulse used.But
problem is that what is the logic behind of Gate use.
Same thing happen D flip flop.
Actually i dont understand which gate have to use and which feedback is connecting to input(in case of
JK flip flop, somewhere Q feedback goes to J and Q feedback goes to K )
Reply
I need perfect truth table for 4 typs of the flipflops
Reply
Its seems that there is an error on the D flip flop Drowing, eather change tha NAND gates to AND, or
the NOR to NAND.
Currently the NOR gats has 1,1 on the inputs which is invalid input
Reply
I try to found Excitation table for flipflop but i could not :(..!!!
so try to add this point to.!!!
Reply
simple questions have simple answer
Reply
Very good..you made the topic very simple to understand
Reply
whats the importance of master slaving
Reply
whats the difference between an unclocked flip-flop and a latch
Reply
Manas Halder
July 24, 2014 at 10:38 am
Nafees
July 22, 2014 at 7:18 pm
Matan
April 22, 2014 at 9:27 am
vivek patel
March 11, 2014 at 11:56 pm
Akshay Kulkarni
November 22, 2013 at 1:14 am
Saikat
November 21, 2013 at 9:37 am
NTD
November 20, 2013 at 7:36 pm
NTD
November 20, 2013 at 7:18 pm
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
realy nice can be ellaborated more . but still nice
Reply
i want pin no.s for above fig.
Reply
thanks for information about flip flop in simple lang.
Reply
j.k ffs structure is WRONG!!!!!
Reply
There are three edge-triggered flip-flops namely SR, D and J-K that are used in digital logic circuits and
every flip-flop has its own operation. State that how these flip-flops can have an effect on the
performance of synchronous systems, and also discuss which flip-flop gives better performance? Give
arguments in the support of your answer.
Reply
thanks a lot
Reply
Sala mal tui master slave er nor gate diye ckt diagram disnai keno ?
Reply
Thanks
Reply
tanq
Reply
Tushar
November 8, 2013 at 1:07 pm
shraddha
October 30, 2013 at 7:39 am
shraddha
October 30, 2013 at 7:37 am
himanshu
October 27, 2013 at 9:17 am
mahaktarar
July 10, 2013 at 9:25 pm
ravindra
May 10, 2013 at 7:08 am
Ismail
April 24, 2013 at 8:47 pm
Akn Gedik
January 29, 2013 at 5:15 pm
triveni
October 3, 2012 at 5:39 am
ch.naveen karthik
May 3, 2012 at 12:26 am
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
thanks for the help
Reply
whats the relation between pulse width and output response of the flip flop.
Reply
Whats are the gates responsible for Subtraction, Divisionof Bit? Since Half Adder Admit Two Bits &
Sum And Full Adder Admit Two Bits, Sum And A Carry Bit?
Reply
I NEED VERILOG HDL TUTORIAL
Reply
go buy a MORIS MANO..
Reply
Jasa Setting Mikrotik Jasa Setting Proxy
Reply
thanks for the help.
Reply
i like it very much it is very useful to me for my assignment
i didnt found these data from other site it is very good
Reply
What is the use of flip flop.and what is mean by clock pulse?
Reply
What is the use of flip flop.and what is mean by clock pulse
Rajakumar
March 13, 2012 at 2:28 am
Mshelia
February 26, 2012 at 4:39 am
sai pradeep
February 8, 2012 at 4:06 am
bisban
October 16, 2013 at 6:32 am
http://www.deskapahendri.com/2011/02/28/jasa-setting-mikrotik-dan-proxy-super-
ngebut-24-jam/
December 10, 2011 at 3:07 am
madushan
November 18, 2011 at 11:58 pm
hrishi
November 15, 2011 at 6:19 am
Arunsnake4u
February 5, 2011 at 8:17 am
Md.Tajul Islam
January 6, 2013 at 11:38 pm
Basic Flip Flops-SR Flip Flop,J K Flip Flop,D Flip Flop,T Flip Flop,Circuits
http://www.circuitstoday.com/flip-flops[21-Sep-14 9:13:52 AM]
Reply
the information provided here is quite easy to understand and useful
Reply
thanq very muchthese are very helpful answers.
Reply
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