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SN54/74LS95B

4-BIT SHIFT REGISTER
The SN54/74LS95B is a 4-Bit Shift Register with serial and parallel
synchronous operating modes. The serial shift right and parallel load are activated by separate clock inputs which are selected by a mode control input.
The data is transferred from the serial or parallel D inputs to the Q outputs
synchronous with the HIGH to LOW transition of the appropriate clock input.
The LS95B is fabricated with the Schottky barrier diode process for high
speed and is completely compatible with all Motorola TTL families.





4-BIT SHIFT REGISTER
LOW POWER SCHOTTKY

Synchronous, Expandable Shift Right
Synchronous Shift Left Capability
Synchronous Parallel Load
Separate Shift and Load Clock Inputs
Input Clamp Diodes Limit High Speed Termination Effects

J SUFFIX
CERAMIC
CASE 632-08
14

CONNECTION DIAGRAM DIP (TOP VIEW)            

1

NOTE:
The Flatpak version has the
same pinouts (Connection
Diagram) as the Dual In-Line
Package.

14
1 

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5 U. 1 TTL Unit Load (U. b. 10 U.5 5.L.L.0 5.5 U.) = 40 µA HIGH/1.25 U. 0.L.25 U.5 U.L.L. 5 (2.0 mA FAST AND LS TTL DATA 5-171 . 74 – 0. 0.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54. 0. for Commercial (74) Temperature Ranges.5 U.5 U.25 U. ORDERING INFORMATION SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC NOTES: a.5 4. 0.5) U. 0. 0. 0.4 mA IOL Output Current — Low 54 74 4.L.L.25 U. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.L. 0.L.L.L.75 5.0 8.L. for Military (54) and 5 U.L. The Output LOW drive factor is 2.L. 0.5 U.6 mA LOW.L.25 U.0 5.              N SUFFIX PLASTIC CASE 646-06  14 1 PIN NAMES S DS P0 – P3 CP1 CP2 Q0 – Q3 D SUFFIX SOIC CASE 751A-02 LOADING (Note a) Mode Control Input Serial Data Input Parallel Data Inputs Serial Clock (Active LOW Going Edge) Input Parallel Clock (Active LOW Going Edge) Input Parallel Outputs (Note b) HIGH LOW 0.

SN54/74LS95B LOGIC DIAGRAM                    .

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Pn = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the Pn = HIGH to LOW clock transition. FAST AND LS TTL DATA 5-172 . and operating the LS95B in the parallel mode (S = HIGH). The serial or parallel mode of operation is controlled by a Mode Control input (S) and two Clock Inputs (CP1) and (CP2). A MODE SELECT — TRUTH TABLE INPUTS OUTPUTS OPERATING MODE S Shift L L Parallel Load H Mode Change CP1 CP2 DS Pn Q0 Q1 Q2 Q3 X X I h X X L H q0 q0 q1 q1 q2 q2 X Pn P0 P1 P2 P3 X X X X X X X X X X X X X X X X X L L H H L L H H L L L L H H H H No Change No Change No Change Undetermined Undetermined No Change Undetermined No Change L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one set-up time prior to the HIGH to LOW clock transition. CP1 is enabled.                    FUNCTIONAL DESCRIPTION HIGH to LOW transition on enabled CP1 transfers the data from Serial input (DS) to Q0 and shifts the data in Q0 to Q1. CP2 is enabled. When the Mode Control input (S) is LOW. S should only change states when both Clock inputs are LOW. Q2 to P1. Q1 to Q2. changing S from LOW to HIGH while CP2 is HIGH. and Q1 to P0. For normal operation. However. The LS95B is a 4-Bit Shift Register with serial and parallel synchronous operating modes. The serial (right-shift) or parallel data transfers occur synchronous with the HIGH to LOW transition of the selected clock input. h = HIGH Voltage Level one set-up time prior to the HIGH to LOW clock transition. It has a Serial (DS) and four Parallel (P 0 – P3) Data inputs and four Parallel Data outputs (Q0 – Q3). or changing S from HIGH to LOW while CP1 is HIGH and CP2 is LOW will not cause any changes on the register outputs. When the Mode Control input (S) is HIGH. A HIGH to LOW transition on enabled CP2 transfers parallel data from the P0 – P3 inputs to the Q0 – Q3 outputs. A left-shift is accomplished by externally connecting Q3 to P2. and Q2 to Q3 respectively (right-shift).

5 V 74 2.7 74 0.0 V) Limits Symbol Parameter Min Typ tW CP Pulse Width 20 ns ts Data Setup Time 20 ns th Data Hold Time 20 ns ts Mode Control Setup Time 20 ns th Mode Control Hold Time 20 ns FAST AND LS TTL DATA 5-173 Test Conditions VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C. VIN = 2.4 V IOL = 4.0 mA 74 0.4 V –100 mA VCC = MAX 21 mA VCC = MAX Max Unit Note 1: Not more than one output should be shorted at a time. IOH = MAX.0 54 0. nor for more than 1 second.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN. AC CHARACTERISTICS (TA = 25°C. VCC = 5.5 3.65 – 1.35 0. VCC = 5.8 – 0. VIN = 0.7 V – 20 0.5 V IOL = 8.4 mA VCC = MAX. VIN = VIH or VIL per Truth Table VCC = VCC MIN. 74 0.0 mA 20 µA VCC = MAX. VIN = 7.0 V) Limits Symbol fMAX tPLH tPHL Parameter Maximum Clock Frequency Min Typ 25 36 Test Conditions MHz 18 27 ns 21 32 ns Max Unit CP to Output VCC = 5.SN54/74LS95B DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input HIGH Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max 2.1 mA VCC = MAX.0 V – 0.25 0.7 3.0 V . IIN = – 18 mA 54 2. VIN = VIL or VIH per Truth Table 54.5 V VCC = MIN.

HOLD TIME (th) — is defined as the minimum time following AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. SETUP TIME(ts) —is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH to LOW in order to be recognized and transferred to the outputs.SN54/74LS95B DESCRIPTION OF TERMS the clock transition from HIGH to LOW that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH to LOW and still be recognized.   .

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