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SBS Avionics Technologies

2400 Louisiana Boulevard, NE


AFC Building 5, Suite 600
Albuquerque, NM 87110-4316
Fax: 505-875-0400
Email: sbshelp@sbse.com
http://www.sbs-avionics.com
800-SBS-1553 or 505-875-0600
Applies to model:
A429-PC8, 429-PC16, A429-PC104
A429-cPCI, A429-PCI, A429-PCMCIA, A429-V2

ARINC 429

Users Manual

ARINC 429 Users Manual

1998 SBS Technologies, Incorporated. All rights reserved.
ARINC 429 Reference Manual Version 2.0
This document is the intellectual property of SBS Technologies, Inc. (SBS), and contains proprietary
and condential information. Use, disclosure, and reproduction is permitted only under the terms of
a software license agreement or explicit written permission of SBS. You should not use this document
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This document and its contents are provided as is, with no warranties of any kind, whether express
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In no event will SBS be liable for any lost revenue or prots or other special, indirect, incidental and
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SBS Technologies, Inc. and its logo are trademarks of SBS Technologies, Inc. All other brand names
and product names contained herein are trademarks, registered trademarks, or trade names of their
respective holders.

Table of Contents i

1: Overview & Startup............................................................................................. 1-1

Conve ntions .............................................................................................................................................. 1-2
Archite cture Ove rvie w............................................................................................................................. 1-3
De sign Re vie w ........................................................................................................................................... 1-4

2: Control Registers................................................................................................. 2-1

Hardware Control Re giste rs ................................................................................................................... 2-2
Me mory Acce ss ......................................................................................................................................... 2-9
Software Control Re giste rs (ARINC 429 Proce ssing Control)......................................................... 2-11
Syste m Clock Re giste rs ......................................................................................................................... 2-20

3: Device Management Firmware Reference.................................................... 3-1

Module Startup/Te st ................................................................................................................................ 3-1
A429 Software Download Instructions ................................................................................................. 3-2
Exte rnal Trigge rs ..................................................................................................................................... 3-11
Exte rnal Clock.......................................................................................................................................... 3-15
Inte rrupt Manage me nt.......................................................................................................................... 3-16

4: Transmitter Firmware Reference..................................................................... 4-1

Control Block Structure .......................................................................................................................... 4-2
Pe riodic Command Block Structure ..................................................................................................... 4-8
Ape riodic Command Block Structure ................................................................................................. 4-15
Channe l Wrap Ope rations ..................................................................................................................... 4-17
Double -Buffe r Transmit Block Fe ature ............................................................................................... 4-20

5: Receive Management Firmware Reference.................................................. 5-1

Re ce ive Data Structure ............................................................................................................................ 5-2
Firmware Ope ration ................................................................................................................................. 5-9
Controlling Ope ration ............................................................................................................................ 5-10

6: Bus Monitoring Firmware Reference.............................................................. 6-1

Se que ntial Monitoring ............................................................................................................................. 6-2
Global Re giste rs ........................................................................................................................................ 6-3
Channe l Re giste rs..................................................................................................................................... 6-4
Filte r Table ................................................................................................................................................. 6-6
Global and Channe l Se que ntial Monitor Buffe rs ................................................................................. 6-8
Monitor Buffe r Words ............................................................................................................................ 6-10
Trigge ring ................................................................................................................................................. 6-14

A: PCMCIA Socket Controller Setup...................................................................... A-1

Introduction .............................................................................................................................................. A-1
Ge ne ral Card Se rvice s Information ........................................................................................................ A-2
Table of Cont ent s

ii Table of Contents

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B: Card Specic Information................................................................................. B-1

Module Spe cications ............................................................................................................................. B-2
De sign Re vie w .......................................................................................................................................... B-8
Me mory Organization ........................................................................................................................... B-11

C: A429 Standard Interface Libraries.................................................................... C-1

Compile r Issue s ........................................................................................................................................ C-1
Library Re fe re nce Table of Conte nts .................................................................................................... C-2
De vice Manage me nt and Low Le ve l Routine s .................................................................................... C-5
BIT Manage me nt Routine s ................................................................................................................... C-33
Re ce ive Manage me nt Routine s........................................................................................................... C-34
Transmit Manage me nt Routine s ......................................................................................................... C-42
Monitor Manage me nt Routine s .......................................................................................................... C-51
Inte rrupt Manage me nt Routine s ........................................................................................................ C-62

D: Operating System Specic Information......................................................... D-1
E: ARINC 429 Standard Unit Test............................................................................ E-1

Library Re fe re nce Table of Conte nts .................................................................................................... E-1
Unit Te st Application ............................................................................................................................... E-2
Sample Applications .............................................................................................................................. E-14

F: An ARINC 429 Commentary................................................................................ F-1

Pre face ....................................................................................................................................................... F-1
About the ARINC Organization .............................................................................................................. F-2
Introduction To ARINC 429 ..................................................................................................................... F-3
Ele ctrical Ele me nts .................................................................................................................................. F-6
Word And Protocol Me thods ............................................................................................................... F-10
Summary.................................................................................................................................................. F-19

1-1

The multichannel ARINC 429 Interface (A429) provides concurrent simulation
of multiple transmit channels, monitoring of multiple receive channels, sequen-
tial monitoring, advanced interrupt services, and high-speed host operations.
The microprocessor design incorporates the latest in DSP processor technology
to provide the most exible, open designed ARINC 429 device in the industry.
The chapters in this manual provide an overview of ARINC architecture and
design along with detailed instructions for starting up and programming the
A429 device. The specic chapters are:


Overview & Startup


Control Registers


Device Management Firmware Reference


Transmitter Firmware Reference


Receive Management Firmware Reference


Bus Monitoring Firmware Reference

Overview &
St art up

This chapter serves as an introduction and basic outline of the rest of the
manual.

Cont rol
Regist ers

This chapter details the processes (host commands) and control registers which
allow the host application program to control hardware and data structures for
ARINC 429 processing. The host command set syntax and key software control
registers for managing ARINC 429 processing are described, and hardware reg-
isters that are directly accessible from the PC (i.e., CSR, and 48-bit clock) are
detailed in this subsection.

Device
Management
Firmware
Ref erence

This chapter details the processes for setting up and general operation of the
A429 transmitters and receivers.

Transmit t er
Firmware
Ref erence

This chapter details the data structures associated with simulating A429 mes-
sages. It explains the denition and management of Transmit command blocks
and their associated data buffers. Command blocks are linked to allow for ex-
ible and accurate A429 simulation.
1: Over vi ew & St ar t up

1-2 Overview & Startup

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Receive
Management
Firmware
Ref erence

The A429 hardware has a sophisticated data structure for real-time monitoring
of ARINC 429 trafc. This chapter shows how to set up individual current value
tables for monitoring. These current value tables are ideal for real-time host pro-
cessing. All current value tables are time-stamped with a 48-bit, 1-sec clock
value.

Bus Monit oring
Firmware
Ref erence

This chapter provides information on how to perform monitoring functions for
the A429 data bus.

1.1 Convent ions

The following conventions appear in this document. These conventions may dif-
fer from those used in other SBS publications. The subsections listed below de-
scribe each convention in more detail:


Typographic Conventions


Symbols

1.1.1 Typographic Conventions

The table below shows the typographic conventions used in this document.

Element Use in body text for: Use in procedures for:

Italic


Document, chapter, section, and
topic titles and cross references.


Emphasis.


Filenames, directory paths
Bold


(Not used in body text.)


Controls, dialogs, menus, and
text or numeric elds that appear
on the screen.


Keys on your keyboard.
Courier Roman


Code examples.


Library function calls.


Simulating the appearance of
screens.
Courier Bold


Emphasizing lines of code.


Commands and other
information that you type as
given.
Angle brackets, e.g.,<
>


Enclosing variable information
that you type in place of a
dummy variable.


Enclosing variable information
that you type in place of a
dummy variable.

Architecture Overview 1-3

1.1.2 Symbols

The following symbols appear throughout our manuals.

Warning:

Paragraphs ne xt to this symbol contain information

critical to module ope ration, or to your safe ty.

Note:

Paragraphs ne xt to this symbol contain information

important to module ope ration.

Tip:

Paragraphs ne xt to this symbol contain use ful tips.

Cross Reference:

Paragraphs ne xt to this symbol contain

cross re fe re nce s to a re late d chapate r or page in this manual.

Software Cross Reference:

Paragraphs ne xt to this symbol
contain cross re fe re nce s to software me dia include d with

this product.

1.2 Archit ect ure Overview

The A429 device interfaces host computer systems to multiple ARINC 429
buses.
The A429 architecture uses a DSP processor to handle ARINC 429 simulation
and monitoring tasks. Low-level processes control simulated ARINC 429 mes-
sages, and monitor ARINC 429 messages for protocol verication. High level
processing is responsible for moving ARINC 429 message packets in real-time
to and from data buffers that you dene. Your application program denes and
manages Transmit, Receive, and Monitor data structures in a main memory area
where the A429 reads and stores ARINC 429 messages.
Transmit, Receive, and Monitor data structures and host command program-
ming are controlled by the hosts application program. Through memory data
structures and command sets, the host controlling program may direct ARINC
429 data for real-time processing.

1-4 Overview & Startup

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NOTE:

The chapte rs e ntitle d

Control Registers,



Device Man-
agement Firmware Reference

,

Transmitter Firmware Refer-
ence

,

Receive Management Firmware Reference

,



and

Bus
Monitoring Firmware Reference

de tail the host inte rface to

the A429-PC application control structure s.

1.3 Design Review

The design of the A429 incorporates an open systems philosophy. The A429 is
a generic processing engine (the DSP processor and most of the hardware clock
and control circuits are software programmable) that can be congured through
various application programs. This manual explains the application program
(rmware) SBS has designed for optimal ARINC 429 bus processing and sim-
ulation. In this application, processing for each of the four, eight, or sixteen
channels is performed independently through host-dened Transmit, Receive,
and Monitoring data structures (detailed in later chapters). The board's design
allows for custom programs (written by the customer or SBS) to correlate data
between channels, or provide advanced processing to off-load the host system.
For all boards except cPCI, PCI, and PCMCIA, you need to set address DIP
switches in order for the host to access the board. For the PC8, PC16, and
PC104, you use the switches to set the boards base I/O register. For the V2, the
switches are used to set the boards base address and address mode. Other host
settings for interrupt level and vectors are software programmable and are de-
tailed later in the

Chapter 2: Control Registers

chapter.

2-1

The sections in this chapter provide a review of control registers. Control regis-
ters provide key setup information used by the host and A429 system (i.e., set-
ting the board's control and status register). In host programmed control
registers, information processing remains unchanged during activation of A429
processing for the respective channels.
The rst section describes

Hardware Control Registers

. The hardware control reg-
isters provide the following module functions to the host:


A429 reset and operation control


Host interrupt control


DSP interrupt control


A429 memory access control
The

Memory Access

section describes the I/O port reads and writes to necessary
to access A429 memory. The

Software Control Registers (ARINC 429 Processing
Control)

section describes the holds and parameters which dene interrupt
queues, transmit and receive operations, and sequential monitor control.

Note:

All addre sse s and data value s are in he xade cimal.
2: Cont r ol Regi st er s

2-2 Control Registers

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2.1 Hardware Cont rol Regist ers

Table 2.1.1 lists the hardware control registers. Detailed discussions for each
register follow the table.

Table 2.1.1: Hardware Control Registers

P
C
8
P
C
1
6
P
C
1
0
4
V
2
c
P
C
I
/
P
C
I
P
C
M
C
I
A
Name
Word Addr
Byte Addr
(in hex)
Description



CSR
00
000
Control/Status Register. Key regis-
ter for proper initialization and op-
eration of the A429.


CSR2
04
008
PC16 Control/Status Register 2.
Key register for proper initialization
and operation of the PC16 Device 2.


CSR
20000
40000
Control/Status Register. Key regis-
ter for proper initialization and op-
eration of the A429.


CSR
01
002
I/O Control/Status Register. Key
register for proper initialization and
operation of the PCM.



ADRS_PORT
01
002
Address Port for host access to the
devices RAM. This register con-
tains 16 bits corresponding to word
addresses 0000h to FFFFh.



DATA_PORT
02
004
Data Port 1 for reading/writing to
Device 1 RAM.


ADRS_PORT2
01
002
Address Port 2 for host access to the
PC16 Device 2 RAM. This register
contains 16 bits corresponding to
word addresses 0000h to FFFFh.


DATA_PORT2
02
004
Data Port 2 for reading/writing to
PC16 Device 2 RAM.


BASE_ADR
01
002
Memory Base Address Register.
Register used to set the memory
base address of the board in the
PC104 hosts memory area.


INTV_A429
(r/w)
01
002
Bits 0-7 of this register set the
VMEbus interrupt vector for A429
user-selected interrupts for the V2.
Bit 0 is the least-significant bit.


INTV_A429
Gen Inter
(wo)
02
004
Write any data to this register to
cause a VMEbus interrupt (having
the vector specified by word ad-
dress 01h) to occur. This is used for
factory testing but may also used by
the user to verify proper VME ISR
operation.


PLD_DNLD
(wo)
00
000
PLD Download Register. Register
downloads the PLD data.

Hardware Control Registers 2-3

2.1.1 I/ O Control/ Status Register

I/O Control/Status Register (CSR) contains bits which control module opera-
tion, and PC and DSP interrupts. Except where otherwise noted, the host has
both read and write access to the CSR bits.

Note:

The following table is use d for the PC8 and the PC16.

Table 2.1.2: PC8/ PC16 Device 1 Control/ Status Register

Bit No. Function Description

0 Window Select 1
0 = lower 128k bytes
1 = upper 128k bytes
1 Reserved
2 Auto Increment 1
When set to 1, causes the address port
(ADRS_PORT1) to increment to the next word
address with each access to the data port, read or
write.
3 PC Interrupt Enable
0 = PC Interrupts disabled
1 = PC Interrupts enabled
4 Interrupt Level Select 0 These bits determine the PC interrupt priority level
to be used by the board. This level is used by all in-
terrupts:
000 = No Interrupt100 = IRQ10
001 = IRQ5101 = IRQ11
010 = IRQ7110 = IRQ12
011 = IRQ9111 = IRQ15
5 Interrupt Level Select 1
6 Interrupt Level Select 2
7
Interrupt Pending (RO)
Interrupt Clear (WO)
0 = No interrupt pending, 1 = Interrupt pending
0 = No function, 1 = Clears pending interrupt
8
Dual Device (ro)
Signal 1 (wo)
[0 = 2nd device not present, 1 = 2nd device present
(PC16)]
0 = No function, 1 = Signal processor 1 (future use
only)
9 Run 0 = Firmware Stop, 1 = Firmware Run
10-15 Reserved

2-4 Control Registers

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Table 2.1.3: PC16 Device 2 Control/ Status Register

Bit No. Function Description

0 Window Select 2
0 = lower 128k bytes
1 = upper 128k bytes
1 Reserved
2 Auto Increment 1
When set to 1, causes the address port
(ADRS_PORT2) to increment to the next word ad-
dress with each access to the data port, read or
write.
3 PC Interrupt Enable
0 = PC Interrupts disabled
1 = PC Interrupts enabled
4 Reserved
5 Reserved
6
Interrupt Pending 1 (ro)
Interrupt Clear 1 (wo)
0 = No Interrupt 1 pending, 1 = Interrupt 1 pending
0 = No function, 1 = Clears pending Interrupt 1
7
Interrupt Pending 2 (ro)
Interrupt Clear 2 (wo)
0 = No Interrupt 2 pending, 1 = Interrupt 2 pending
0 = No function, 1 = Clears pending interrupt
8
Dual Device (ro)
Signal 1 (wo)
0 = 2nd device not present, 1 = 2nd device present
0 = No function, 1 = Signal processor 2 (future use
only)
9 Run 2 0 = Firmware Stop, 1 = Firmware Run
10-15 Reserved

Hardware Control Registers 2-5
Table 2.1.4: PC104 Control/ Status Register

Bit No. Function Description

0 Channel Enable
0 = memory accesses ignored
1 = memory accesses acknowledged
1 Select 0 Memory Bit selection bit 0
2 Select 1 Memory Bit selection bit 1
3 PC104 Host Interrupt Enable
0 = PC104 Host Interrupts disabled
1 = PC104 Host Interrupts enabled
4 Interrupt Level Select 0 These bits determine the PC interrupt priority level
to be used by the board. This level is used by all in-
terrupts:
000 = No Interrupt100 = IRQ10
001 = IRQ5101 = IRQ11
010 = IRQ7110 = IRQ12
011 = IRQ9111 = IRQ15
5 Interrupt Level Select 1
6 Interrupt Level Select 2
7
Interrupt Pending (ro)
Interrupt Clear (wo)
0 = No interrupt pending, 1 = Interrupt pending
0 = No function, 1 = Clears pending interrupt
8
Signal (ro)
Select 0* (wo)
0 = No function, 1 = Signal processor (future use
only)
0 = Select 0 is set, 1 = Select 0 is not set
9 Run 0 = Firmware Stop, 1 = Firmware Run
10-15 Reserved

2-6 Control Registers

Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:35
Table 2.1.5: V2 Control/ Status Register
Table 2.1.6: V2 CSR Interrupt Level Select Bits
Bit No. Function Description
0 Run
0 = firmware stop
1 = firmware run
1 Code Location Select
0 = load from data RAM
1 = load from FLASH memory
2 Reserved
Reserved for factory test purposes. SET THIS BIT
TO 0 WHEN WRITING TO THE CSR.
3 VMEbus Interrupt Enable
0 = clear
1 = enable interrupt
When this bit is enabled, an interrupt can be gener-
ated by the V6 with the corresponding vector in
register word offset 01h.
4
Interrupt Pending (ro)
Interrupt Clear (wo)
0 = no interrupt
1 = interrupt pending (read)
/clear interrupt (write)
Read this bit to determine whether a VMEbus in-
terrupt is pending. Set this bit to clear the interrupt.
5-7
Interrupt Level Select 0 Interrupt
Level Select 1 Interrupt Level Select
2
These bits determine the VMEbus interrupt
priority level to be used by the V2 board.
This level is used by all interrupts.
8-15 Reserved Reserved for future use
CSR
Bit No.
Bit
Function
Interrupt level
(se t bits 5-7 as illustrate d be low for the de sire d inte rrupt le ve l)
level 0 level 1 level 2 level 3 level 4 level 5 level 6 level 7
5
Interrupt Level
Select 0
0 1 0 1 0 1 0 1
6
Interrupt Level
Select 0
0 0 1 1 0 0 1 1
7
Interrupt Level
Select 0
0 0 0 0 1 1 1 1
Hardware Control Registers 2-7
Table 2.1.7: V2 Hardware Control Registers
Table 2.1.8: cPCI/ PCI Control/ Status Register
Name
Word Addr
Byte Addr
(in hex)
Description
INTV_A429
(r/w)
01
002
Bits 0-7 of this register set the VMEbus interrupt vector for A429
user-selected interrupts for the V2. Bit 0 is the least-significant bit.
INTV_A429
Gen Inter
(wo)
02
004
Write any data to this register to cause a VMEbus interrupt (having
the vector specified by word address 01h) to occur. This is used for
factory testing but may also used by the user to verify proper VME
ISR operation.
Bit No. Function Description
0 Run
0 = rmware stop
1 = rmware run
1 DSP Startup Mode
0 = load from data RAM
1 = load from FLASH memory
2 Reserved
3 cPCI/PCI Interrupt Enable
0 = cPCI/PCI Interrupts disabled
1 = cPCI/PCI Interrupts enabled
4-6 Reserved
7
Interrupt Pending (ro)
Interrupt Clear (wo)
0 = no interrupt
1 = interrupt pending (read)
/clear interrupt (write)
Read this bit to determine whether a host
interrupt is pending. Set this bit to clear the
interrupt.
8-15 Reserved Reserved for future use
Note: Exce pt whe re othe rwise note d, the host has both re ad and write asse ss to the
SER bits.
2-8 Control Registers
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Table 2.1.9: PCMCIA I/ O Control/ Status Register Bits
Table 2.1.10: PCMCIA Download Register
Bit No. Function Description
0 Run
0 = rmware stop
1 = rmware run
1 Select 0 Memory WIndow selection bit 0
2 Select 1 Memory WIndow selection bit 1
3-4 Reserved Reserved for future use
5 Program Enable 1 = Enable board for DSP programming
6 PMC host Interrupt Enable
0 = PCM host interrupts disabled
1 = PCM host interrupts enabled
7
Interrupt Pending (ro)
Interrupt Clear (ro)
0 = No interrupt pending, 1 = An interrupt is pending
0 = No function, 1 = Clears pending interrupt
8-15 Reserved Reserved for future use
Note: Exce pt whe re othe rwise note d, the host has both re ad and write acce ss to the
CSR bits.
Bit No. Function Description
0 PLD Data Holds value of PDL data bit being stored
1 PLD Clock Clock bit used to store PLD data
2 PLD Reset
0 = PLD
1 = Normal operation
3 PLD Output Enable
0 = Disable output
1 = Enable output
4-15 Reserved Reserved for future use
Memory Access 2-9
2.2 Memory Access
Table 2.2.1: Memory Base Address Register (BASE_ADR) for PC104
Table 2.2.2: Device1 (2) Memory Address Register (ADRS_PORT1(2)) for the
PC8/ PC16
Table 2.2.3: External Output Port Register (DATA_PORT1 (2))for the PC8/ PC16
BIt Function Description
0 Address 16 Address Line 16 Compare Value
1 Address 17 Address Line 17 Compare Value
2 Address 18 Address Line 18 Compare Value
3 Address 19 Address Line 19 Compare Value
4 Address 20 Address Line 20 Compare Value
5 Address 21 Address Line 21 Compare Value
6 Address 22 Address Line 22 Compare Value
7 Address 23 Address Line 23 Compare Value
8 Enable Change 0 Must write as 1 to allow change of address
9 Enable Change 1 Must write as 0 to allow change of address
10-15 Reserved --
P
C
8
P
C
1
6
BIt Function Description
0-15
Output Address
(ro)
Provides address for access to device 1 RAM
(ADRS_PORT1 and ADRS_PORT2 for the PC16)
P
C
8
P
C
1
6
BIt Function Description
0-15
Input/Output
Data (ro)
Provides data to/from RAM (DATA_PORT1 and
DATA_PORT2 for the PC16)
2-10 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:35
For the PC8 and PC16, memory access is accomplished through I/O port reads
and writes. The PC8 has two and the PC16 has four 16-bit I/O ports provided
for accessing A429 memory (see Table 2.2.2 and Table 2.2.3).
To access a PC8 or the rst device on a PC16
1. Load the addre ss that is to be writte n to or re ad from into ADRS_PORT
(ADRS_PORT1 of De vice 1 for the PC16).
2. Re ad or write to DATA_PORT (DATA_PORT1 of De vice 1 for the PC16) to acce ss
me mory at the addre ss spe cie d by ADRS_PORT (ADRS_PORT1 of De vice 1 for
the PC16).
3. To acce ss De vice 2 of the PC16, write the addre ss to be acce sse d to
ADRS_PORT2 and re ad or write the data to or from DATA_PORT2.
In the PC8, bit 0 of the CSR (CSR1 and CSR2 of the PC16) se le cts the uppe r or
lowe r 128 kilobyte s of A429 me mory. Use this bit to acce ss the full 256
kilobyte s of me mory. In the PC16, use CSR1 bit 0 to acce ss the full 256 kilobyte s
of De vice 1 me mory and use CSR2 bit 0 to acce ss the full 256 kilobyte s of
De vice 2 me mory.
Note: Addre sse s 0000h-07FFh and 10000h-107FFh are re -
se rve d for inte rnal use by the de vice .
4. Se t bit 2 of the CSR to 1 to cause ADRS_PORT (ADRS_PORT1 of De vice 1 for the
PC16) to automatically incre me nt to the ne xt word location with e ach acce ss
of the DATA_PORT (DATA_PORT1 of De vice 1 for the PC16).
This allows acce ss to a range of A429 de vice me mory without having to update
ADRS_PORT with e ach me mory re ad or write .
5. For the PC16 you ne e d to se t bit 2 of CSR2 to 1 to cause ADRS_PORT2 to
automatically incre me nt to the ne xt word location with e ach acce ss of the
DATA_PORT2.
To access A429 memory, complete the following steps:
1. Se t the I/O base addre ss to an available location be twe e n 000h and 7FFh.
Note: In the PC16, comple te ste ps 2-5 for e ach de vice (De vice
1 and 2). To acce ss De vice 1, use CSR1, ADRS_PORT1, and
DATA_PORT1. To acce ss De vice 2, use CSR2, ADRS_PORT2, and
DATA_PORT2.
Software Control Registers (ARINC 429 Processing Control) 2-11
2. Se t the de vice me mory window se le ct bit (bit 0) in the CSR to 0 for window
1 or 1 for window 2.
3. If de sire d, se t the auto-incre me nt bit (bit 2) to 1 to automatically incre me nt
the addre ss in ADRS_PORT.
4. Write the addre ss of the A429 me mory location that is to be acce sse d to
ADRS_PORT.
5. Write to or re ad from DATA_PORT to acce ss A429 me mory at the addre ss
spe cie d by ADRS_PORT.
2.3 Sof t ware Cont rol Regist ers (ARINC 429 Processing Cont rol)
The Software Control Registers table contains parameters and pointers to vari-
ous data structures required for successful operation of the A429 devices rm-
ware.
Note: To acce ss all sixte e n channe ls of the board, the param-
e te rs and data structure s de scribe d in this table must be de -
ne d for both de vice s of the A429-PC16. For De vice 1, acce ss
the parame te rs and data structure s through DATA_PORT1.
For De vice 2, acce ss the parame te rs and data structure s
through DATA_PORT2.
2-12 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:35
Table 2.3.1: Software Control Registers - D16 Access
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
General Control Registers
CMD
(wo)
880
1100
Commands the start of ARINC 429 bus processing. Write a non
zero value to this register to start bus processing. Write a zero to
this register to halt bus processing.
RESP
(ro)
881
1102
This word continuously increments in response to CMD not set to
zero. This provides a simple check that the firmware is running.
While counting, this word should never be equal to zero (zero is
skipped in the counting).
DVTYPE
(ro)
842
1084
Device Type. Indicates the total number of channels available on
the A429 device.
RXCNT
(ro)
843
1086
Receive Count. Indicates the total number of receivers available.
This value should match the value set during start-up in offset
800h.
TXCNT
(ro)
844
1088
Transmit Count. Indicates the total number of transmitters avail-
able. This value should match the value set during start-up in offset
801h.
CHCPTR
884
1108
Channel control pointer. Points to the base of the channel control
table. CHCPTR contains a value of 900h.
BTCSR
(r/w)
885
110A
Bus traffic control/status. Set this register to a nonzero value to re-
set the bus traffic word count (BTWCNT) to "0". This register will
be cleared to "0" when the word count has been reset.
GFLAG
(r/w)
886
110C
Global Flag. This register is the global control register for all
transmit blocks. Set bit 0 of this register to a 1 to cause the End
of Command Interrupt NOT to occur when the NO-OP bit is set.
System Clock Registers
SCLOW
(r/w)
896
112C
The firmware uses an internal 48-bit, 1-microsecond timer.
Contains the least significant 16 bits.
SCMID
(r/w)
897
112E
Contains the middle 16 bits of the system timer.
SCHIGH
(r/w)
898
1130
SCHIGH contains the most significant 16 bits of the system timer.
CCW
(r/w)
899
1132
Clock Control Word. Each bit corresponds to an action. Bit 0: read
timer and update SCHIGH, SCMID, and SCLOW, send interrupt
code 7 when update is valid; Bit 1: read timer and update SCHIGH,
SCMID, and SCLOW, no interrupt; Bit 2: reset internal timer with
values stored in SCHIGH, SCMID, and SCLOW. Updates and re-
sets are done within 100 microseconds.
Software Control Registers (ARINC 429 Processing Control) 2-13
Interrupt Registers
IQRSP
(r/w)
89B
1136
Interrupt Queue Response flag word: Set IQRSP=FFFFh to process
interrupts. Set IQRSP=0001h when processing is complete.
IQPTR1 *
(r/w)
89C
1138
Offset to Interrupt Queue 1. This queue is processed by the host
computer.
IQPTR2 *
(r/w)
89D
113A
Offset to Interrupt Queue 2. This is the queue which is currently
active. The host should NOT process this queue.
IQCNT1
(ro)
89E
113C
Contains the number of entries in Interrupt Queue 1. This is used
by the host computer's ISR to process the IQPTR1 queue.
IQCNT2
(wo)
89F
113E
Contains the number of entries in Interrupt Queue 2.
Warning: Do not acce ss this re giste r while the A429
de vice is proce ssing ARINC 429 data.
IQNUM
(r/w)
8A0
1140
Defines the maximum number of entries per interrupt queue. If the
number of entries exceeds the value in IQNUM, an interrupt over-
flow will occur. The default value for this register is "4".
Transmit Operation Registers
Addresses are offsets from the base of each channel control table. Channel control tables
start at 900h and have a length of 1Fh. Therefore, channel 1 table occupies 900h to 91Fh,
channel 2 table occupies 920h to 93Fh, etc.
CHTYPE
(ro)
Offset 00
Channel type. This word defines whether the control table is being
used for a receiver or transmitter channel. If this register contains
0h, the channel is a receiver; if this register contains FFFFh, the
channel is a transmitter.
CMDBCW
(r/w)
Offset 01
Command block control word. This word governs transmit and
command block operations for a specific channel. Set bit 0 of
CMDBCW to 1 to halt processing of the command block upon
completion of the current command block. Set bit 1 of CMDBCW
to 1 to cause the channel to operate at 100 KHz. Set bit 1 to 0
to cause the channel to operate at 12.5 KHz. Set bit 3 of CMDBCW
to 1 to enable Channel Wrap. Set bit 3 of CMDBCW to 0 to
disable Channel Wrap. Set bit 4 of CMDBCW to 1 to enable
Channel Wrap Error Injection. Set bit 4 of CMDBCW to 0 to
disable Channel Wrap Error Injection.
CBIPTR
(r/w)
Offset 02
Command block initial pointer. This location is continuously mon-
itored by the A429's firmware. When CBIPTR is nonzero, the
firmware sets this pointer to zero and executes a chain of command
blocks beginning at the offset defined in CBIPTR.
CBCPTR
(ro)
Offset 03
Command block current pointer. This location points to the current
location in the command block structure. This pointer is zero until
processing of a command block structure begins.
CBLPTR
(ro)
Offset 04
Command block last pointer. This location indicates the last com-
mand block that was executed before a halt occurred.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
2-14 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:35
MNFCNT
(r/w)
Offset 05
Minor frame count. This value determines the number of minor
frames to be executed for each major frame.
MNCNT
(ro)
Offset 06
Minor count. This value indicates the current minor frame being
processed.
MJFCNT
(r/w)
Offset 07
Major frame count. This value determines the number of major
frames to execute before halting command block processing. Set
MJFCNT to "0" for continuous operation.
MJCNT
(ro)
Offset 08
Major count. This value indicates the current major frame being
processed.
CBCTMP
(ro)
Offset 09
Temporary command block current pointer. This register is used
for A-periodic block processing. This value is only used by the
A429 firmware.
TXHPAM
(r/w)
Offset 0A
Transmit high priroity asynchronous message. This control register
allows the transmission of additional block(s) within a minor frame
or transmit block whenever there is DEAD bus time. Program the
high priority command block pointed to by TXHPAM (Ah).
TXLPAM
(r/w)
Offset 0B
Transmit low priority asynchronous message.This control register
allows the transmission of additional block(s) within a minor frame
or transmit block whenever there is DEAD bus time. Program the
low priority command block pointed to by TXLPAM (Bh), then
program TXLPAT (Ch) register with the time required to execute
the block.
TXLPAT
(r/w)
Offset 0C
Transmit low priority asynchronous time. This register is used with
TXLPAM and contains the amount of time required to execute the
message block.
LFRAME
(ro)
Offset 0D
Low frame. This register contains the least significant 16 bits of
the 48-bit time at which the last minor frame type command was
processed.
MFRAME
(ro)
Offset 0E
Middle frame. This register contains the middle 16 bits of the 48-
bit time at which the last minor frame type command was pro-
cessed.
HFRAME
(ro)
Offset 0F
High frame. This register contains the most significant 16 bits of
the 48-bit time at which the last minor frame type command was
processed.
CWPTR
(r/w)
Offset 10
Channel Wrap Pointer. Used for channel wrap feature and consists
of LMASK, HMASK, and TXWCNT for each label.
BTWCNT
(ro)
Offset 12
Bus traffic word count. The value in this register increments for
each word received or transmitted. A word count is provided for
each channel.
CHLED
(ro)
Offset 13
Channel Activity Indicator. Indicates bus activity for a specific
channel: 0000h = not active, 00FFh = active, FF00h = transmitting
with errors.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
Software Control Registers (ARINC 429 Processing Control) 2-15
Command Block Pointer Locations
Addresses are offsets from the base of each command block
CMDTYP Offset 0
Command type. This register specifies the type of command and action
to take. 0 = minor frame type, 1 = transmit type.
MFLTME
(r/w)
Offset 01
Minor frame low time. This register contains the lower 16 bits of the
time, in microseconds, allotted for a minor frame.
MFHTME
(r/w)
Offset 02
Minor frame high time. This register contains the upper 16 bits of the
time, in microseconds, allotted for a minor frame.
SCLTME
(r/w)
Offset 01
Schedule low time. This register contains the lower 16 bits of the time,
in microseconds, that must expire before the transmit command block
is processed. The time is referenced from the minor frame.
SCHTME
(r/w)
Offset 02
Schedule high time. This register contains the upper 16 bits of the
time, in microseconds, that must expire before the transmit command
block is processed. The time is referenced from the minor frame.
TBCNT
(r/w)
Offset 03
Transmit buffer count. This register is associated with the transmit
type command and indicates the number of words to transmit. Each
value to be transmitted requires three 16-bit words. The first word is
the control word, followed by the lower 16 bits of the ARINC data
word, followed by the upper 16 bits of the ARINC data word. There-
fore, the total length of the transmit buffer is TBCNT * 3.
TXWCNT
(r/w)
N/A
Transmit word control. Use this register to inject errors on and control
a transmitted data word. Set one of four bits to 1 to inject the follow-
ing errors: Bit 0: Parity Disable, Bit 1: Generate Even Parity, Bit 2: En-
able Bit Errors, Bit 3: Add/Subtract a Bit, and Bit 5: Transmit sync.
TXWCNT is stored with the data word in the transmit data buffer as
the first 16-bit word in the 3-word block. Bits 12-14: Used to program
interword gap (0-15) bit times. Bit 10: 0 = default or sustain gap time,
1 = set gap time.
TDBPTR
(r/w)
Offset 04
Transmit data buffer pointer. This value is associated with the transmit
type command and points to the base of the transmit buffer for the as-
sociated command block.
WRDCNT
(ro)
Offset 05
Word count. This register is associated with the transmit type com-
mand and indicates the current location in the transmit data buffer.
START
(r/w)
Offset 06
Start frame. This register indicates which minor frame a transmit type
command block will begin executing.
REPRTE
(r/w)
Offset 07
Repetition Rate. This register indicates how often to process a transmit
type command block after the START condition is met. If REPRTE=2,
processing of the command block will occur every other time the asso-
ciated command block is accessed. If no minor frame structure is de-
fined, set this value to "0".
LNKPTR
(r/w)
Offset 0B
Link Pointer. This value points to the next command block. If LNKP-
TR equals zero, processing of the command structure for that channel
will halt.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
2-16 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:35
Receive Registers
Addresses are offsets from the base of each channel control table. Channel control tables
start at 900h and have a length of 1Fh. Therefore, channel 1 table occupies 900h to 91Fh,
channel 2 table occupies 920h to 93Fh, etc.
CHTYPE Offset 00
Channel type. This word defines whether the control table is being
used for a receiver or transmitter channel. If this register contains
0h, the channel is a receiver; if this register contains FFFFh, the
channel is a transmitter.
RCVCW
(r/w)
Offset 01
Receive control word. This word contains eight bits used for con-
trolling receiver operations.
Bit 0 1=run, 0=halt
Bit 1 1=100KHz, 0=12.5KHz
Bit 2 1=interrupt on error, 0=no interrupt
Bit 3 1=sort by SDI/label, 0= sort by label
Bit 4 1=channel monitor halted (RO), 0=channel monitor
running
Bit 5 1=restart channel monitor, 0=don't restart
Bit 6 1=force channel monitor swap, 0=no swap
Bit 7 1=interrupt on channel monitor swap, 0=no interrupt
Bit 8 1=swap current value table, 0=no swap
Bit 9 Interrupt on current value swap.
Bit 12 1=channel wrap enabled, 0=channel wrap disabled
CVBPTR
(r/w)
Offset 02
Current value buffer pointer. This register contains the pointer to
the base of the receive current value buffer. The current value buff-
er is a buffer where the most current data for each received word is
stored by SDI, label, or both. Use this pointer to service the current
value table.
CTBPTR
(ro)
Offset 03
Current time buffer pointer. If nonzero, a 48-bit time stamp is sup-
plied for received data. The time stamps are sorted by SDI, label,
or both. Use this value to service the current time table.
GFTPTR
(r/w)
Offset 04
Global Filter Pointer. This register contains an offset to a table of
128 or 512 words arranged by SDI, label number, or both. Entries
in this table govern interrupts and sequential monitoring for each
possible receive SDI, label, or both. The bits in each word in the
table determine the following: Bit 0: Sequential Monitor Enable,
Bit 1: Interrupt on Label, Bit 2: Disable Parity Checking, and Bit
3: Buffer Swap on Label.
CFTPTR
(r/w)
Offset 05
Channel filter pointer. This register contains an offset to a table of
128 or 512 words arranged by SDI, label number, or both. Entries
in this table govern interrupts and sequential monitoring for each
possible receive SDI, label, or both. Bits in each word in the table
are as follows: bit 0-channel monitor enable, bit 3-buffer swap on
label.
Note : if parity disable is se t for the global se que ntial
monitor, parity che ck will automatically be disable d for
the channe l monitors.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
Software Control Registers (ARINC 429 Processing Control) 2-17
CVAPTR
(r/w)
Offset 06
Current value active pointer. This register contains a pointer to the
currently active current value buffer. To get the current values, set
bit 8 of RCVCW to a "1'. This will cause the pointers CVBPTR and
CVAPTR, as well as CVTPTR and CTAPTR, to swap. Bit 8 of
RCVCW will be set to 0 when it is safe to read the current values.
Always read from the buffer pointed to by CVBPTR.
CTAPTR
(r/w)
Offset 07
Current time active pointer. This register contains a pointer to the
currently active current time buffer. (see discussion of CVAPTR
for servicing procedures)
CWTX
(r/w)
Offset 08
Channel wrap transmitter. Used for channel wrap feature, desig-
nates which transmitter data will be channel wrapped to. Valid
transmit channels are 2 thru 8.
LABCNT
(ro)
Offset Ah
Label counter. This register contains an offset table to a table of
256 words arranged by Label number. Entries in this table provide
a counter for each time the Label is encountered. (Used by PASS
for frequency calculation between received labels on the same
channel.)
* CMIPTR
(r/w)
Offset Bh
Channel monitor initial pointer. This register contains a pointer to
the base of the channel monitor. This value must be initialized to a
nonzero value prior to writing a nonzero value to the CMD register.
CMCPTR
(ro)
Offset Ch
Channel monitor current pointer. This register contains a pointer to
the currently active channel monitor buffer. Received data is stored
in this buffer.
CMLPTR
(ro)
Offset Dh
Channel monitor last pointer. This register contains a pointer to the
last monitor buffer filled. Data in this buffer is safe to read.
CMCNT
(r/w)
Offset Eb
Channel monitor count. This register contains a value indicating
the monitor swap count. This value is incremented each time a
channel monitor swap occurs. It can be initialized to any value.
This value will roll over to 0000h once FFFFh swaps occur.
CMCNT is stored in the channel monitor buffer at offset 4 when a
swap occurs.
BTWCNT
(ro)
Offset 12
Bus traffic word count. The value in this register increments for
each word received or transmitted. A word count is provided for
each channel.
CHLED
(ro)
Offset 13
Channel Activity Indicator. Indicates bus activity for a specific
channel: 0000h = not active, 00FFh = active, FF00h = receiving
with errors.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
2-18 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:36
Figure 2.3.1 gives a pictorial representation of the software control registers.
Sequential Monitor Registers
GMCWRD
(r/w)
8A9
1152
Global monitor control word. This word governs sequential mon-
itoring on a global level. The bits determine the following:
Bit 0 Monitor Halted Bit 3 Interrupt on Swap
Bit 1 Restart Monitor Bit 4 Buffer Overflow
Bit 2 Force Buffer Swap
* GMIPTR
(r/w)
8AA
1154
Global monitor initial pointer. Points to the base of the first se-
quential monitor buffer. This pointer must be a nonzero value prior
to writing a nonzero value to the CMD register.
GMCPTR
(ro)
8AB
1156
Global monitor current pointer. Points to the base of the currently
active sequential monitor buffer.
GMLPTR
(ro)
8AC
1158
Global monitor last pointer. Points to the base of the last sequential
monitor buffer that was accessed.
GMCNT
(r/w)
8AD
115A
Global Monitor Buffer Counter.
Trigger Registers
TRGCW
(r/w)
8A3
1146
Trigger control word. This value defines the trigger location and
indicates trigger activity:
0=triggering stopped 2=trigger at middle
1=trigger at start 3=trigger at end
TGIPTR
(r/w)
8A4
1148
Trigger initial pointer. Indicates the base offset of the first trigger
control block. This value must be nonzero for trigger operation.
TGCPTR
(ro)
8A5
114A
Trigger current pointer. Indicates the base offset of the currently
active trigger control block.
TGLPTR
(ro)
8A6
114C
Trigger last pointer. Indicates the base offset of the last trigger con-
trol block that was accessed.
XTCWD
(r/w)
8B0
1160
External trigger control word. This value governs external triggers
1, 2 and 3. The bits determine the following:
Bit 0 Enable External Triggers
Bit 1 External Trigger 1 Select
Bit 2 External Trigger 2 Select
Bit 13 Enable Trigger IN for External Clock (Wait for External
Trigger).
Bit 14 Enable Clock Master
0=Master 2=Slave
Bit 15 Enable External Clock
LEGEND:

* Entry required for proper firmware operation
r/w = read/write, ro = read only, wo = write only
Word offset locations between 840h and AFFh that are not described in this table are re-
served. Accessing these locations produces unpredictable results.
Name
(host
access)
Word
Addr
Byte Addr
(in hex)
Description
Software Control Registers (ARINC 429 Processing Control) 2-19
Figure 2.3.1: Software Control Registers
8FFh
8AEh
CMD
RESP
RESERVED
RESERVED
CHCPTR
BTCSR
|
RESERVED
APPL PROD CODE
APPL VER NUM
DVTYPE
RXCNT
TXCNT
BRDMOD
|
|
RESERVED
SCLOW
SCMID
SCHIGH
CCW
RESERVED
IQRSP
IQPTR1
IQPTR2
IQCNT1
IQCNT2
IQNUM
RESERVED
RESERVED
TRGCW
TGIPTR
TGCPTR
TGLPTR
RESERVED
RESERVED
GMCWRD
GMIPTR
GMCPTR
GMLPTR
XTCWD
RESERVED
|
880h
840h
845h
884h
896h
89Bh
8A3h
8A0h
8A9h
8B0h
87Fh
CH1TBL
|
CH2TBL
|
CH3TBL
|
CH4TBL
|
CH5TBL
|
CH6TBL
|
CH7TBL
|
CH8TBL
|
900h
920h
940h
960h
980h
9A0h
9C0h
9E0h
A00h
871h
870h
LSTEND
LSTST
GFLAG
886h
GMCNT
PC104
PC8/cPCI-8/PCI-8/
PC16/V2
2-20 Control Registers
Doc: a429 re f 02.fm, ve r 2.0, 1 Jun 1999, 09:36
2.4 Syst em Clock Regist ers
2.4.1 Clock Control Word (CCW), SCHIGH, SCMID, SCLOW
To obtain the latest time information, set bit 1 of the clock control word (CCW)
to 1. This causes the rmware to calculate the current 48-bit system time and
update the SCHIGH, SCMID, and SCLOW registers. When it has updated these
registers, the rmware clears CCW, indicating to the user that the time update is
complete. The rmware completes this action within 100 microseconds after bit
1 of CCW is set to 1. Set bit 0 to 1 (instead of bit 1) to cause the rmware
to update the time registers and interrupt (with interrupt code 7) the host imme-
diately after the time update is complete.
SCHIGH, SCMID, and SCLOW may also be used to preset the 48-bit system
time. Load SCHIGH, SCMID, and SCLOW with the desired time and then set
bit 2 of the CCW to 1. The rmware will set the system time to these values
and then will clear the CCW.
2.4.2 Bus Trafc Control/ Status Register (BTCSR)
Set this register to a nonzero value to reset the bus trafc word count
(BTWCNT) to 0. This register will be cleared to 0 when the word count has
been reset.
2.4.3 Hardware Reset
If the hardware reset button on the host system is pressed, the CSR is reset and
rmware execution is halted. At this point, memory is still intact and may be ac-
cessed. After a hardware reset, the rmware must be restarted (see the Module
Startup/Test subsection) and memory will be cleared at this time.
Module Startup/ Test 3-1
3.1 Module St art up/Test
Note: This se ction de scribe s the ste ps re quire d to initialize
De vice 1 of the A429 PC-16. To initialize De vice 2, re pe at the
proce dure s, substituting CSR2, ADRS_PORT2, and
DATA_PORT2 for CSR1, ADRS_PORT1, and DATA_PORT1.
This se ction also de scribe s the ste ps re quire d to initialize
De vice 1 of the A429 V2. To initialize De vice 2, re pe at the
proce dure s.
3.1.1 A429 Initialization Steps
Prior to startup, the A429 module must be properly installed in the host comput-
er system. Once installation is accomplished, the A429 is ready to be congured
and initialized for ARINC 429 operations. The startup procedure consists of
several steps which must be completed in the proper sequence. The following
table outlines these steps and gives the related manual section or subsection.
3: Devi ce Management Fi r mw ar e Ref er ence
Step Procedure Related Section or Subsection
1 Set up the base I/O address Section 2.2: Memory Access
2 Set up the memory mode and memory
base address
Section 2.1: Hardware Control Registers
3 Download the firmware code Section 3.1: Module Startup/Test
4 Start up the module in BIT mode and
run tests if desired
Section 3.1: Module Startup/Test
5 Switch to application program mode Section 3.1: Module Startup/Test
6 Program control registers for each
channel
Chapter 2: Control Registers
7 Enable bus processing Section 3.1: Module Startup/Test
3-2 Device Management Firmware Reference
Doc: a429 re f 03.fm, ve r 2.0, 1 Jun 1999, 09:36
The control/status register is always accessible to the host. Program the control/
status register anytime during A429 operation.
Cross Reference: Se e Section 2.1.1: I/O Control/Status Register for
more de tails about e ach of the se proce dure s.
3.2 A429 Sof t ware Download Inst ruct ions
The A429 requires all rmware code to be downloaded prior to initializing ap-
plication data structures. One ASCII le contains all the rmware code in one
ASCII le.
The data in the download le is structured as 16-bit words. The rst sixteen
words make up the le header, containing product and version information. The
seventeenth word in the le contains a word count value (N), for the rst half of
the data in the le (See Figure 3.2.1).
Figure 3.2.1: A429 Download File Format
End of File
Firmware File
16 Header Words
Word Count N
Word 1
Word 2
Word N
Word Count P
.
.
.
A429-PC Memory
Offset 800h
Offset 800h + N
Offset 2C00h
Offset 2C00h + P
Offset 12C00h
Offset 12C00h + X
Word 1
Word 2
Word P
.
.
.
Word 1
Word 2
Word X
.
.
.
A429 Software Download Instructions 3-3
3.2.1 Downloading the Firmware from a File
To download the rmware code to the A429, complete the following steps:
1. Ope n the rmware code le (te xt mode ).
2. Re ad the run bit in the CSR (bit 9 for PC-8, PC-16, PC-104 or bit 0 for V2, cPCI,
PCI) of the I/O Control Re giste r (CSR) to ve rify that the inte rnal proce ssor is
not running. (If re quire d, write a 0 to this bit to halt proce ssing.)
Cross Reference: Se e Chapter 2: Control Registers of this manual.
3. Write a data value of 000Ah to offse t 0FFFFh.
4. Re ad and skip the rst sixte e n words in the rmware le .
5. Re ad the ne xt word. This is the word count, N.
6. Re ad the ne xt word from the le and write the word to me mory, starting at
offse t 00800h.
7. Continue re ading the le , writing the data, and incre me nting the addre ss
until N words have be e n re ad and writte n.
8. Afte r the Nth word is proce sse d, re ad the ne xt word. This is the word count, P.
9. Re pe at ste ps 5 and 6 with a starting offse t of 02C00h until P words have be e n
re ad and writte n.
10. Afte r the Pth word is proce sse d, re pe at Ste ps 5 and 6 with a starting addre ss
of 10800h until the e nd of the le is re ache d.
PC8 and PC16 Note: To acce ss me mory addre sse s 10000h and
above , se t bit 0 of the CSR to 1 .
3.2.2 Instructions for Downloading the PLD and Firmware Files
The PCMCIA requires all PLD data and rmware code to be downloaded prior
to initializing application data structures. The PLD data and rmware code is
contained in three les. The PLD data le is in a binary format and the rmware
code les are in an ASCII format.
3-4 Device Management Firmware Reference
Doc: a429 re f 03.fm, ve r 2.0, 1 Jun 1999, 09:36
Downloading
t he PLD Dat a
Use the PLD Download Register (I/O Port 0) to download the PLD data to the
PCMCIA:
1. Re se t the PLD by se tting bits 2 and 3 of the PLD Download Re giste r to 1 . Wait
approximate ly 100 millise conds to allow the PLD to re se t itse lf.
2. Se t bit 2 to 0 to be gin downloading (le ave bit 3 e qual to 1 ).
3. Ope n the PLD data le (binary mode ).
4. Using the I/O Control/Status Re giste r, ve rify that the inte rnal proce ssor is not
running.
5. Starting at the be ginning of the le , re ad one byte at a time , until the value s
obtaine d from two conse cutive re ads are FFh and F2h. This value , FFF2h, is the
pre amble and the rst value to be downloade d.
Note: Each value is downloade d one bit at a time , be ginning
with the most signicant bit of the pre amble . Thre e write in-
structions (ste ps f, g, and h be low) must be pe rforme d to
download e ach bit.The PLD Download Re giste r consists of
four bits:
bit 3Output Enable - always se t this bit to 1
bit 2Re se t - always se t this bit to 0
bit 1Clock - toggle this bit from 0 (ste p f) to 1 (ste p g) to 0
(ste p h)
bit 0Data - se t this bit e qual to the value of the bit be ing
downloade d
6. Write a 4-bit value to the PLD Download Re giste r as follows: se t bit 3 to 1 , se t
bit 2 to 0 , se t bit 1 to 0 , and se t bit 0 e qual to the value of the bit be ing
downloade d (Whe n downloading the most signicant bit of the pre amble ,
this value will be 1001 ).
7. Write a 4-bit value to the PLD Download Re giste r as follows: se t bit 3 to 1 , se t
bit 2 to 0 , se t bit 1 to 1 , and se t bit 0 e qual to the value of the bit be ing
downloade d (Whe n downloading the most signicant bit of the pre amble ,
this value will be 1011 ).
8. Write a 4-bit value to the PLD Download Re giste r as follows: se t bit 3 to 1 , se t
bit 2 to 0 , se t bit 1 to 0 , and se t bit 0 e qual to the value of the bit be ing
downloade d (Whe n downloading the most signicant bit of the pre amble ,
this value will be 1001 ).
9. Re pe at Ste ps 6, 7, and 8 for e ach of the re maining bits in the pre amble .
A429 Software Download Instructions 3-5
10. Re ad the ne xt byte from the PLD data le .
11. Re pe at Ste ps 6, 7, and 8 for e ach bit, be ginning with the most signicant.
12. Continue re ading byte s from the PLD data le and writing bits to the PLD
Download Re giste r until the e nd of the le is re ache d.
3.2.3 Downloading the Firmware Code
Complete the following steps to download the rmware code to the PCMCIA:
1. Ope n the bootloade r code ASCII te xt le (bootload.txt).
2. Using the I/O Control/Status Re giste r, ve rify that the inte rnal proce ssor is not
running and the program e nable bit is se t to 1 .
3. Re ad the rst 16-bit he xade cimal word from the ASCII le .
4. Starting at offse t 0000h, write the data word that was re ad in Ste p 3.
5. Continue re ading the le , writing the data, and incre me nting the addre ss
until the e nd of the le is re ache d.
6. Ope n the te xt le code.txt.
7. Re pe at Ste ps 2 and 3.
8. Starting at offse t 0100h, re pe at Ste p 3.
9. Re pe at Ste p 5.
3.2.4 Instructions for Starting the Firmware
After powering-up or resetting the PCMCIA module, rst download the code/
data les per the software download instructions. Upon completion of the down-
load, perform the following procedure to start up the PCMCIA:
1. Write FFFFh to the BIT Status re giste r (offse t 83Bh).
2. Write 0001h to the I/O Control/Status Re giste r to start the PCMCIA rmware .
3. Re ad the BIT Status re giste r and wait for the value to e qual 0000h, indicating
that the powe r-up te sts have comple te d.
4. Re ad the BIT total e rror count (offse t 83Ch). The value will be nonze ro if e rrors
we re de te cte d.
5. Afte r this proce dure is comple te d, the PCMCIA is in BIT mode awaiting a
command. Eithe r se le ct BIT te sts to be pe rforme d or initialize the board for
1553 ope rations.
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3.2.5 Downloading the Firmware from Flash
Note: This proce dure only applie s to the A429 cPCI-8, PCI-8, and V2.
After powering-up or resetting the V2, cPCI-8, or PCI-8 module, complete the
following steps to start up the module using the ash memory:
1. Write 0002h to the CSR (offse t 0) to re se t the hardware .
2. Write 000Ah to offse t 0FFFFh.
3. Write FFFFh to the BIT Status re giste r (offse t 83Bh).
4. Write 0003h to the CSR to start the rmware .
5. Re ad the BIT Status re giste r and wait for the value to e qual 0000h, indicating
that the powe r-up te sts have comple te d.
6. Re ad the BIT total e rror count (offse t 83Ch).
Note: The value will be nonze ro if e rrors we re de te cte d. If a
nonze ro value occurs, contact SBS Te chnologie s.
Note: Conguration of ash download can be ve rie d at off-
se ts 0x800 (numbe r of re ce ive rs) and 0x801 (numbe r of trans-
mitte rs).
After this procedure has been completed, the V2, cPCI, and PCI are in BIT
mode awaiting a command. Either select BIT tests to be performed or initialize
the board for ARINC operations.
3.2.6 Reprogramming the Flash Memory
The ash memory on the V2, cPCI-8, or PCI-8 may be reprogrammed, provid-
ing rmware updates at your site without the need for PROM replacements. The
procedure is similar to the two methods of module startup previously described
in Section 3.2.1: Downloading the Firmware from a File and Section 3.2.5:
Downloading the Firmware from Flash. Complete the following steps:
1. Pe rform a Software Download with the ne w code to be programme d.
2. Pe rform a Module Startup - Data RAM Mode . This will ve rify that the code is
loade d into the board me mory be fore re programming the FLASH.
3. Pe rform the Software Download with the ne w code to be programme d.
A429 Software Download Instructions 3-7
4. Pe rform a Module Startup - Flash Mode using the following ste ps:
a. Indicate the numbe r of re ce ive rs in offse t 0F808h and the numbe r of
transmitte rs in offse t 0F809h. If a valid conguration is e nte re d, offse t
0F80Ah will cle ar, and the proce ss will comple te . If an invalid
conguration is e nte re d, offse t 0F80Ah will e qual BADDh, and the
proce ss will fail.
b. Write 0002h to the CSR (offse t 0 for the V2 and 20000h for the cPCI and
PCI) to re se t the hardware .
c. Write C0DEh to Program Command Re giste r 1 (offse t 0FC00h).
d. Write 1234h to Program Command Re giste r 2 (offse t 0FC01h).
e. Write FFFFh to the BIT Status Re giste r (offse t 83Bh).
f. To start the rmware , write 0003h to the CSR.
g. Re ad the BIT Status Re giste r and wait for the value to e qual 0000h,
indicating that the powe r-up te sts have comple te d.
Note: Comple tion of Ste p g re quire s up to ve se conds.
h. Re ad both Program Command Re giste rs (offse ts 0FC00h and 0FC01h).
Note: The value s will be nonze ro if ash programming e rrors
we re de te cte d.
Note: Flash me mory will contain only one conguration
base d upon value s e nte re d at 0xF808h (numbe r of re ce ive rs)
and 0xF809h (numbe r of transmitte rs) offse ts. In orde r to
change congurations, ash me mory must be re pro-
gramme d.
The procedures in Section 3.2.6: Reprogramming the Flash Memory repro-
grams the ash memory with the new code. The new code restarts the device.
After this procedure is completed, the device is in BIT mode awaiting a com-
mand.
3.2.7 Module Startup/ Channel Assignments
St art up t he
A429
After powering-up or resetting the A429 module, rst download the rmware
code per the software download instructions in Section 3.2.1: Downloading the
Firmware from a File. Upon completion of the download, perform the following
procedure to start up the A429:
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1. For the PC-8 and PC-16 only, se le ct Me mory Window 1 by writing 0000h to the
I/O Control re giste r (CSR).
2. Write 0200h for the PC8, PC16, and PC104; and 0001h for the V2, cPCI, and PCI
to start the A429 rmware .
3. Re ad the ENCDEC Status re giste r (offse t 802h) and wait for the value to e qual
BADDh, indicating that the de vice is in channe l conguration mode .
4. Indicate the numbe r of re ce ive rs in offse t 800h and the numbe r of
transmitte rs in offse t 801h. If a valid conguration is e nte re d, the ENCDEC
Status re giste r will cle ar to 0000h and the proce ss will comple te .
Note: The total numbe r of available channe ls can be re ad from
offse t 803h if ste ps 1 through 3 we re succe ssful. All e ight channe ls
must be congure d for e ithe r re ce ive or transmit.
5. For e xample , to congure the A429 de vice for 2 re ce ive channe ls and 6
transmit channe ls, write a 2 to offse t 800h and a 6 to offse t 801h (se e Table
3.2.1). The A429 rmware de signate s which channe ls will ope rate as re ce ive
channe ls and which will ope rate as transmit channe ls, base d on the value s
e nte re d in offse ts 800h and 801h. The re ce ive channe ls are always assigne d to
the lowe r channe l numbe rs.
6. Re ad the Xilinx Download Status Re giste r (offse t 812h). A value of C0DEh (or
0x86B for the V2) indicate s download was succe ssful.
7. Re ad the BIT Status re giste r (offse t 83Bh) and wait for the value to e qual 0000h,
indicating that the powe r-up te sts have comple te d.
8. Re ad the BIT total e rror count (offse t 83Ch).
Note: The value will be nonze ro if e rrors we re de te cte d. If a
nonze ro value occurs, contact SBS Te chnologie s.
Table 3.2.1: ENCDEC Conguration Register
After you complete this procedure, the A429 is in BIT mode awaiting a com-
mand. Either select BIT tests to be performed or initialize the board for ARINC
429 operations.
16-bit Register Offset (Hex) Register Description
800 Number of Receivers
801 Number of Transmitters
802 ENCDEC Status
803 Total Number of Channels
A429 Software Download Instructions 3-9
3.2.8 BIT Test Registers
Table 3.2.2 contains a summary of the registers used to perform BIT tests.
Table 3.2.2: BIT Test Operational Registers
Perf orming All
BIT Test s
Complete the following steps to perform all BIT tests:
1. Write 0000h to the BIT Total Error Count Re giste r (offse t 83Ch).
2. Write FFFFh to the Se le cte d Te st Re giste r (offse t 83Dh).
3. Write 0002h to the BIT Control Re giste r (offse t 83Ah).
4. Re ad the BIT Control Re giste r (offse t 83Ah) and wait for a te st comple te
indication (value =00000h).
5. Re ad the BIT Total Error Count Re giste r (offse t 83Ch).
Note: The value will be nonze ro if e rrors we re de te cte d. If a
nonze ro value occurs, contact SBS Te chnologie s.
3.2.9 Module Operation
Transmit ,
Receive,
Monit or, and
Int errupt
f unct ions
The Transmit, Receive, Monitor, and Interrupt functions of this interface are
executed from application program mode. To enter this mode from the self-test
mode, perform the following operations:
1. Write 0000 to control re giste r offse t 0840h. Upon prope r startup of the
application rmware , this re giste r will be loade d with the rmware ve rsion
numbe r.
2. Write 000D to the BIT Control re giste r (offse t 83Ah).
3. Go into a software loop, che cking the re giste r at offse t 0840h for a nonze ro
value . Exit the loop whe n the re giste r contains a nonze ro value .
4. Load data structure s and control re giste rs into A429 me mory.
16-bit Register Offset (Hex) Register Description
83A BIT Control Register
83B BIT Status Register
83C BIT Total Error Count
83D Selected Test Register
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Note: Firmware control re giste rs IQPTR1 and IQPTR2 must be
de ne d for prope r rmware ope ration. Additionally, if re ce iv-
e rs are de ne d, you must se t CMIPTR and GMIPTR control
re giste rs.
5. Se t the CMD control re giste r (offse t 0880h) to 0001. This e nable s ARINC 429 bus
proce ssing.
6. Ve rify that the RESP control re giste r (offse t 0881h) is incre me nting. This
e nsure s that the rmware has succe ssfully pe rforme d startup and is curre ntly
proce ssing ARINC 429 data.
Note: If CMD re giste r (offse t 880h) e quals 0 and RESP con-
trol re giste r (offse t 881h) e quals FFFFh, Firmware Startup
faile d, data structure s we re not loade d corre ctly.
Note: You can re turn to BIT Mode afte r e nte ring module op-
e ration mode . Simply stop I/O (se t CMD=0 (offse t 880h)) and
cle ar the BIT control re giste r (offse t 83Ah) e qual to 0 . This
place s the rmware in BIT mode once again.
After completed, the A429 operates as described in Chapter 2: Control Regis-
ters.
External Triggers 3-11
3.3 Ext ernal Triggers
3.3.1 External Trigger Control Word (XTCWD)
Note: To use e xte rnal trigge rs on all sixte e n channe ls of the
board, you must de ne the parame te rs de scribe d in this se c-
tion for both de vice s of the A429 PC16 and A429 V2.
Table 3.3.1: Trigger Description
You can congure three triggering functions: interrupt host, synchronize trans-
mitters, trigger monitoring, and external clock. An external trigger control
word, XTCWD (offset 8B0h), governs the functionality of the external triggers.
The denitions appear below.
Bit 0 - Enable/
Disable Ext ernal
Triggers
To enable external triggers, set this bit to 1. To disable external triggers, set
this bit to 0'.
Bit 1 - Trigger 1
Select
To set external trigger 1 to trigger synchronous transmission, set this bit to 1.
To set external trigger 1 to generate an interrupt to the host, set this bit to 0.
Bit 1 - Trigger 5
Select (f or PC-16
and V2)
To set external trigger 5 to trigger synchronous transmission for Device 2, set
this bit to 1. To set external trigger 1 to generate an interrupt to the host, set
this bit to 0.
Card Type External
Triggers
Connector
External Triggers
configured as
trigger inputs
Triggers Reserved
for future
development
PC8
8 Bi-dire ctional P2 1 thru 3 4 thru 8
PC16
8 Bi-dire ctional J2 1 thru 3 for De vice 1/
5 thru 7 for De vice 2
4 and 8
V2
8 Bi-dire ctional J1 1 thru 3 for De vice 1/
5 thru 7 for De vice 2*
4 and 8
*V2 can have 6 triggers for a single device or 3 triggers for a dual device.
cPCI/PCI
6 1 thru 3 4 thru 6
PC104
2 Bi-dire ctional J3 1 thru 2
PCMCIA
2 Bi-dire ctional DB26 1 thru 2
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Bit 2 - Trigger 2
Select
To set external trigger 2 to trigger sequential monitoring, set this bit to 1.
To set external trigger 2 to generate an interrupt to the host, set this bit to 0.
Bit 2 - Trigger 6
Select
(PC-16 and V2)
To set external trigger 6 to trigger sequential monitoring for Device 2, set this
bit to 1. To set external trigger 2 to generate an interrupt to the host, set this
bit to 0.
Note: The following bit de scriptions apply to Exte rnal
Trigge rs for Exte rnal Clock Ope ration within XTCWD.
Bit 13 - Trigger 1
Select f or
Ext ernal Clock
To set external trigger 1, enabling trigger IN to start External Clock, set this bit
to 1. To disable trigger IN, set this bit to 0.
Bit 13 - Trigger 5
Select f or
Ext ernal Clock
(PC16 and V2)
To set external trigger 5, enabling trigger IN to start External Clock for Device
2, set this bit to 1. To disable trigger IN, set this bit to 0.
Bit 14 - Trigger 3
Select f or
Operat ion of
Ext ernal Clock
To set external trigger 3 as a MASTER, set this bit to 1.
To set external trigger 3 as a SLAVE, set this bit to 0.
Bit 14 - Trigger 7
Select f or
Operat ion of
Ext ernal Clock
(PC16 and V2)
To set external trigger 7 as a MASTER for Device 2, set this bit to 1.
To set external trigger 7 as a SLAVE for Device 2, set this bit to 0.
Bit 15 - Enable/
Disable Ext ernal
Clock
To enable external clock, set this bit to 1.
To disable external clock, set this bit to 0.
PC-8 and PC-16 Note: Trigge rs 3 and 7 are pre -congure d to
ge ne rate an inte rrupt to the host. The re fore , if you use e x-
te rnal trigge rs 1-3 and 5-7 (De vice 2 of PC-16), all thre e inte r-
rupt functions can be imple me nte d simultane ously. The
following paragraphs de scribe e ach of the se functions.
External Triggers 3-13
3.3.2 Interrupt Host
This function causes an interrupt to be generated to the host if external triggers
are enabled and an external trigger event occurs. An interrupt code specifying
which trigger event occurred as well as a 48-bit time stamp are stored in the in-
terrupt queue (see Section 3.5: Interrupt Management). Transmit data structures
must be properly dened before you can use this function.
When using t he
PC-8
To use external triggers 1 or 2 for this function, set bit 0 of XTCWD to 1 and
bit 1 or 2 of XTCWD to 0. To use external trigger 3, set bit 0 of XTCWD to
1.
When using t he
PC-16
For Device 1, to use external triggers 1 or 2 for this function, set bit 0 of
XTCWD to 1 and bit 1 or 2 of XTCWD to 0. To use external trigger 3, set
bit 0 of XTCWD to 1.
For Device 2, to use external triggers 5 or 6 for this function, set bit 0 of
XTCWD to 1 and bit 1 or 2 of XTCWD to 0. To use external trigger 7, set
bit 0 of XTCWD to 1.
When using t he
PC 104
To use this function, set bit 0 of XTCWD to 1 and bit 1 or 2 of XTCWD to
0.
3.3.3 Synchronize Transmitters
This function synchronizes the transmission of data words being transmitted
from multiple channels. To use this function:
1. De ne the transmit data structure s and se t bits 0 and 1 of XTCWD to 1
2. Se t bit 5 of TXWCNT to 1 for e ach word to be synchronize d.
The word will be transmitte d whe n a trigge r e ve nt occurs on e xte rnal trigge r
1 (for De vice 1, or e xte rnal trigge r 5, for De vice 2 whe n using the PC-16 or V2).
Since e ach transmitte d word has a TXWCNT word associate d with it, you can
apply this function to e ach transmitte d word on e ach channe l.
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3.3.4 Trigger Monitoring
This function triggers the global sequential monitor upon the occurrence of an
external trigger event. To use this function:
1. de ne the monitor trigge r data structure s and se t bits 0 and 2 of XTCWD to 1 .
2. Assign a value of 3h or trigger at end to TRGCW (se e Chapter 6: Bus Monitoring
Firmware Reference).
3.3.5 Trigger Events
External triggers 1 through 3 (5 through 7 for the PC-16 and V2, 1 through 2 for
the PC104) are congured as active low inputs and are arranged by priority. A
trigger event is characterized by a high to low transition on one or more trigger
lines present for at least 500 nsec.
Example 1 For example, external trigger 1 has the highest priority and external trigger 3 has
lowest priority. Therefore, if all external trigger events (1-3) occurred simulta-
neously, external trigger 1 would be serviced rst, external trigger 2 would be
serviced about 20 sec later, and external trigger 3 would be serviced about 20
sec after service of external trigger 2. Times given here are dependent on de-
vice conguration (receive to transmit ratio), A429 system setup, and bus load-
ing. Therefore, the times given are estimated maximums and will generally be
signicantly less.
Example 2 Another example would be if external trigger 1 and external trigger 2 occurred
simultaneously and before external trigger 2 could be serviced, external trigger
1 occurred again. In this situation, the rmware would service external trigger
1 twice before servicing trigger 2.
3.3.6 Controlling Operations
To perform ARINC 429 external triggering, complete the following steps:
1. Se le ct the e xte rnal trigge r conguration by se tting bit 1, bit 2, or both of
XTCWD to 1 .
2. Se t bit 0 of XTCWD to 1 to e nable e xte rnal trigge rs.
External Clock 3-15
Note: If ARINC 429 bus proce ssing is in progre ss (i.e ., CMD is
nonze ro and RESP is incre me nting) and a ne w e xte rnal trig-
ge r conguration is de sire d, disable e xte rnal trigge rs by
se tting bit 0 of XTCWD to 0 , wait 20 se c for the rmware to
cle ar any e xisting e xte rnal trigge r e ve nts, and the n re -e nable
e xte rnal trigge rs with the ne w conguration.
3. Se t up any data structure s associate d with e xte rnal trigge rs, including
transmit data structure s, monitor trigge r structure s, inte rrupt que ue s, and
se que ntial monitor pointe rs.
4. Start ARINC 429 bus proce ssing by writing a nonze ro value to CMD.
3.4 Ext ernal Clock
The A429 board provides the capability of an external clock for the PC8, PC16,
PCI, cPCI, and V2. If using external clock you must enable bit 15 of XTCWD.
The A429 has the capability of providing an external clock out (MASTER) or
operate as an external clock in (SLAVE). The external clock is transmitter/re-
ceived on External Trigger 3, External Trigger 7 or both for the PC16 and V2.
If using the feature to start External Clock on a trigger IN, use External Trigger
1, External Trigger 5 or both for the PC16 and V2. The timer will not start unit
External Trigger
You should dene both the timer values and the external clock conguration
prior to setting CMD to 1.
Note: The e xte rnal clock can be starte d and stoppe d at any
time during IO proce ssing. To disable the e xte rnal clock, se t
Bit 15 to 1 and Bit 0 to 0 of XTCWD. Wait 20 se c for the
rmware to cle ar and e xisting e xte rnal trigge r e ve nts and
the n re -e nable the e xte rnal clock by se tting appropriate bits
in XTCWD.
Cross Reference: Re fe r to the Exte rnal Trigge r Pinouts in
Chapte r 4 of the Ge tting Starte d that you re ce ive d with your
board.
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3.5 Int errupt Management
The A429 offers extensive interrupt capabilities for notifying the host processor
of transmit, receive, monitoring, and system events that have occurred on the
ARINC 429 bus. Interrupts may be enabled via the following structures:
Filter Tables
MCWRD
RCVCW
Transmit Command Block Types
External Triggers
To store detected or generated events for the host system interrupt service rou-
tines, the A429 utilizes a doubled buffered queue structure. The queue address-
es and event counters for this data structure are managed by control registers.
The host system reads these control registers during an interrupt service proce-
dure to determine which interrupt queue is currently active and how many inter-
rupt events are stored in the active queue.
Cross Reference: Se e Chapter 2: Control Registers.
In using the PC-16 or the V2, the host may read CSR1 and CSR2 and examine
bit 7 of each register to determine the origin of an interrupt. If bit 7 of CSR1 is
set to 1, the interrupt was generated by Device 1; if bit 7 of CSR2 is set to 1,
the interrupt was generated by Device 2.
Note: The status of bit 7 of CSR1 is also copie d to bit 6 of CSR2.
The re fore , a single re ad of CSR2, e xamining bits 6 and 7, can
also be use d to de te rmine the origin of an inte rrupt.
For all other ARINC cards, the host system may handle interrupt events in one
of two ways: 1) by polling the interrupt control registers via host software with
the hardware interrupts disabled, 2) by using an interrupt service routine (ISR)
written for the specic device with the hardware interrupts enabled.
Note: SBS has de ve lope d many ISR routine s for PC and UNIX
syste ms which are available upon re que st to A429 custome rs.
Interrupt Management 3-17
The A429 lls the interrupt queue buffers and updates interrupt control registers
regardless of which method is used. If the host system does not require hard-
ware interrupts, the interrupt enable bit in the CSR control register (offset
0000h) should be set to 0 at startup.
The interrupt queue data structures and control registers allow the host system
to easily determine what type of transmit, receive, monitor, or system event oc-
curred. This subsection details the types of A429 interrupts and the data struc-
tures and control registers used by interrupt service procedures to manage
interrupts.
3.5.1 Interrupt Types
There are interrupts associated with each major A429 function (transmit and re-
ceive operation, and monitoring) and interrupts for general system functions.
Table 3.5.1 details the various A429 interrupt conditions. The Code column
lists the numbers assigned to each interrupt condition. Each entry in an interrupt
queue buffer consists of four words, the rst word representing the code type.
The host system uses this code to determine how to handle each interrupt.
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Table 3.5.1: A429 Interrupt Types
Type Code (hex) Description
Transmit Operation
End of
Command
Block
0001 This interrupt is generated if the end of a command has been
reached. Set bit 14 of a command block type word to 1 to en-
able this interrupt.
Receive Operation
Error
Detected
0003 This interrupt is generated if bit 2 of the receive interrupt con-
trol word for a specific channel is set to 1, and the received
word to the respective channel has errors when it is received.
SDI/Label
Word
Detected
0004 This interrupt is generated if bit 1 of the Global Filter Table for
a specific RT address and subaddress is set to 1, and the
command word to the respective RT is received. This function
is extremely useful for receive simulation and monitoring in
determining when important words have been received on the
ARINC 429 bus.
Monitoring
Global Sequential
Monitor Buffer Swap
0002 This interrupt is generated if bit 3 of GMCWRD is 1 and a
monitor buffer swap occurs. A monitor buffer swap can occur
during normal bus monitoring or via a forced buffer swap (set
bit 2 of GMCWRD to 1 to force a buffer swap). The firm-
ware stores ARINC 429 data, including data with errors, ac-
cording to Filter Table programming. This interrupt is
frequently used by the host system to read one monitor buffer
while the other buffer is filling with data.
Global Sequential
Monitor Full
0005 This interrupt is generated if bit 0 of MCWRD for a monitor
buffer is set to 1 and the monitor buffer becomes full.
Channel
Sequential
Monitor Full
0006 This interrupt is generated if bit 0 of MCWRD for a monitor
buffer is set to 1 and the monitor buffer becomes full.
Channel
Sequential
Monitor Buffer Swap
0009 This interrupt is generated if bit 7 of RCVCW is set to 1 for
a specific receive channel and a monitor swap occurs. A mon-
itor buffer swap can occur during normal bus monitoring or via
a forced buffer swap (set bit 2 of GMCWRD to 1 to force a
buffer swap). The firmware stores ARINC 429 data, including
data with errors, according to Filter Table programming. This
interrupt is frequently used by the host system to read one mon-
itor buffer while the other buffer is filling with data.
External Trigger
External
Trigger
Event
Ext Trig ID + 0Ah This interrupt indicates that an external trigger event has oc-
curred. Set Bit 0 of XTCWD and generate an external trigger
event to generate this interrupt.
General System
System Time
Update
0007 This interrupt indicates that the system time has been updated
as requested by the user. Set CCW to 1h to update the time and
generate this interrupt.
Interrupt
Overflow
0008 This interrupt indicates that the interrupt queue has over-
flowed. The host system neglected to service the first interrupt
of the queue before the entire queue filled with data.
Current
Value Swap
0B This interrupt is generated if bit 3 of RCVCW is set to 1 for a
specific receiver and a current value swap occurs.
Interrupt Management 3-19
3.5.2 Interrupt Queue Data Structures and Control Registers
The A429 manages interrupts using a double buffered queue and counter control
registers. When an interrupt event occurs, the A429 stores four words in the cur-
rent interrupt queue buffer. These four words consist of an interrupt code and
three information words. The host reads these words to determine what type of
interrupt occurred and obtains related information such as the ARINC 429 label
words, pointer values, and time values associated with the interrupt event.
Figure 3.5.1 illustrates the interrupt queue buffers and control registers.
Figure 3.5.1: A429 Interrupt Queue Buffers and Control Registers
3.5.3 Minimum Programming Requirements for Interrupt Queue
The host software must program two interrupt queue buffers. These buffers
must be identical in length, must be located in memory between 0B00h and
FFFFh, and must hold a minimum of four interrupt entries each. A pointer
(IQPTR1 and IQPTR2) must be programmed for each buffer to indicate the
starting address. Each buffer must also have a counter (IQCNT1 and IQCNT2)
to count interrupt entries as they occur. Each entry will consist of one to three
words of valid data.
IQRSP
IQPTR1
IQPTR2
IQCNT1
IQCNT2
IQNUM
ENTRY 1 *
ENTRY 2
|
|
ENTRY 1 *
ENTRY2
|
|
IQNUM
IQNUM
INTERRUPT CODE
DATA 1
DATA 2
DATA 3
* ENTRY DETAIL
SEE TEXT DISCUSSION
Buffer 1
Buffer 2
3-20 Device Management Firmware Reference
Doc: a429 re f 03.fm, ve r 2.0, 1 Jun 1999, 09:36
The host places the starting address of the rst queue buffer into IQPTR1, the
address of the second queue buffer into IQPTR2, and the length of the queue
buffers into control register IQNUM. The value in IQNUM determines the
number of entries in each buffer; each entry contains one to four words. For ex-
ample, enter a value of 10 (000Ah) into IQNUM for a 40-word queue. Ten
interrupt entries may be stored in a queue this size. The A429 rmware defaults
IQNUM to 4 at startup.
When an interrupt event occurs, the rmware sets the interrupt pending bit of
the CSR control register (bit 7 of offset 0000h). If bit 3 of the CSR is set to 1
the A429 generates a hardware interrupt. The host ISR writes the value
FFFFh to IQRSP when starting the service routine and writes 0001h to
IQRSP when the routine is complete. Control registers IQCNT1 and IQCNT2
provide an event count for each buffer (there are four words per event).
After startup, the rmware writes interrupt events to the buffer indicated by
IQPTR1. When an interrupt occurs, the host ISR sets IQRSP to FFFFh. The
host must then wait two microseconds for the rmware to nish processing any par-
tially completed asynchronous interrupt events (see note below). If there is a
partial interrupt pending, the rmware nishes processing, places the event in-
formation in the buffer indicated by IQPTR1, and increments IQCNT1. If a new
interrupt occurs during the host service (after FFFFh is written to IQRSP), the
new interrupt event information is placed in the buffer indicated by IQPTR2.
After servicing the interrupts, the host ISR writes a 1 to IQRSP and the rm-
ware swaps the values from IQPTR2 to IQPTR1 and from IQCNT2 to IQCNT1.
If an interrupt event was placed in the buffer indicated by IQPTR2, the rmware
generates a new hardware interrupt.
Note: If the host has programme d the A429 for inte rrupt
e ve nts that are known to be synchronous, and the se e ve nts
occur more than 10 s apart, the host ISR doe s not ne e d to
wait two s be fore se rvicing the inte rrupts.
When the host services an interrupt, it reads the code word from the interrupt
entry to determine the interrupt type. Some interrupt types consist of only this
code word and others also contain data words. Table 3.5.2 denes each of the
code words and their associated data words. Some words are undened (their
values are unknown) and should be ignored by the host software.
Interrupt Management 3-21
Table 3.5.2: Interrupt Codes
Figure 3.5.2: A429 Received Label/ Channel
Note: For De vice 2 in a PC16, the Channe l ID value is an offse t
from 9; i.e ., a Channe l ID of 1 indicate s that the labe l that the
labe l was re ce ive d on Channe l 10.
Type Word 1 - Code Word 2 Word 3 Word 4
End of Command 1 channel number current command
pointer
current frame
Global Sequential
Monitor Swap
2 monitor base
last pointer
channel number undefined
Error Detected 3 channel with
error
undefined undefined
Label Word
Detected
4 received label &
channel number
16 middle bits of
system time
16 lower bits of
system time
Global Monitor
Full
5 monitor base
pointer
undefined undefined
Channel Monitor
Full
6 monitor base
pointer
undefined undefined
System Time
Update
7 undefined undefined undefined
Interrupt
Overflow
8 undefined undefined undefined
Channel Monitor
Swap
9 monitor base
last pointer
channel number undefined
External
Trigger
Event
External Trigger
ID + Ah
(Figure 3.5.3)
16 lower bits of
system time
16 middle bits of
system time
16 upper bits of
system time
Current
Value Swap
B CVBPTR CTBPTR channel number
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Channel ID SDI / Label Reserved
3-22 Device Management Firmware Reference
Doc: a429 re f 03.fm, ve r 2.0, 1 Jun 1999, 09:36
Figure 3.5.3: A429 External Trigger Event
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Trigger ID
Code = 0Ah
External trigger 1/
External trigger 2/
External trigger 3/
For PC-16/V2
External trigger 5
External trigger 6
External trigger 7
Interrupt Management 3-23
3.5.4 Hardware Interrupt Service Procedure
The recommended procedures for servicing A429 hardware interrupts appear in
Table 3.5.3.
Table 3.5.3: Hardware Interrupt Service Procedures
Step
Number
Description
1 Host receives A429 hardware interrupt and starts ISR.
2
Note: This ste p is only applicable for the PC-16 and V2
Host ISR reads CSR1 (offset 0000h) and CSR2 (offset 0008h) and examines bit 7
of each register to determine the orgin of the interrupt. If bit 7 of CSR1 is set to 1,
the interrupt was generated by Device 1; if bit 7 of CSR2 is set to 1, the interrupt
was generated by Device 2.
Note: A single re ad of CSR2, e xamining bits 6 and 7, can also be use d to de -
te rmine the orgin of the inte rrupt.
Perform steps 3-10 on the device that generated the interrupt.
3 Host ISR reads IQRSP in a loop until IQRSP is equal to "0".
4 Host ISR writes "FFFF" to IQRSP.
5 Host ISR waits 2 microseconds for the firmware to swap values between IQPTRs
and IQCNTs.
6 Host ISR reads IQCNT1 to determine the number of interrupt events to process.
7 Host ISR reads IQPTR1 to get the address of the interrupt queue buffer to process.
The host reads each interrupt event, beginning at the address indicated by IQPTR1.
The host reads each interrupt event in the buffer, deciphering the code word to de-
termine if data words are present. The host ISR may either process the interrupt
data at this point or after execution has returned to the host software.
8 Clear the interrupt pending bit.
Note: For the PC-16 and V2, the host ISR se ts bit 7 of CSR1 or bit 6 of CSR2
to 1 to cle ar an inte rrupt ge ne rate d by De vice 1. Host ISR se ts bit 7 of CSR2
to 1 to cle ar an inte rrupt ge ne rate d by De vice 2Host ISR se ts bit 7 of CSR1
or bit 6 of CSR2 to 1 to cle ar an inte rrupt ge ne rate d by De vice 1. Host ISR
se ts bit 7 of CSR2 to 1 to cle ar an inte rrupt ge ne rate d by De vice 2.
9 Host ISR writes 0001h to IQRSP.
3-24 Device Management Firmware Reference
Doc: a429 re f 03.fm, ve r 2.0, 1 Jun 1999, 09:36
3.5.5 Software Polling Interrupt Service Procedure
The recommended procedures for software polling of A429 interrupt events
appear in Table 3.5.4.
Table 3.5.4: Software Polling Interrupt Service Procedure
Step
Number
Description
1 Host polls (reads) bit 7 (bit 4 for V2) of the CSR until it detects a value of 1.
A 1 indicates an interrupt event has occurred on the A429.
Note: For the PC-16, host polls (re ads) bit 7 of CSR1 (offse t 0000h) and
CSR2 (offse t 0008h) until it de te cts a value of 1 . (NOTE: The host can
also poll bit 6 and bit 7 of CSR2 to de te ct an inte rrupt on De vice 1 or De -
vice 2, re spe ctive ly.) A 1 indicate s an inte rrupt e ve nt has occurre d on
the A429 PC-16. Pe rform ste ps 2-9 on the de vice that ge ne rate d the
inte rrupt.
2 Host ISR reads IQRSP in a loop until IQRSP is equal to "0".
3 Host ISR writes FFFFh IQRSP.
4 Host ISR waits 2 microseconds for the firmware to swap values between IQP-
TRs and IQCNTs.
5 Host ISR reads IQCNT1 to determine the number of interrupt events to process.
6 Host ISR reads IQPTR1 to get the address of the interrupt queue buffer to pro-
cess.
7 The host reads each interrupt event, beginning at the address indicated by
IQPTR1. The host reads each interrupt event in the buffer, deciphering the code
word to determine if data words are present. The host ISR may either process
the interrupt data at this point or after execution has returned to the host soft-
ware.
8 Host ISR writes a 1 to bit 7 (bit 4 for V2) of the CSR control register to clear
the interrupt request.
Note: For the PC-16,cle ar the inte rrupt re que st. Host ISR se ts bit 7 of
CSR1 or bit 6 of CSR2 to 1 to cle ar an inte rrupt ge ne rate d by De vice 1.
Host ISR se ts bit 7 of CSR2 to 1 to cle ar an inte rrupt ge ne rate d by De -
vice 2.
9 Host ISR writes 0001h to IQRSP.
4-1
Note: The parame te rs and data structure s de scribe d in this
chapte r must be de ne d for both de vice s of the A429 PC16
and A429 V2 in orde r to acce ss all sixte e n channe ls of the
board.
The following sections describe the A429 transmit operations:
Control Block Structure
Periodic Command Block Structure
Aperiodic Command Block Structure
Channel Wrap Operations
Double-Buffer Transmit Block Feature
Transmit operations for each transmit channel in the A429 are governed by a
single data structure consisting of a linked list of command blocks. A separate
data structure must be dened for each channel. Command blocks in the linked
list contain encoded information for the transmission of ARINC messages. This
linked list can be loaded at any location in memory range 0B00h to FFFFh
(memory Window 1 for the PC8 and PC16 or memory Window 1, Window 2 or
both for the PC104). Each periodic command block in the linked list consists of
ten words, containing the following information:
A type word designating the type of command block: either message
transmission type or minor frame type
Two schedule words (if the command block is a minor frame type, these
words will contain the minor frame time)
A transmit buffer length
A pointer to a transmit data buffer which contains the words to be
transmitted
Three words for controlling start and repetition rates
A pointer to the next block in the chain
To perform transmit operations on the A429, you rst construct a linked-list data
structure of command blocks and load this structure into A429 memory. Then
4: Tr ansmi t t er Fi r mw ar e Ref er ence
4-2 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
you program register CBIPTR with the address of the rst word of the rst com-
mand block. When the rmware detects a nonzero value in CBIPTR, it uses this
value as a pointer to the rst command block of the linked list. It then sets
CBIPTR to 0 and begins processing the command block. (There may be up
to a 20 s delay from the time you write the value to CBIPTR to when the rst
command block is processed. You can monitor CBIPTR to determine when pro-
cessing begins.)
The command block data structure does not need to be dened in A429 memory
at startup.
Also available in the A429 are two types of aperoidic transmit operations:
High Priority
Low Priority
4.1 Cont rol Block St ruct ure
Associated with each transmitter is a control block containing 32 words which
govern command block processing. Figure 4.1.1 illustrates the data structure
for the control block.
Control Block Structure 4-3
Figure 4.1.1: Transmit Control Block Structure
7 6 5 4 3 2 1 0
Transmit Speed
CHTYPE (RW)
CMDBCW (RW)
CBIPTR (RW)
CBCPTR (RO)
CBLPTR (RO)
MNFCNT (RW)
MNCNT (RO)
MJFCNT (RW)
MJCNT (RO)
CBCTMP(RO)
TXPAM(RW)
TXNAM(RW)
TXNAT(RW)
LFRAME (RO)
MFRAME (RO)
HFRAME (RO)
CWPTR
PBRX
BTWCNT (RO)
CHLED (RES)
00
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
1 = 100KHz
0 = 12.5KHz
HALT
Transmit Control Block Structure
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
06
07
08
09
0A
0B
0C
0D
0E
1F
10
11
12
01
02
03
04
05
1 = Channel Wrap Enabled
0 = Channel Wrap Disabled
1 = Channel Wrap Error Injection Enabled
0 = Channel Wrap Error Injection Disabled
Label 0
Label 255
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1 = Playback Enabled
0 = Playback Disabled
1 = Transmit Mode 24 bit
0 = Transmit Mode 32 bit
RESERVED
TXWCNT 0
LOPMASK 0
HOPMASK 0
LAMSK 0
HMASK 0

TXWCNT 255
LOPMASK 255
HOPMASK 255
LAMSK 255
HMASK 255
4-4 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.1.1 Channel Type (CHTYPE)
This word species the type of channel; it contains FFFFh if it has been desig-
nated as a transmit channel and 0000h if it has been designated as a receive
channel. This value is provided for informational purposes only. If you modify
the value contained in this word, it will not affect module operation.
Notes: The A429 PC8, cPCI, and PCI can simulate up to e ight ARINC
429 channe ls.
Each of the two de vice s on the A429 PC-16 or the A429-V2 can
simulate up to e ight ARINC 429 channe ls.
The A429 PC104 can simulate up to four ARINC 429 channe ls.
Each channe l is congure d for e ithe r transmit or re ce ive ope ration
base d on the value s e nte re d in 800h and 801h during the Module
Startup proce dure (Se e Section 3.1: Module Startup/ Test).
4.1.2 Command Block Control Word (CMDBCW)
This word governs transmit and command block operations for the specic
channel through the following three bits:
Bit 0 - Halt To halt processing for the associated command structure, set this bit to 1. The
rmware nishes processing the current command block, halts processing, and
then clears this bit.
Bit 1 - Transmit
Speed
For 100 KHz transmission, set this bit to 1.
For 12.5 KHz transmission, set this bit to 0.
Bit 3 - Channel
Wrap
To enable Channel Wrap processing set this bit to 1
For normal operation set bit to 0.
Bit 4 - Channel
Wrap Error
Inject ion
To enable Channel Wrap Error Injection globally set this bit to a 1.
To disable Channel Wrap Error Injection globally set this bit to a 0.
Control Block Structure 4-5
4.1.3 Command Block Initial Pointer (CBIPTR)
This location is continuously monitored by the A429's rmware. When CBIP-
TR is non- zero, the rmware sets this pointer to zero and executes a chain of
command blocks beginning at the offset dened in CBIPTR.
4.1.4 Command Block Current Pointer (CBCPTR)
This location points to the current location in the command block structure.
This pointer is zero until processing of a command block structure begins.
4.1.5 Command Block Last Pointer (CBLPTR)
This location, updated when a halt occurs, indicates the last command block that
was executed before the halt occurred. A halt can be generated in one of three
ways:
By setting bit 0 of CMDBCW to 1.
By setting the link pointer, LNKPTR, of a command block to 0.
By completing the specied number of major frames.
4.1.6 Minor Frame Count (MNFCNT)
This value determines the number of minor frames to execute for each major
frame.
4.1.7 Minor Count (MNCNT)
This value indicates the current minor frame being processed. This value is up-
dated by the A429 rmware.
4.1.8 Major Frame Count (MJFCNT)
This value determines the number of major frames to execute before halting
command block processing. For continuous operation, set MJFCNT to 0.
4-6 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.1.9 Major Count (MJCNT)
This value indicates the current major frame being processed. This value is up-
dated by the A429 rmware.
4.1.10 Temporary Command Block Current Pointer (CBCTMP)
This register is used for aperiodic block processing. This value is only used by
the A429 rmware.
4.1.11 High Frame (HFRAME)
This register contains the most signicant 16 bits of the 48-bit time at which the
last minor frame type command was processed. This value is used by the A429
rmware to keep track of minor frame times.
4.1.12 Middle Frame (MFRAME)
This register contains the middle 16 bits of the 48-bit time at which the last mi-
nor frame type command was processed. This value is used by the A429 rm-
ware to keep track of minor frame times.
4.1.13 Low Frame (LFRAME)
This register contains the least signicant 16 bits of the 48-bit time at which the
last minor frame type command was processed. This value is used by the A429
rmware to keep track of minor frame times.
Control Block Structure 4-7
4.1.14 Channel Wrap Pointer (CWPTR)
Will consist of a (3 x 256) buffer pointed to by CWPTR. CWPTR will consist
of a transmit control word, Low mask, and High mask for each of the 255 pos-
sible labels. You will have to set these values for the appropriate labels. The
transmit control word is used for error injection. Possible errors are:
Parity
Add a bit
Subtract a bit.
Low and High mask values will be exclusively ored (XOR) with the data to be
channel wrapped.
4.1.15 Bus Trafc Word Count (BTWCNT)
The value in this register increments for each word transmitted. A word count
is provided for each channel.
4.1.16 CHLED
This value is used by the A429 rmware to indicate bus activity:
0000 = no bus activity
00FF = channel is active
FF00 = channel is transmitting errors
4-8 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.2 Periodic Command Block St ruct ure
You must specify A429 transmission commands in a series of linked-list com-
mand blocks. The length of the command block linked-list is limited only by the
available A429 memory. Figure 4.2.1 illustrates the data structure for the com-
mand block linked-list chains.
Figure 4.2.1: Command Block Data Structure
Transmit Type
SCLTME (RW)
SCHTME (RW)
TBCNT (RW)
TDBPTR (RW)
WRDCNT (RO)
START (RW)
REPRTE (RW)
REPCNT (RES)
Reserved
Reserved
LNKPTR (RW)
TXWCNT 1
DATA 1 Lower 16
DATA 1 Upper 16
TXWCNT 2
|
|
TXWCNT n
DATA n Lower 16
DATA n Upper 16
Minor Frame Type
MFLTME (RW)
MFHTME (RW)
Reserved
Reserved
Reserved
Reserved
TXFLAG
TXAPTR
TXBPTR
TXCNT
LNKPTR (RW)
CBIPTR
CBCPTR
KEY:
RW = Read/write
RO = Read only
RES = Reserved for firmware only
TBCNT
*
3
Refer to the section on the
Double-Buffer Transmit
feature for more information
on these four registers.
Periodic Command Block Structure 4-9
4.2.1 Minor Frame Type/ Transmit Type
This location holds a code describing the type of operation and how it is to be
performed. The available codes are shown in Table 4.2.1.
Table 4.2.1: Type Codes
Bit 15 - NO-OP Set this bit to 1 to cause the command to be skipped.
Set this bit to 0 to process the command.
Bit 14 - Int errupt
at End of
Command
To generate an interrupt when the command is completed, set this bit to 1.
To generate no interrupts upon completion of the command, set this bit to 0.
Bit 13 - TX Block To transmit a single word each time the command block is processed, set this bit
to 1. Each time the command block is processed the next data word in the
transmit buffer is sent. To transmit the entire data buffer each time the command
block is processed set this bit to 0.
Cross Reference: Re fe r to GFLAG of Chapter 2: Control Regis-
ters.
4.2.2 Minor Frame High Time (MFHTME) - R/ W
This register is associated with the minor frame type command and contains the
upper 16 bits of the time, in microseconds, allotted for a minor frame. When the
rmware encounters another minor frame, it checks MFHTME and MFLTME
to determine when to start processing the next minor frame.
4.2.3 Minor Frame Low Time (MFLTME) - R/ W
This register is associated with the minor frame type command and contains the
lower 16 bits of the time, in microseconds, allotted for a minor frame. See de-
scription of MFHTME.
Operation
Control
(Bit 15)
Control
(Bit 14)
TX Block
(Bit 13)
Control
(Bit 12)
Type Code
(Bit 0)
Minor Frame NO-OP Interrupt at end
of command
N/A N/A
0
Transmit NO-OP
Interrupt at end
of command
1 = Single
0 = Block
One Shot TX-Will set
Bit 15 after TX block
has occurred.
1
4-10 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.2.4 Schedule High Time (SCHTME) - R/ W
This register is associated with the transmit type command and contains the up-
per 16 bits of the time, in microseconds, that must expire before the transmit
command block is processed. The time is referenced from the last minor frame
type command.
4.2.5 Schedule Low Time (SCLTME) - R/ W
This register is associated with the transmit type command and contains the
lower 16 bits of the time, in microseconds, that must expire before the transmit
command block is processed. See description of SCHTME.
4.2.6 Transmit Buffer Count (TBCNT) - R/ W
This register is associated with the transmit type command and indicates the
number of data words to transmit for the associated command block. Each val-
ue to be transmitted requires three 16-bit words. The rst word is the control
word, followed by the lower 16 bits of the ARINC data word, followed by the
upper 16 bits of the ARINC data word, i.e., Transmit Buffer Length = 3 TB-
CNT.
Note: This value is in he x.
4.2.7 Transmit Data Buffer Pointer (TDBPTR) - R/ W
This value is associated with the transmit type command and points to the base
of the transmit buffer for the associated command block.
4.2.8 Word Count (WRDCNT) - RO
This register is associated with the transmit type command and points to the cur-
rent location in the transmit data buffer.
Periodic Command Block Structure 4-11
4.2.9 Start Frame (START) - R/ W
This register is associated with the transmit type command and indicates which
minor frame a transmit type command block will begin executing.
Note: Se t this value to 0 if no minor frame structure is de -
ne d (i.e ., the command structure contains no minor frame
type commands).
4.2.10 Repetition Rate (REPRTE) - R/ W
This register is associated with the transmit type command and indicates how
often to process a transmit type command block after the START condition is
met. If REPRTE=2, processing of the command block occurs every other time
the associated command block is accessed.
Note: Se t this value to 0 if no minor frame structure is de -
ne d.
4.2.11 Repetition Count (REPCNT) - RES
A429 rmware uses this value to control the repetition rate word transmission.
4.2.12 Link Pointer (LNKPTR) - R/ W
This value points to the next command block in the chain. If LNKPTR is zero,
processing of the command structure for that channel will halt.
4.2.13 Transmit Word Control (TXWCNT)
The transmit word control TXWCNT for channel wrap operation consists of a
16-bit word that will allow you to inject errors, program an inner word gap,
synchronize transmitters, and select a logical operator to be performed to the
channel wrapped data.
Note: You must be aware that data be ing channe l wrappe d is
sche dule d to the incoming re ce ive d data. The re fore pro-
gramming an inne r word gap can re sult in e rrors.
4-12 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
This is the rst word of a three-word block which denes a transmit word.
Inject errors for each word or synchronize transmitters by using the following
bits of TXWCNT:
Figure 4.2.2: Transmit Word Control Bit Diagram
Bit 0 - Parit y
Generat ion
To disable parity generation, set this bit to 1.
For normal operation, set this bit to 0.
Bit 1 - Parit y
Type
Set this bit to 1 to inject parity errors. (Even parity.)
Set this bit to 0 for normal operation. (Odd parity.)
Bit 2 - Enable
Bit Errors
To add or subtract a bit, set this bit to 1.
For normal operation, set this bit to 0.
Bit 3 - Error
Inject ion Type
To add a bit (33 bits), set this bit to 1.
To subtract a bit (31 bits), set this bit to 0.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Channel Wrap Logical Operation*
1 = Set Gap Time
0 = Default or Sustain Gap Time
Programmable Inner Word
Gap Time (0-15) Bit Times
Reserved
00 = XOR*
01 = AND*
10 = OR*
11 = FORCE*
Reserved
1 = Add a Bit (33 bits)
0 = Subtract a Bit (31 bits)
1 = Add or Subtract a Bit
0 = Normal Operation
1 = Even Parity (Parity Errors)
0 = Odd Parity (Normal Operation)
1 = Dissable Parity Generation
0 = Normal Operation
KEY:
* For Channel Wrap Operation Only
Periodic Command Block Structure 4-13
Note: Both e rror type s (33 or 31 bits) will be applie d to the
High 16 bits of the data word. If e rror type transmits 31
bits is se le cte d, the 32nd bit will not transmitte d. This
cause s the high word to shift to the right one bit (e x: Word
Se tup -- 0AAA AA80 will be transmitte d as 1555 AA80). If e r-
ror type is transmit 33 bits is se le cte d, the n 33 bits will be
will be transmitte d. This e rror type will not e ffe ct the
transmission of the data word se tup.
Bit 4 & 5 Reserved
Bit 6 & 7-
Channel Wrap
Logical
Operat ion
For XOR functions, set bits 6 and 7 to 0 (00 = XOR).
For AND functions, set bit 7 to 0 and bit 6 to 1 (01 = AND).
For OR functions, set bit 7 to 1 and bit 6 to 0 (10 = OR).
For FORCE functions, set bits 6 and 7 to 1 (11 = FORCE).
Synchronous
Transmission
If bit 5 of TXWCNT is set to 1 for a particular word, the word will not be
transmitted until schedule time, minor frame time (REPRTE and START), and
an external trigger event occurs. This feature allows synchronous transmission
of multiple transmit channels on a word-by-word basis. Transmitted words are
synchronized within 1 transmit bit time 5sec.
Cross Reference: Se e Section 3.3: External Triggers for more
information.
Bit s 6 - 9 Reserved
Bit 10 - Gap Time
Enable
To set the Gap time between words equal to the value contained in bits 11 thru
14, set this bit to 1. To sustain the Gap, set this bit to 0.
Note: The inne r word gap only has to be se t once at the
be ginning of the transmit control block. The IWGAP will
maintain throughout all pre ce ding transmission. Not se tting
an IWGAP will re sult in the de fault of 4 bit time s.
Bit s 11 - 14
Programmable
Gap Time
Set these bits to program the Gap time between words from 0 to 15 transmit bit
times (10 sec for 100Khz and 80 sec for 12.5 Khz).
Note: The Gap time can be change d at any time within the
transmit control block structure .
Bit 15 Reserved
4-14 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
A three-word transmit block consists of TXWCNT, followed by the lower 16
bits of the ARINC data word, followed by the upper 16 bits for the ARINC data
word. The transmit buffer is pointed to by TDBPTR and contains all of the
transmit blocks for the associated command block.
Cross Reference: Se e Section 3.3: External Triggers for more
information.
4.2.14 Firmware Operations
During transmit operations, the rmware decodes each block of the linked-list
program and takes the appropriate action. If a minor frame type is indicated, the
minor frame times are checked and the structure is set up for minor frame oper-
ations. If a transmit type is indicated and schedule times, start, and repetition
rates are met, the transmit buffer is transmitted. The command block structure
is processed until a halt condition occurs.
Aperiodic Command Block Structure 4-15
4.3 Aperiodic Command Block St ruct ure
4.3.1 High and Low Aperiodic Transmission
In order to transmit a high or low priority message(s) complete the following:
1. Program the priority command block pointe d to TXHPAM/TXLPAM.
2. Program the additional block(s) and place the buffe r in A429 me mory.
3. Program TDBPTR to point to the base of the transmit buffe r and e nte r the
numbe r of words to transmit in TBCNT.
4. Program TXHPAM or TXLPAM to point to the priority command block
structure .
5. If de sire d, you can have a linke d list of ape riodic command structure s by
programming LNKPTR.
Whenever there is DEAD Bus time, the rmware continuously monitors
TXHPAM or TXLPAM for a non zero value within a minor frame or transmit
block. If non-zero, TXHPAM/TXLPAM will be copied into CBCPTR and one
or more high or low priority blocks will be transmitted. In the case of a low
priority transmission, you must program TXLPAT with the time required to
execute the block(s). The rmware compares the value in TXLPAT with the
amount of DEAD Bus time at the completion of the current minor frame. If the
DEAD Bus time is greater than or equal to TXLPAT then the execution of the
command block pointed to by TXLPAM occurs. The rmware clears
TXLHPAM/TXLPAM at the start of transmission and when transmission is
complete restores CBCPTR.
Be aware of the time required to transmit the additional high or low aperiodic
blocks. Failure to do so could cause the scheduled data timing to be skewed.
Figure 4.3.1 illustrates aperiodic transmit blocks being transmitted.
4-16 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
Figure 4.3.1: High and Low Aperiodic Command Block Data Structures
Major Frame Minor Frame
TXBLK
TXBLK
Minor Frame
TXBLK
TXBLK
Periodic Transmission
TYPE
TBCNT(R/W)
TDBPTR(R/W)
WRDCNT(RO)
Reserved
Reserved
Reserved
Reserved
Reserved
LNKPTR
TXHPAM
Aperiodic High Priority Transmit Block
CBCPTR
Aperiodic Low Priority Transmit Block
TXLPAT
User defined time, time to transmit
low priority a-periodic block(s)
Next block
or Null
TXWCNT 1
Data 1 Low 16
Data 1 High 16
TXWCNT 2
|
|
TXWCNT n
Data n Low 16
Data n High 16
TYPE
TBCNT(R/W)
TDBPTR(R/W)
WRDCNT(RO)
Reserved
Reserved
Reserved
Reserved
Reserved
LNKPTR
TXLPAM
CBCPTR
Next block
or Null
TXWCNT 1
Data 1 Low 16
Data 1 High 16
TXWCNT 2
|
|
TXWCNT n
Data n Low 16
Data n High 16
Representation of a High or Low Aperiodic Transmission
Reserved
Reserved
Reserved
Reserved
Transmission of an aperiodic Transmit
Block(s) occur within a Transmit or
Minor Frame Block,whenever there is
DEAD Bus time.
Channel Wrap Operations 4-17
4.4 Channel Wrap Operat ions
The purpose of the channel wrap feature is to allow you to receive data on a
channel and immediately transmit the same data (Channel Wrapped) out a
selected transmit channel. This feature allows you to perform an operational
mask and logical mask to the channel wrapped data. The operational mask is
used to determine if the logical mask is to be applied to the channel wrap data
in. Logical operators XOR, AND, and OR, in addition to operator FORCE, can
be selected. An inner word gap or error injection (globally or per word) may also
be applied to the channel wrap data in. See Figure 4.4.1.
Figure 4.4.1: Channel Wrap Operation
4.4.1 Receiver Operation
User Level 1. Ente r the Channe l Wrap transmitte r numbe r at word offse t 08h of the e xte rnal
re ce ive data structure .
2. Se t bit 12 of the RCVCW (CW e nable d).
3. Se le ct the appropriate labe ls in the Channe l Filte r Table .
Labe ls that Channe l Wrap will be e nable d by bit 1/9 for that labe l lte r offse t.
Cross Reference: For more information re fe r to Figure 5.1.1
and Figure 5.1.2.
RX Data In TX Data Out
Operational Mask
Logical Mask
Inner Word Gap
Error Injection
(Apply one or more
operations to the Data In)
Channel Wrap Operation
4-18 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.4.2 Transmitter Operation
User Level The transmit control block will contain a two Channel Wrap control bits located
in CMDBCW, bit 3 will be used to enable/disable Channel Wrap operation. Bit
4 will be used to enable/disable error injection globally. The transmitters
CWPTR will point to a (5*256) word buffer (offset 10h of transmit control
block). CWPTR buffer will consist of a Transmit Word Control (TXWCNT),
Low Operational Mask (LOPMASK), High Operational Mask (HOPMASK),
Low Logical Mask (LMASK), and High Logical Mask (HMASK) for each la-
bel. The user will have to set up these words for each label of interest.
Cross Reference: For more information se e Figure 4.1.1.
Cross Reference: For more information se e Section 4.2.13:
Transmit Word Control (TXWCNT).
Operat ional
Mask (LOPMASK
and HOPMASK):
The operational mask is used to determine, on a per bit basis (all 32 bits are test-
ed), if the logical mask will be applied to the CW data in. If the operational mask
bit is set for the CW data in, then the logical mask will be applied to the CW
data in. If the operation mask bit is not set for the CW data in, then the logical
mask data will not be applied to the CW data in. The CW data out will maintain
its current value. Refer to Example 1 and Example 2.
Logical Mask
(LMASK and
HMASK):
If the operation mask is set for a bit (all 32 bits are tested), the logical mask will
be applied to the data in. There are four possible operators that can be selected
on a per label basis. The four possible operators are an XOR, AND, OR and
FORCE. These operators are set by bits 6 and 7 of TXWCNT. While the XOR,
AND, and OR are self explanatory, the FORCE operator is used to force the CW
data out value to the logical mask value. Refer to Example 1 and Example 2.
Channel Wrap Operations 4-19
Example 1 Logical operator = AND
Example 2 Logical operator = FORCE
Transmit t er
Channel Wrap
Operat ion Set up
1. CMDBCW bit 3 e nable s or disable s Channe l Wrap ope ration.
2. CMDBCW bit 4 e nable s or disable s Channe l Wrap e rror inje ction globally.
3. CWPTR se tup (offse t 10h of Transmit Data Structure ) points to Channe l Wrap
control table se tup (CWPTR).
4. Se tup TXWCNT, e rror inje ction, and logical ope rator.
5. Se tup ope rational and logical mask value s.
Notes:
1. Channe l Wrap will consist of a de dicate d transmitte r.
No othe r minor frame or transmit block can be se tup
2. You must be aware of the Ope rational and Logical mask
value for e ach labe l, a failure to e nte r value s for the se
words will re sult in e rrone ous Channe l Wrappe d data.
3. On an A429-PC16, De vice 1 CANNOT Channe l Wrap
to De vice 2, nor can De vice 2 Channe l Wrap to
De vice 1.
4. Pe r ARINC spe cications, the LABEL has a re ve rse d
orde r. For e xample , labe l AAh is transmitte d as
55h. Labe ls are bit swappe d prior to be ing
maske d and are pointe d to by CWPTR. The re fore , if
the labe l re ce ive d is 55h, the word will be maske d at
offse t AAh [Labe l logically Ore d with (55h x 2)].
CW Data In 1010 0111 0011 0010 1010 0001 1111 1111
Operation Mask 0111 0000 0000 0111 1111 0000 0000 0000
Logical Mask 0100 1111 0100 0010 0000 1101 0110 0001
CW Data Out 1000 0111 0011 0010 0000 0001 1111 1111
CW Data In 0010 0111 0011 0010 1010 0001 1111 1111
Operation Mask 0111 0000 0000 0111 111 0000 0000 0100
Logical Mask 1100 1111 0100 0101 0000 1101 0110 0001
CW Data Out 0100 0111 0011 0101 0000 0001 1111 1011
4-20 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
4.5 Double-Buff er Transmit Block Feat ure
This feature allows the user to quickly copy data into one or more standard
transmit data buffers during transmit block scheduling. The control logic is in
the minor frame type block: if you set the TXFLAG bit 0, then the rmware cop-
ies a block of data pointed to by TXBPTR into a block of memory pointed to by
TXAPTR. The length of the block to be copied equals the number of data words
indicated in DBCNT. Because each data word consists of three 16-bit words
(TXWCNT, Low word, and High word), the rmware multiplies DBCNT by 3
to determine the number of offsets to copy. After it completes the copy opera-
tion, the rmware clears TXFLAG bit 0 and executes the transmit block(s).
To use this feature, complete the following steps:
1. If you are copying data into more than one standard transmit data buffe r,
che ck the value s of TDBPTR and TBCNT to ve rify that the buffe rs will be in
conse cutive me mory blocks.
2. Se t TXBPTR to the starting location of the rst block you wish to copy.
3. Se t DBCNT to the numbe r of data words you wish to copy.
4. Se t TXAPTR to the location whe re you wish to copy the data block(s). TXAPTR
and TDBPTR should point to the same location.
Note: TXAPTR is the active data block, which TDBPTR acce sse s
in the standard transmit type block structure . TXBPTR is the
inactive block that you should update with ne w transmit data.
5. To be gin copying, se t bit 0 of TXFLAG.
Note: The e stimate d time associate d with a block copy is ~50
nanose conds/word. The re fore , it take s approximate ly 15 mi-
crose conds to copy 100 A429 words (e ach one consisting of
TXWCNT, Low word, and High word).
Figure 4.5.1 provides an example of the double-buffer transmit block feature. In
this example, the rmware has copied 10 data words (DBCNT = 0xA) from the
inactive data block at 6200 (that TXBPTR points to) into the active block at
6100 (that TDBPTR of block A and TXAPTR point to).
Double-Buffer Transmit Block Feature 4-21
Figure 4.5.1: Normal Block Structure (Periodic) with Example of Double-Buffer
Transmit Block Feature
Transmit Type
SCLTME (RW)
SCHTME (RW)
TBCNT (RW)
TDBPTR (RW)
WRDCNT (RO)
START (RW)
REPRTE (RW)
REPCNT (RES)
Reserved
Reserved
LNKPTR (RW)
Minor Frame Type
MFLTME (RW)
MFHTME (RW)
Reserved
Reserved
Reserved
Reserved
TXFLAG
TXAPTR
TXBPTR
DBCNT
LNKPTR (RW)
TXWCNT 1(A)
DATA Low 16(A)
DATA High 16(A)
TXWCNT 2(A)
|
|
TXWCNT 5(A)
DATA 5 Low 16(A)
DATA 5 High 16(A)
DATA High 16(B)
TXWCNT 2(B)
|
|
TXWCNT 5(B)
DATA 5 Low 16(B)
DATA 5 High 16(B)
TXWCNT 1(B)
DATA Low 16(B)
CBIPTR
CBCPTR
KEY:
RW = Read/Write
RO = Read only
RES = Reserved for firmware only
1= Copy TXBPTR Block
to TXAPTR Block
0x6100 =
0x6200 =
0xA =
0x5 =
0x6100 =
Active Block
(always pointed to by TDBPTR in
standard transmit type blocks)
Inactive Block
(the firmware copies data from
this block to the active block)
Transmit Type
SCLTME (RW)
SCHTME (RW)
TBCNT (RW)
TDBPTR (RW)
WRDCNT (RO)
START (RW)
REPRTE (RW)
REPCNT (RES)
Reserved
Reserved
LNKPTR (RW)
0x5 =
0x6105 =
Optional: Double-Buffer
Transmit Data Buffers
DBCNT
*
3
Standard
Transmit
Data Buffer A
TBCNT
*
3
Standard
Transmit
Data Buffer B
TBCNT
*
3
6100
6105
TXWCNT 1(A)
DATA Low 16(A)
DATA High 16(A)
TXWCNT 2(A)
|
|
TXWCNT 5(A)
DATA 5 Low 16(A)
DATA 5 High 16(A)
DATA High 16(B)
TXWCNT 2(B)
|
|
TXWCNT 5(B)
DATA 5 Low 16(B)
DATA 5 High 16(B)
TXWCNT 1(B)
DATA Low 16(B)
6200
DBCNT
*
3
4-22 Transmitter Firmware Reference
Doc: a429 re f 04.fm, ve r 2.0, 1 Jun 1999, 09:36
5-1
Note: In orde r to acce ss all sixte e n channe ls of the board, the
parame te rs and data structure s de scribe d in this chapte r
must be de ne d for both de vice s of the A429 PC16 and A429
V2.
This chapter reviews the key data structures required for A429 receiver opera-
tion. Table 5.0.1 denes the data storage structures.
Table 5.0.1: Data Storage Structures
Note: You se le ct e ithe r Channe l Monitoring, Se que ntial Mon-
itoring, or both ope rations at the same time .
5: Recei ve Management Fi r mw ar e Ref er ence
Data Storage Structures Description
Current Value Buffer Contains the latest received data
words for a specic channel.
They are arranged by SDI, label, or
both.
Current Time Buffer A time stamp buffer can be set up
to provide a current time stamp for
each received word.
Channel Sequential Monitor Stores data received on a specic
channel.
Global Sequential Monitor Stores data from all receive chan-
nels.
5-2 Receive Management Firmware Reference
Doc: a429 re f 05.fm, ve r 2.0, 1 Jun 1999, 09:36
5.1 Receive Dat a St ruct ure
The receive data structure is comprised of 32 words: the channel type word, the
receiver control word, the current value buffer pointer, the current time buffer
pointers, the lter pointers, bus trafc word count, and channel activity indica-
tor. Figure 5.1.1 illustrates the receive data structure. The subsections discuss
each word in greater detail.
Figure 5.1.1: Receive Data Structure
000 LTIME
000 MTIME
000 HTIME
001 LTIME
001 MTIME
001 HTIME
|
|
3FF LTIME
Current Value Buffer
7 6 5 4 3 2 1 0
1=Run
1=100k 0=12.5k
1=Interrupt on error
CHTYPE(RO)
RCVCW(RW)
CVBPTR(RW)
CTBPTR(RO)
GFTPTR(RW)
CFTPTR(RW)
CVAPTR(RW)
CTAPTR(RW)
Rerserved
Rerserved
LABCNT(RO)
CMIPTR(RW)
CMCPTR(RO)
CMLPTR(RO)
1=SDI/DATA sorting
(256
or
1024) * 3
Receiver Control Word (RCVCW)
000
001
|
100
101
|
|
|
3FF
512
or
2048
Current Time Buffer
00h
Offset
Note: Table length depends
on the use of SDI bits
8
1=Swap current values
1=Interrupt on swap
1=Force monitor swap
1=Restart monitor
1=Monitor halt
CMLPTR(RO)
CMCNT(RW)
Rerserved
Rerserved
Rerserved
BTWCNT (RO)
CHLED (RES) CHLED (RES)
F E D C B A 9
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
- -
1 = Channel Wrap Enabled
0 = Channel Wrap Disabled
12h
11h
10h
0Fh
0Eh
0Dh
0Ch
0Bh
0Ah
09h
08h
07h
06h
05h
04h
03h
02h
01h
00h
Rerserved
CWTX (RW)
Receive Control Block Structure
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
Rerserved
1=Interrupt on
current value swap
1 = Receive Mode 24 bit
0 = Receive Mode 32 bit
Receive Data Structure 5-3
5.1.1 Channel Type (CHTYPE)
This word species the type of channel. The word contains FFFFh if the channel
has been designated as a transmit channel. The word contains 0000h if it chan-
nel has been designated as a receive channel. The word value is provided for
informational purposes only. If the value contained in the CHTYPE word is
modied, it will not affect module operation.
Notes: The A429 PC8, cPCI, and PCI can simulate up to e ight
ARINC 429 channe ls.
Each of the two de vice s on the A429 PC16 and A429 V2 can
simulate up to e ight ARINC 429 channe ls.
The A429 PC104 can simulate up to four ARINC 429 channe ls.
Each channe l is congure d for e ithe r transmit or re ce ive op-
e ration base d on the value s e nte re d in 800h and 801h during
the Module Startup proce dure .
5.1.2 Receiver Control Word (RCVCW)
This word controls receiver operations through the following nine bits:
Bit 0 - Run/Halt To start receive operations for the specied receiver, set this bit to 1. To halt
receive operations, set this bit to 0.
Bit 1 - Receiver
Speed
To process 100 KHz ARINC data, set this bit to 1. To process 12.5 KHz
ARINC data, set this bit to 0.
Bit 2 - Int errupt
on Error
To generate a host interrupt when a received data word contains an error, set
this bit to 1.
Bit 3 - SDI/Dat a To sort received data by SDI bits and label (bits 0-9 of ARINC word), set this
bit to 1. To sort received data by label only (bits 0-7 of ARINC words), set this
bit to 0.
Bit 4 - Channel
Monit or Halt
(RO)
If this bit is 1, the monitor halts. A halt can also occur if the monitor link
pointer, CMLPTR, is zero. When the monitor restarts, the rmware clears this
bit.
Bit 5 - Rest art
Channel Monit or
(R/W)
To restart the channel monitor after a halt has occurred, set this bit to 1. when
the monitor restarts, the rmware clears this bit, as well as bit 4.
5-4 Receive Management Firmware Reference
Doc: a429 re f 05.fm, ve r 2.0, 1 Jun 1999, 09:36
Bit 6 - Force
Monit or Swap
(R/W)
To force a monitor buffer swap, set this bit to 1. The rmware clears this bit
after the swap has occurred.
Bit 7- Int errupt
on Swap (R/W)
To generate an interrupt to the host each time a monitor swap occurs, set this bit
to 1.
Bit 8 - Service
Current Value
Buff ers (R/W)
To cause the current value and time pointers to swap, set this bit to 1. The
swap allows you to read the current value and time buffers pointed to by
CVBPTR and CVTPTR, respectively. The rmware clears this bit after the
pointers have been swapped.
Bit 9 - Int errupt
on Current Value
Swap
To generate an interrupt to the host each time a current value buffer swap accurs,
set this bit to 1.
Bit 12 -
Channel Wrap
To enable channel wrap, set this bit to 1.
Note: If the channe l wrap fe ature is e nable d, channe l wrap
will be the transmitte rs only function.
5.1.3 Current Value Buffer Pointers (CVAPTR, CVBPTR)
These words point to the base offset of the current value buffers. The current
value buffers are 512- or 2048-word buffers containing the most recently re-
ceived ARINC words arranged by SDI, label, or both. For the PC8 and the
PC16, the current value buffers must be in device memory Window 1 between
B00h and FFFFh.
Note: Pe r ARINC spe cications, the labe l (le ast signicant 8
bits) has a re ve rse d bit orde r. For e xample , labe l AAh is trans-
mitte d as 55h. Labe ls are bit swappe d prior to be ing store d
in the curre nt value buffe r. If the le ast signicant 8 bits
re ce ive d are 55h, the word will be store d at offse t (SDI logical-
ly ORe d with 55h) 2.
To read the current values, set bit 8 of RCVCW to 1. The active pointer,
CVAPTR, swaps value with CVBPTR and clears bit 8. Then read the values
pointed to by CVBPTR. Reading buffer from left to right, the order of data is
LDATA then HDATA.
Low Dat a
(LDATA)
This location contains the lower 16 bits of data.
Receive Data Structure 5-5
High Dat a
(HDATA)
This location contains the upper 16 bits of data.
Note: Be aware of the available A429 de vice me mory whe n
using sort by SDI.
5.1.4 Current Time Buffer Pointers (CTAPTR, CTBPTR)
These words point to the base offset of the current time buffers. If CTAPTR and
CTBPTR are nonzero when a word is received, a 48-bit time stamp is stored in
the active current time buffer. The received word determines the CTAPTR
offset. The time stamp is stored at:
The current time value buffers must be in device memory window 1 between
B00h and FFFFh. To read current times:
1. se t bit 8 of RCVCW to 1 . This swaps the active pointe r with CTBPTR and cle ars
bit 8.
2. Re ad value s pointe d to by CTBPTR from le ft to right. The orde r of the time
stamp is LTIME, MTIME, and HTIME.
Low Time
(LTIME)
This location contains the least signicant 16 bits of the 48-bit time stamp.
Middle Time
(MTIME)
This location contains the middle 16 bits of the 48-bit time stamp.
High Time
(HTIME)
This location contains the upper 16 bits of the 48-bit time stamp.
5.1.5 Global Filter Pointer (GFTPTR)
This register contains an offset to a table of 128 or 512 words arranged by SDI,
label number, or both. Entries in this table govern interrupts and sequential
monitoring for each possible receive SDI, label, or both. Entries are placed on
8-bit boundaries. Even labels occupy the eight least signicant bits and odd
labels occupy the eight most signicant bits. Figure 5.1.2 illustrates this table
and details the bits of an entry.
OFFSET CTAPTR
SDI
LABEL
-------------------- x 3 + =
5-6 Receive Management Firmware Reference
Doc: a429 re f 05.fm, ve r 2.0, 1 Jun 1999, 09:36
Figure 5.1.2: Global Filter Table Structure
5.1.6 Global Filter Bit Descriptions
Bit 0/Bit 8 -
Sequent ial
Monit or Enable
To store messages having the associated label in the sequential monitor, set bits
to 1. To lter messages having the associated label from the sequential mon-
itor, clear this bit to 0.
Bit 1/Bit 9 -
Int errupt on
Label
To cause the rmware to interrupt the host when this label is received, set bits
to 1. To select no interrupts, clear this bit to 0.
Bit 2/Bit 10 -
Disable Parit y
Check
To disable parity checking, set bits to 1. This allows for handling of ARINC
575 transmissions. To enable parity checking, clear this bit to 0.
Bit 3/Bit 11 -
Sequent ial Swap
on Label
To cause a sequential buffer swap to occur when the associated label is received,
set these bits to 1. To select no buffer swap, clear this bit to 0.
Bit s 4-7 and
12-15
Reserved
FLT 001/ FLT 000
FLT 003 / FLT 002
|
|
FLT 3FF / FLT 3FE
7 6 5 4 3 2 1 0
1 = Enable Sequential monitoring
0 = Disable Sequential monitoring
1 = Interrupt on label
0= No interrupt
1 = Sequential buffer swap on label
0 = No swap on label
1 = Disable parity check
0 = Enable parity check
GFTPTR
15 14 13 12 11 10 9 8
SDI/Label 000 SDI/Label 001
Reserved
1 = Disable Sequential monitoring
0 = Enable Sequential monitoring
1 = Interrupt on label
0= No interrupt
1 = Sequential buffer swap on label
0 = No swap on label
1 = Disable parity check
0 = Enable parity check
Reserved
Note: SDI bits used only if bit 3 of
RCVCW is set to "1"
Exploded View of Filter Table Words
Receive Data Structure 5-7
5.1.7 Channel Filter Pointer (CFTPTR)
This register contains an offset to a table of 128 or 512 words arranged by label
or SDI and label. Entries in this table govern sequential monitoring on a chan-
nel level for each possible receive label or SDI and label. Entries are placed on
8-bit boundaries. Even labels occupy the eight least signicant bits and odd
labels occupy the eight most signicant bits. Figure 5.1.3 illustrates this table
and details the bits of an entry.
Figure 5.1.3: Channel Filter Table Structure
5.1.8 Channel Filter Bit Descriptions
Bit 0
Enable Channel
Sequent ial
Monit oring
To enable Channel Sequential Monitoring, set this bit to 1.
To disnable Channel Sequential Monitoring, set this bit to 0.
Bit 1
Channel Wrap
To cause the associated label to be channel wrapped, set bits to 1.
For normal operation se bits to 0.
Bit s 2 Reserved
Bit 3
Sequent ial Swap
on Label
To cause a sequential buffer swap to occur if the associated label is received,
set this bit to 1. To select no buffer swap, clear bit to 0.
FLT 001/ FLT 000
FLT 003 / FLT 002
|
|
FLT 3FF / FLT 3FE
7 6 5 4 3 2 1 0
1 = Enable Channel Sequential Monitoring
0 = Disable Channel Sequential Monitoring
1 = Channel Sequential Buffer Swap on Label
0 = No Swap on Label
CFTPTR
15 14 13 12 11 10 9 8
SDI/Label 000 SDI/Label 001
Reserved
1 = Enable Channel Sequential Monitoring
0 = Disable Channel Sequential Monitoring
1 = Channel Sequential Buffer Swap on Label
0 = No Swap on Label
Reserved
Note: SDI bits used only if bit 3 of
RCVCW is set to "1"
Reserved
Reserved
Exploded View of Filter Table Words
1 = Channel Wrap Enable
0 = Normal Operation
1 = Channel Wrap Enable
0 = Normal Operation
5-8 Receive Management Firmware Reference
Doc: a429 re f 05.fm, ve r 2.0, 1 Jun 1999, 09:36
Bit s 4 t o 7 Reserved
Bit 8
Enable Channel
Sequent ial
Monit oring
To enable Channel Sequential Monitoring, set this bit to 1.
To disnable Channel Sequential Monitoring, set this bit to 0.
Bit 9
Channel Wrap
To cause the associated label to be channel wrapped, set bits to 1.
For normal operation se bits to 0.
Bit 10 Reserved
Bit 11
Sequent ial Swap
on Label
To cause a sequential buffer swap to occur if the associated label is received,
set this bit to 1. To select no buffer swap, clear bit to 0.
Bit s 12 t o 15 Reserved
Transmit channels that received data will be wrapped to a valid transmit chan-
nel. Valid transmit channels are 2 thru 8.
5.1.9 Channel Monitor Initial Pointer (CMIPTR)
This register contains a pointer to the base of the channel monitor. Prior to writ-
ing a nonzero value to the CMD register, initialize CMIPTR to a nonzero value.
5.1.10 Channel Monitor Current Pointer (CMCPTR)
This register contains a pointer to the currently active channel monitor buffer.
The buffer stores received data.
5.1.11 Channel Monitor Last Pointer (CMLPTR)
This register contains a pointer to the last monitor buffer which was lled. Data
is this buffer is safe to read.
5.1.12 Channel Monitor Buffer Counter (CMCNT)
This register contains a value that indicates the monitor swap count. This value
increments each time a channel monitor swap occurs. It can initialize to any val-
ue. This value will roll over to 0000h once FFFFh swap occur. CMCNT is stored
in the channel monitor buffer at offset 4 when a swap occurs.
Firmware Operation 5-9
5.1.13 Bus Trafc Word Count (BTWCNT)
This value increments for each word received and can be used as a measure for
bus loading.
5.1.14 CHLED
This value is used by the A429 rmware to indicate bus activity:
Table 5.1.1: Bus Activity Values
5.2 Firmware Operat ion
During receive operations, the rmware polls an I/O status register to determine
if new data has been received, or if a bus error has occurred on a specic receive
channel. If data has been received or an error has occurred, the rmware reads
the I/O receive buffer. The rmware processes the data, fetches a time stamp,
and stores the data in the current value buffer (if initialized). The rmware then
stores the data in the sequential monitor(s). If an error occurs when receiving
the data, the data and a time stamp are stored in the sequential monitor regard-
less of the bits set in the lter table. The current value buffer is not updated.
The lter value is the label offset plus GFTPTR/CFTPTR. The lter value man-
ages interrupts, Channel Wrap, and Sequential Monitoring for the data received.
Processing begins when bit 0 of RCVCW is set to 1 and continues until bit 0
is set to 0.
Value Activity
0000 no bus activity
00FF channel is active
FF00 channel is receiving errors
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Doc: a429 re f 05.fm, ve r 2.0, 1 Jun 1999, 09:36
5.3 Cont rolling Operat ion
To perform normal ARINC 429 receive operations, complete the following
steps:
1. De te rmine the location for the curre nt value buffe r and curre nt value active
buffe r (optional).
2. Store the curre nt value locations in CVBPTR and CVAPTR, re spe ctive ly. Curre nt
value and curre nt time buffe rs are locate d in me mory be twe e n B00h and
FFFFh.
Note: For the PC8 and PC16, the me mory is locate d in
Window 1. For the PC104 the me mory is in me mory Window
1, Window 2, or both.
3. Se t up the control ags for e ach labe l in the lte r table , locate d at pointe rs
GFTPTR and CFTPTR.
4. Cle ar all value s in the lte r table to allow for normal ope ration. This is the
de fault se tting.
5. De te rmine the location of se que ntial monitors.
6. Store the pointe r value s in CMIPTR and GMIPTR. The se que ntial monitors are
locate d in me mory be twe e n 10000h and 1FFFFh. For the PC8 and PC16 this
is in me mory Window 2. For the PC104 this is in me mory Window 3, Window 4,
or both.
Note: To acce ss de vice me mory window 2, se t bit 0 of the CSR
to 1 . For the PC 104, bits 1 and 2 of the CSR are use d to se -
le ct be twe e n four 64K me mory windows. The cPCI, PCI, and
V2 have a at me mory structure .
7. De ne the spe e d of the re ce ive r (bit 1 of RCVCW).
8. Enable inte rrupts (bit 2 of RCVCW)
9. Se le ct SDI/Labe l (bit 3 of RCVCW).
10. To start re ce ive proce ssing, se t the run bit (bit 0 of RCVCW) to 1 .
6-1
Note: The parame te rs and data structure s de scribe d in this
subse ction must be de ne d for both de vice s of the A429
PC-16 and A429 V2 in orde r to acce ss all sixte e n channe ls of
the board.
This subsection of the manual details the Sequential Monitoring feature of the
A429 module.
Sequential Monitoring stores raw ARINC 429 trafc in linked monitor buffers
for real-time data logging, recording, and analysis applications. The A429 is ca-
pable of storing every ARINC 429 message to monitor buffers and notifying the
host system of buffer swaps through interrupt and polling functions. The mes-
sages are stored with 48-bit, 1-microsecond resolution time stamps. This mon-
itoring method is useful when the host system has tight processing constraints
(relative to ARINC 429 trafc), but must still receive every ARINC 429 message
word. The key data structures for Sequential Monitoring are the Sequential
Monitor Buffers, the Filter Table, the Interrupt Queue, and the Trigger Control
Blocks.
There are two types of sequential monitoring:
Global
Channel
The global sequential monitor stores data received from all specied channels.
This monitor type includes triggering capabilities which are detailed at the end
of this chapter. The channel sequential monitor is provided for each A429 re-
ceive channel. Only data received on the receive channel is stored. This allows
for easy parsing of data received on a single channel. Both sequential monitor
types use the same data structures which are located in memory between
10000h and 1FFFFh. For the PC8 and PC16 this is in memory Window 2. For
the PC104 this is in memory Window 3, Window 4, or both.
6: Bus Moni t or i ng Fi r mw ar e Ref er ence
6-2 Bus Monitoring Firmware Reference
Doc: a429 re f 06.fm, ve r 2.0, 1 Jun 1999, 09:37
6.1 Sequent ial Monit oring
Sequential Monitoring provides a method of receiving every ARINC 429 mes-
sage in the same data format as presented on the bus. Dene the multiple mon-
itor buffers (of any length, up to the maximum available A429 memory). These
buffers are linked together through the use of pointers, forming a buffer chain.
The Filter Table for Global and Channel Sequential Monitoring must be dened
to specify which channel and label combinations will have their messages
stored in these buffers.
Messages ll one buffer at a time. The A429 rmware switches to the next buff-
er (pointed to by MLKPTR) when there are less than eight words remaining in
the current buffer (the size of an ARINC 429 message plus overhead words).
This action continues indenitely, or until a link pointer of zero is reached.
You must dene at least three structures before Sequential Monitoring can take
place:
The Filter Table must be dened with the desired channel/labels (Global
and Channel Only).
The Sequential Monitor Buffers must be dened.
The Interrupt Queue buffers must be dened.
If triggering is desired, the trigger structures must be dened. The starting
addresses for all of these data structures must be programmed in the Pointer
Table. The following paragraphs provide programming details for each of the
above data structures.
Cross Reference: Chapter 5: Receive Management Firmware
Reference also provide s programming de tails for the data
structure s.
Global Registers 6-3
6.2 Global Regist ers
6.2.1 Global Monitor Control Word (GMCWRD) - offset 8A9h
The global monitor control word, GMCWRD, governs the monitoring. The bits
of the global monitor control word are as follows:
Bit 0 - Monit or
Halt ed (RO)
This is a read-only bit. The monitor was halted, if this bit is 1. A halt can oc-
cur if the monitor link pointer, GMLPTR, is zero. When the monitor restarts, the
rmware clears this bit.
Bit 1 - Rest art
Monit or (RW)
To restart the monitor after a halt has occurred, set this bit to 1. The rmware
clears this bit, as well as bit 0, when the monitor restarts.
Bit 2 - Force
Monit or Swap
(RW)
To force a monitor buffer swap, set this bit to 1. The rmware clears this bit
after the swap occurs.
Bit 3 - Int errupt
On Swap (RW)
To generate an interrupt to the host each time a monitor swap occurs, set this bit
to 1.
Bit 4 - Overow
(RO)
This is a read-only bit. If this bit is 1, the monitor buffer has overowed. This
bit is used during triggering to indicate the read order of the data from the initial
monitor buffer.
Note: If trigge ring is be ing done and the ove row bit is se t to
1 , re ad data one word past the numbe r of words indicate d
by the word count (offse t 3 in the monitor). Continue re ading
to the e nd of the buffe r. The n, re ad the data from the start
of the initial monitor buffe r to the trigge r point. This will
place the data prior to the trigge r in the corre ct chronologi-
cal orde r. Continue re ading at the start of the ne xt monitor
buffe r to ge t the data re ce ive d afte r the trigge r e ve nt. If trig-
ge ring is be ing done and the ove row bit is se t to 0 , be gin
re ading data at the start of the initial monitor buffe r. Re ad
the numbe r of words indicate d by the word count (offse t 3 in
the monitor). This include s all of the data re ce ive d prior to
the trigge r e ve nt. Continue re ading at the start of the ne xt
monitor buffe r to ge t the data re ce ive d afte r the trigge r
e ve nt.
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6.2.2 Global Monitor Initial Pointer (GMIPTR) - offset 8AAh
This register points to the base of the rst sequential monitor buffer.
6.2.3 Global Monitor Current Pointer (GMCPTR) - offset 8ABh
This register points to the base of the currently active sequential monitor buffer.
6.2.4 Global Monitor Last Pointer (GMLPTR) - offset 8ACh
This register points to the base of the last sequential monitor buffer that was ac-
cessed.
6.2.5 Global Monitor Buffer Counter (GMCNT) - offset 8ADh
This register contains a count of the monitor buffers. GMCNT increments each
time a monitor buffer swap or a monitor halt occurs. Use this value to keep track
of monitor buffer swaps.
6.3 Channel Regist ers
6.3.1 Receive Control Word (RCVCW)
This word contains bits that control the receiver operations. Table 6.3.1. details
the bit information.
Channel Registers 6-5
Table 6.3.1: Receive Control Word Bits
6.3.2 Channel Monitor Initial Pointer (CMIPTR)
This register contains a pointer to the base of the channel monitor. Initialize
CMIPTR value to a nonzero value prior to writing a nonzero value to the CMD
register.
6.3.3 Channel Monitor Current Pointers (CMCPTR)
This register contains a pointer to the currently active channel monitor buffer.
Received data is stored in this buffer.
6.3.4 Channel Monitor Last Pointer (CMLPTR)
This register contains a pointer to the last monitor buffer which was lled. Read
the data stored in this buffer.
6.3.5 Channel Monitor Count (CMCNT)
This register contains a value indicating the monitor swap count. Initialize this
register to any value. When a swap occurs, CMCNT increments and places the
channel monitor buffer at offset 4. This value will roll over to 0000h after
FFFFh swaps have occurred.
Bit #
Bit Value
0 1
0 halt run
1 12.5 KHz 100 KHz
2 no interrupt interrupt on error
3 sorted by label sorted by SDI/label
4 channel monitor running channel monitor halted (RO)
5 do not restart restart channel monitor
6 no swap force channel monitor swap
7 no interrupt interrupt on channel monitor swap
8 no service service current value table
9 no interrupt interrupt on current value swap
C channel wrap operation disabled channel wrap operation enabled
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6.4 Filt er Table
The Global Filter Table and Channel Filter Table provide programming options
for receive operation and sequential monitoring. Eight possible receive regis-
ters hold a pointer to each of the two lter tables. Each lter table contains ei-
ther 128 or 512 words. Each word designates two of the 256 possible labels or
two of the 1024 possible SDI/label combinations. Each label or SDI/label com-
bination has an associated sequential monitor enable bit in the lter table. Data
from the associated SDI/label will be ltered from the sequential monitor buffer
if this bit is set to 1. There are no limits on the number of SDI/label words
that can be ltered from or stored to buffers.
Cross Reference: A de taile d Filte r Table de scription is in Chap-
ter 5: Receive Management Firmware Reference.
Cross Reference: Figure 6.4.1 and Figure 6.4.2 are provide d
for re fe re nce .
Figure 6.4.1: Global Filter Table Data Structures
FLT 001/ FLT 000
FLT 003 / FLT 002
|
|
FLT 3FF / FLT 3FE
7 6 5 4 3 2 1 0
1 = Enable Sequential monitoring
0 = Disable Sequential monitoring
1 = Interrupt on label
0= No interrupt
1 = Sequential buffer swap on label
0 = No swap on label
1 = Disable parity check
0 = Enable parity check
GFTPTR
15 14 13 12 11 10 9 8
SDI/Label 000 SDI/Label 001
Reserved
1 = Disable Sequential monitoring
0 = Enable Sequential monitoring
1 = Interrupt on label
0= No interrupt
1 = Sequential buffer swap on label
0 = No swap on label
1 = Disable parity check
0 = Enable parity check
Reserved
Note: SDI bits used only if bit 3 of
RCVCW is set to "1"
- - - - - - - - - - - - - - - - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Exploded View of Filter Table Words
Filter Table 6-7
6.4.1 Global Filter Bit Descriptions
Bit 0/Bit 8 -
Sequent ial
Monit or Enable
To store messages having the associated label in the sequential monitor, set bits
to 1. To lter messages having the associated label from the sequential mon-
itor, clear bits to 0.
Bit 1/Bit 9 -
Int errupt on
Label
The rmware will interrupt the host when this label is received if the bits are set
to 1. To select no interrupts, clear bits to 0.
Bit 2/Bit 10 -
Disable Parit y
Check
To disable parity checking, set bits to 1. This allows for handling of ARINC
575 transmissions. To enable parity checking, clear bits to 0.
Bit 3/Bit 11 -
Sequent ial Swap
on Label
Set bits to 1 to cause a sequential buffer swap to occur if the associated label
is received. Clear bits to 0 to select no buffer swap.
Bit s 4-7 and 12-
15
Reserved
Figure 6.4.2: Channel Filter Data Structures
FLT 001/ FLT 000
FLT 003 / FLT 002
|
|
FLT 3FF / FLT 3FE
7 6 5 4 3 2 1 0
1 = Enable Sequential Monitoring
0 = Disable Sequential Monitoring
1 = Buffer Swap on Label
0 = No Swap on Label
CFTPTR
15 14 13 12 11 10 9 8
SDI/Label 000 SDI/Label 001
Reserved
1 = Enable sequential monitoring
0 = Disable sequential monitoring
1 = Buffer swap on label
0 = No swap on label
Reserved
Note: SDI bits used only if bit 3 of
RCVCW is set to "1"
Reserved Reserved
- - - - - - - - - - - - - - - - 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1
Exploded View of Filter Table Words
1 = Channel Wrap Enable
0 = Normal Operation
1 = Channel Wrap Enable
0 = Normal Operation
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Doc: a429 re f 06.fm, ve r 2.0, 1 Jun 1999, 09:37
6.4.2 Channel Filter Bit Descriptions
Bit 0/Bit 8 -
Monit or Enable
Set bits to 1 to store messages having the associated label in the monitor buff-
er. Clear bits to 0 to lter messages having the associated label from the mon-
itor buffer.
Bit 1/Bit 9 -
Channel Wrap
Operat ion
To cause the associated label to be channel wrapped, set bits to 1. For normal
operation, clear bits to 0.
Bit 3/Bit 11 -
Sequent ial Swap
on Label
If the associated label is received, set bits to 1 to cause a sequential buffer
swap to occur. To select no buffer swap, clear bits to 0.
Bit s 1-2, 4-7, 9-
10, and 12-15
Reserved
6.5 Global and Channel Sequent ial Monit or Buff ers
Consider the host system's processing capabilities and the amount of ARINC
429 bus loading to determine the size of the buffers. For example, the maximum
transfer rate (about 2.8K words/second at 100 KHz) of the ARINC 429 bus re-
quires two 7K buffers. This results in two buffer swaps per second (and proba-
bly two interrupts to the host system per second). Most ARINC 429 buses have
much lower transfer rates. Most host systems can process much more than two
interrupts per second. Therefore, a smaller buffer size is required (typical A429
setups include buffers of 4K-16K words).
Sequential Monitoring takes place if the sequential monitor bit is set to 1 for
a particular label in the Global Filter Table, Channel Filter Table, or both. When
the A429 rmware detects a word with this label, it time stamps the message and
stores it in the next available message block of the buffer, pointed to by GMCP-
TR, CMCPTR, or both, along with a receiver status word. The rmware always
uses the value in GMCPTR, CMCPTR, or both as the starting address for the
current buffer. When the current buffer is lled, the rmware copies GMCPTR
to GMLPTR and CMCPTR to CMLPTR. GMCPTR and CMCPTR always
point to the current buffer and GMLPTR and CMLPTR always point to the
last monitor buffer serviced.
Global and Channel Sequential Monitor Buffers 6-9
Note: GMCPTR and CMCPTR are not update d with the curre nt
storage location within the buffe r. The se locations are main-
taine d inte rnally by the rmware .
Figure 6.5.1 and Figure 6.5.2 provide descriptions of the Sequential Monitor
Buffer data structure.
Figure 6.5.1: Global Sequential Monitor Buffer Data Structures
MLKPTR
MCWRD
MLNG
MWCNT
MBCNT
RESERVED
RESERVED
RESERVED
RESERVED
Status 1
Ltime 1
Mtime 1
Htime1
Ldata1
Hdata1
|
MLKPTR
MCWRD
MLNG
MWCNT
MBCNT
RESERVED
RESERVED
RESERVED
RESERVED
Status n
Ltime n
Mtime n
Htime n
Ldata n
Hdata n
|
GMIPTR GMCPTR
7 6 5 4 3 2 1 0
GMLPTR
- - - - - - - 0/1
Interrupt on End
GMCWRD
7 6 5 4 3 2 1 0
Interrupt on Swap
Restart Monitor
Monitor Halted
Force Monitor Swap
Extra Bit Error
Lost Bit Error
Parity Error
Channel ID
High Word
| Reserved
Reserved
|
|
Reserved
Reserved
|
|
Overflow
8 9 10 11 12 13 14 15
7 6 5 4 3 2 1 0
0/1
0/1
0/1 0/1 0/1 0/1
0/1 0/1 0/1 0/1 0/1 0/1 0/1
- - - - - - - - - -
- - - - - -
LABEL
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Figure 6.5.2: Channel Sequential Monitor Buffer Data Structures
6.6 Monit or Buff er Words
Each monitor buffer contains a nine-word header, consisting of the following:
6.6.1 Monitor Link Pointer (MLKPTR)
Each monitor buffer contains a monitor link pointer word at offset 0. This word
points to the next monitor buffer in the chain. the rmware reads MLKPTR
when it performs a monitor buffer swap.
The rmware swaps to the monitor buffer pointed to by its contents if MLKPTR
is nonzero. Monitoring stops if MLKPTR is zero.
MLKPTR
MCWRD
MLNG
MWCNT
MBCNT
RESERVED
RESERVED
RESERVED
RESERVED
Status 1
Ltime 1
Mtime 1
Htime1
Ldata1
Hdata1
|
MLKPTR
MCWRD
MLNG
MWCNT
MBCNT
RESERVED
RESERVED
RESERVED
RESERVED
Status n
Ltime n
Mtime n
Htime n
Ldata n
Hdata n
|
CMIPTR CMCPTR
Monitor Buffers
CMLPTR
Interrupt on End
RCVCW
Interrupt on Swap
Restart Monitor
Monitor Halted
Force Monitor Swap
Extra Bit Error
Lost Bit Error
Parity Error
Channel ID
High Word
| Reserved
Reserved
|
|
Reserved
Reserved
|
|
7 6 5 4 3 2 1 0
0/1 0/1 0/1 0/1 - - - - - -
- - - - - - - 0/1
7 6 5 4 3 2 1 0
0/1
7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15
0/1 0/1 0/1 0/1 0/1 0/1 0/1
- - - - - - - - - -
- -
LABEL
Monitor Buffer Words 6-11
6.6.2 Monitor Control Word (MCWRD)
Each monitor buffer contains a monitor control word at offset 1. When the mon-
itor buffer is full, set bit 0 of this word to 1 to generate an interrupt.
6.6.3 Monitor Length (MLNG)
Each monitor buffer contains a monitor length value at offset 2. This word de-
nes the total length of the monitor buffer. There are nine header words in each
monitor buffer. Each word the rmware receives occupies eight stored words.
MLNG must be at least 17 words in length. A halt or monitor swap occurs when
there are less then eight words of space remaining in the monitor buffer.
6.6.4 Monitor Word Count (MWCNT)
Each monitor buffer contains a monitor word count at offset 3. When a monitor
buffer swap or a monitor halt occurs this word updates with the total number of
words in the monitor buffer (including the nine header words).
6.6.5 Monitor Buffer Count (MBCNT)
Each monitor buffer contains a monitor buffer count at offset 4. When a monitor
buffer swap or a monitor halt occurs, GMCNT, CMCNT, or both fetches, incre-
ments, and stores the count in MBCNT. This value to keeps track of monitor
buffer swaps.
MBCNT is followed by four reserved words.
The remainder of the buffer contains word blocks, consisting of a status word
(Status), three time-stamp words (Ltime, Mtime, Htime), two 16-bit data words
(Ldata, Hdata), and two reserved words.
6.6.6 Status Word Bits
Bit 8 15 LABEL
Bit 7
Ext ra Bit s Error
The specied channel receives extra bits if this bit is set to 1. The received
data word will be indeterminate.
Bit 6 - Lost
Bit s Error
If bits were lost or a complete ARINC word was not received, set this bit to 1,
The received data word will be indeterminate.
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Bit 5 - Parit y
Error
If a parity error was detected in the received data, this bit is set to 1. To receive
a label from ARINC 575 protocol, disable parity checking.
Bit 4 - High
Word
If the error occurred while receiving the upper 16 bits of the ARINC word, this
bit is set to 1. If the error occurs in the lower 16 bits, this bit is set to 0.
Bit 3 Reserved
Bit s 2 t hru 0 -
Channel ID
These three bits indicate which channel receives the data. This is useful in the
global sequential monitor. Table 6.6.1 illustrates bits 2 thru 0.
Table 6.6.1: Channel Identication
The Ltime, Mtime, and Htime words provide a 48-bit, 1-microsecond resolution
value for word time stamping.
Hdata contains the upper 16 bits of the 32-bit ARINC word. Ldata contains the
lower 16 bits of the 32-bit ARINC word.
When a monitor buffer becomes full (less than eight words remaining), a mon-
itor buffer swap occurs or monitoring halts. Offset 3 stores the total number of
words in the monitor, including the header words.
The monitor count, GMCNT, CMCNT, or both, is incremented and copied to
offset 4 of the monitor.
The monitor link pointer, MLKPTR, is checked.
Bits
Value Channel
2 1 0
0 0 0 0 1
0 0 1 1 2
0 1 0 2 3
0 1 1 3 4
1 0 0 4 5
1 0 1 5 6
1 1 0 6 7
1 1 1 7 8
Monitor Buffer Words 6-13
If MLKPTR is 0, monitoring halts and bit 0 of GMCWRD or bit 4 of
RCVCW is set to 1. If MLKPTR is nonzero, monitoring continues with the
monitor buffer pointed to by MLKPTR. For a global monitor, GMLPTR is set
to GMCPTR and GMCPTR is set to MLKPTR. For a channel monitor, CMLP-
TR is set to CMCPTR and CMCPTR is set to MLKPTR. Monitor pointers and
counts are maintained in internal memory and are not accessible to the host sys-
tem. External values available to the host are updated during monitor swaps,
monitor restarts, and monitor halts.
Note: The global and channe l se que ntial monitor buffe rs
must be de ne d in orde r for the rmware to run. GMIPTR
and CMIPTR must point to buffe rs which are a minimum of
se ve nte e n words in le ngth (MLNG must be at le ast 17 for e ach
buffe r, including 9 he ade r words and 8 words for re ce iving).
6.6.7 Buffer Swap Detection
Either through hardware interrupts of by monitoring GMCPTR, GMLPTR,
CMCPTR, and CMLPTR for address changes, you can detect when a buffer
swap occurs.
The A429 will force a hardware interrupt to the host system when a buffer swap
occurs if:
the CSR control register (offset 0000h) enables interrupts and
if one of the following bits are set to 1:
bit 0 of MCWRD, bit 3 of GMCWRD, or bit 7 of RCVCW.
Cross Reference: Ple ase se e Chapter 2: Control Registers dis-
cussion on Control I/O re giste rs and Section 3.5: Interrupt
Management for more de tails.
The host system may detect a buffer swap by polling GMCPTR, CMCPTR, or
both for a change of address. Upon startup:
GMCPTR contains the address of the rst global sequential monitor buffer
CMCPTR contains the address of the rst channel sequential monitor
GMLPTR and CMLPTR contain 0
1. Whe n a global buffe r swap occurs GMCPTR is copie d to GMLPTR and MLKPTR is
copie d to GMCPTR.
2. Whe n a channe l buffe r swap occurs, CMCPTR is copie d to CMLPTR and MLKPTR
is copie d to CMCPTR.
3. GMCPTR and CMCPTR always contain the addre sse s of the curre nt buffe rs.
6-14 Bus Monitoring Firmware Reference
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6.7 Triggering
Triggers provide the ability to locate and monitor data according to where and
with what frequency it is received. Trigger processing is controlled by a trigger
control word and a linked list of trigger control blocks or TCBs. Figure 6.7.1
illustrates these data structures.
Note: Trigge ring applie s only to the global se que ntial
monitor.
Figure 6.7.1: Triggering Data Structures
TRGCW
TGIPTR
TGCPTR
TGLPTR
TYPE
TRGCH
LMASK
HMASK
LVALUE
HVALUE
TEVCNT
ERRTYPE
BLKAPTR
BLKBPTR
RESERVED
RESERVED
Trigger Control Block
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 = Trigger on channel TRGCH
0 = Trigger on any channel
0h = Trigger always
1h = Trigger on EQUAL
2h = Trigger on NOT EQUAL
3h = Trigger External
TYPE
TRGCH
LMASK
HMASK
LVALUE
HVALUE
TEVCNT
ERRTYPE
BLKAPTR
BLKBPTR
RESERVED
RESERVED
TYPE
TRGCH
LMASK
HMASK
LVALUE
HVALUE
TEVCNT
ERRTYPE
BLKAPTR
BLKBPTR
RESERVED
RESERVED
Other TCB's...
Trigger Control Registers
0/1 -- -- -- -- -- -- -- -- -- -- 0/1 0/1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0h = Trigger stopped
1h = Trigger at start
2h = Trigger at middle
3h = Trigger at end
-- -- -- -- -- -- -- -- -- -- -- -- -- 0/1 0/1
"OR" Operation to Trigger
Control Blocks (TCBs)
1 = "OR" Operation
0 = Normal Operation
0/1
7 6 5 4 3 2 1 0
-- -- -- -- -- 0/1 0/1 0/1
1h = Parity Error
2h = Lost Bit Error
4h = Extra Bit Error
0/1 0/1 0/1
1 = Trigger on any ERROR
1 = Trigger on ERROR Type
set by ERRTYP
1 = Trigger on ERROR Type
and TCB
Triggering 6-15
6.7.1 Trigger Control Registers
Trigger cont rol
word (TRGCW) -
off set 8A3h
This word determines the location of the trigger. Values for TRGCW appear in
Table 6.7.1.
Table 6.7.1: Values for Trigger Control Word
Select trigger at start to begin monitoring after the trigger event occurs. Select
trigger at middle to begin monitoring prior to the trigger and continue after
the trigger. Select trigger at end to halt monitoring when the trigger event oc-
curs. When the monitor halts, bit 0 of GMCWRD is set to 1. To restart mon-
itoring, set bit 1 of GMCWRD to 1. The rmware clears bits 0 and 1 when
the monitor is restarted.
Note: If Bit 2 is se t in TRGCW the rmware will che ck for a
match with the rst TCB, if the re is not a match with the rst
TCB the rmware will apply the same data word to the ne xt
and subse que nt TCBs. The TRIGGER will be applie d if any one
of the TCBs crite ria match the data word. If, afte r all the TCBs
have be e n applie d to the same data word and a match was
not found, the rmware will start ove r with the TCB and
pe rform the same logic for the ne xt data word re ce ive d.
Note: If too many TCBs (~ 5 to 10 de pe nding on bus loading)
are se tup, the rmware can be de laye d while pe rforming
OR ope ration.
Trigger Init ial
Point er (TGIPTR)
- off set 8A4h
Enter a value in this register to point to the base of the rst trigger control block.
All trigger control blocks must be located in A429 memory between 0B00h and
FFFFh (device memory Window 1 of the PC8/PC16 and memory Window 1,
Window 2, or both of the PC104). When trigger processing begins, the rm-
ware copies this value to TGCPTR.
Trigger Current
Point er (TGCPTR)
- off set 8A5h
This register contains a pointer to the trigger control block currently being
processed. This value is updated by the rmware.
Bit Value Description
0h no trigger processing
1h trigger at start
2h trigger at middle
3h trigger at end
4h OR operation to TCBs
6-16 Bus Monitoring Firmware Reference
Doc: a429 re f 06.fm, ve r 2.0, 1 Jun 1999, 09:37
Trigger Last
Point er (TGLPTR)
- off set 8A6h
This register contains a pointer to the last trigger control block processed. This
value is updated by the rmware.
6.7.2 Trigger Control Block (TCB)
Each TCB consists of twelve 16-bit words that govern trigger processing. The
following is a description of these words.
TYPE This word determines how received data affects the trigger event. Bit descrip-
tions follow:
Bit s 0-1 Table 6.7.2 describes mask and trigger values. Mask represents the value of
LMASK and HMASK and trigger value represents the value of LVALUE and
HVALUE.
Table 6.7.2: Mask and Trigger Values
Bit 15 To consider received data from any receive channel, set at 0.
To consider data received from the channel specied, set at 1. Use TRGCH to
specify the channel.
Bit Value Description
0h Trigger always. Trigger event occurs on any received data.
1h Trigger if equal. Trigger event occurs if received data, logi-
cally ANDed with mask, is equal to trigger value.
2h Trigger if not equal. Trigger event occurs if received data,
logically ANDed with mask, is not equal to trigger value.
3h Trigger if external event. Trigger event occurs if data is re-
ceived and an external trigger event occurs prior to having
received data.
Cross Reference: Se e Section 3.3: External Triggers for more
information.
4h Trigger on any error.
8h Trigger on error type set by ERRTYP.
10h Trigger on error type and TCB
Note: You will be able to trigge r on:
Error type se t by ERRTPP and TCB
or
Any e rror type and TCB.
Triggering 6-17
Trigger Channel
(TRGCH)
TRGCH species the channel to use for triggering if bit 15 of TYPE is set to
1. Process data from channel 1, set TRGCH to 0; to process data from chan-
nel 2, set TRGCH to 1; and so on.
High Mask and
Low Mask
(HMASK and
LMASK)
These words contain the mask that is logically ANDed with the received data
before it is compared to the trigger value. Use these values to mask off data that
is not important for triggering.
High Value and
Low Value
(HVALUE and
LVALUE)
These words contain the trigger value. For example, to trigger on SDI = 2, set
HVALUE to 0000h, LVALUE to 0200h, HMASK and LMASK to FFFFh, and
TYPE to 0001h.
Note: SDI bits re side in bit locations 8 and 9 (with the le ast
signicant bit de ne d as bit 0).
Trigger Event
Count (TEVCNT)
This word contains the number of received data matches to detect before trig-
gering. For example, to trigger on the fth occurrence of a particular label, set
TEVCNT to 0005h.
Block A Point er
(BLKAPTR)
If a trigger match is made and the number of matches (specied by TEVCNT)
is met, set this word address to process the trigger control block. Set this value
to zero to stop trigger processing when the trigger conditions are met. Use this
word to create a chain of trigger control blocks.
Block B Point er
(BLKBPTR)
If a trigger match is NOT made or the number of matches (specied by
TEVCNT) is NOT met, set this word to process the address of the trigger control
block. Set this value to zero to stop trigger processing when the rst NOT con-
dition occurs. Use this word to create a chain of trigger control blocks.
6.7.3 Triggering Example
When data is received, the logic used for triggering is as follows:
IF (Data Received on Trigger Channel & MASK) = (or <>) VALUE
and IF the Number of Matches is met
THEN GOTO BLKAPTR
ELSE GOTO BLKBPTR
6-18 Bus Monitoring Firmware Reference
Doc: a429 re f 06.fm, ve r 2.0, 1 Jun 1999, 09:37
For example, to trigger at end on the eighth occurrence of SDI bits not equal to
3 being received on receive channel 4, set up the trigger data structures as fol-
lows:
TRCWRD = 0003hTrigger at the end. This will store data prior to the trigger
event and halt monitoring when the trigger event occurs.
The amount of stored data is dependent on the length of the rst monitor buffer
and the time at which the trigger event occurs.
TGIPTR=base if TCB (between offsets 0B00h and FFFFh).
Table 6.7.3: Trigger Control Block words
Term Trigger Control Block Words:
TYPE = 8002h Bit 15 = 1 (consider data from only one channel)
Bits 0-1 = 2h (trigger if not equal)
TRGCH= 0003h Select channel 4 as trigger channel
MASKL = 0300h Mask off all but bits 8 and 9 of least significant 16 bits of the
received word - SDI bits
MASKH = 0000h Mask off the 16 most significant bits of the received word
LVALUE = 0300h Trigger on SDI=3h
HVALUE = 0000h Most significant bits are don't care
TEVCNT = 0008h Require 8 occurrences before triggering
BLKAPTR = 0000h Triggering will stop when the above conditions are met
BLKBPTR = base of TCB
(i.e., BLKBPTR = TGIPTR)
Use the first TCB for comparison with every received data
word
Triggering 6-19
6.7.4 Conditions Required for Trigger Processing
Trigger processing starts when the following conditions are met:
1. Both TRGCW and TGIPTR are nonze ro.
2. Re ce ive proce ssing is starte d (Se e Chapter 5: Receive Management Firmware
Reference for de tails.)
3. Data is re ce ive d on a re ce ive channe l.
Trigger processing halts when the trigger conditions are met and BLKAPTR is
zero. When this occurs, TGCPTR is set to zero, TGLPTR points to the last trig-
ger control block processed, and TGCWRD is set to zero. To restart trigger pro-
cessing, set TGCWRD to a nonzero value.
Note: If an e rror occurs due to imprope r se tup of trigge r
type s and TGCWRD, trigge r proce ssing will halt. The rmware
doe s not ve rify that pointe rs have be e n prope rly initialize d.
Note: Whe n trigge ring @ start the data will be store d in the
rst monitor buffe r prior to the trigge r. Afte r the trigge r
e ve nt occurs, data will start lling at the be ginning of the
rst monitor buffe r. The time stamp in the monitor buffe r
will de te rmine whe n monitoring stoppe d afte r a trigge r
e ve nt.
Whe n trigge ring @ middle the data will start lling data in
the rst buffe r. Whe n the trigge r e ve nt occurs the buffe rs
swap and start lling data in the se cond buffe r.
6-20 Bus Monitoring Firmware Reference
Doc: a429 re f 06.fm, ve r 2.0, 1 Jun 1999, 09:37
Introduction A-1
A.1 Int roduct ion
Before accessing the A429 PCMCIAs socket controller chipset, you must rst
follow the Card Services Calls to set up the host computer. These calls should
be executed in the order listed below:
1. Ge tCardSe rvice sInfo()
2. Re giste rClie nt()
3. Re que stIO()
4. Re que stWindow()
5. MapMe mPage ()
6. Re que stConguration()
7. Re se tCard()
When the application program is exiting, the following Card Services Calls
should be executed to decongure the PCMCIA socket controller chipset.
1. Re le ase Conguration()
2. Re le ase Window()
3. Re le ase IO()
4. De re giste rClie nt()
The above Card Services Calls are explained in the remainder of this appendix.
A: PCMCIA Socket Cont r oller Set up
A-2 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2 General Card Services Inf ormat ion
Make Card Services Calls from the application program using software inter-
rupts. The interrupt number is 1Ah. When the software interrupt is generated,
the internal processor registers contain information about the type of call and the
parameters of the call. Upon return from the Card Services Call, the processor's
AX register contains the return code and the Carry Flag indicates whether an er-
ror occurred.
The Card Services Calls that are required to set up the controller chip are de-
scribed in the following paragraphs:
Cross Reference: For information on othe r Card Se rvice s
Calls, ple ase re fe r to the PCMCIA spe cication or a PCMCIA
re fe re nce book.
A.2.1 Function 0Bh - GetCardServicesInfo
This function detects the presence of Card Services. It also provides informa-
tion on the number of logical sockets present, the compliance level of the CS
implementation, and vendor identication information.
Input AH = AFh
AL = 0Bh
DX = Not used
DI:SI = Not used
CX = Argument Length (>4)
ES:BX = Argument Pointer
Output
AX = Return Code
Carry Flag = 0 - GetCardServicesInfo successful
1 - GetCardServicesInfo failed
General Card Services Information A-3
Table A.2.1: GetCardServicesInfo Argument List
Offset FieldName Bytes I/ O Description
0 InfoLen 2 O
Length of data block returned by Card
Services
2 Signature 0 1 I/O
ASCII C returned if CS installed.
Must be set to 00h on entry
3 Signature 1 1 I/O
ASCII S returned if CS installed.
Must be set to 00h on entry
4 Count 2 O Number of sockets
6 Revision 2 O Vendor's CS version number in BCD
8 CS Level 2 O Card Services Release Number in BCD
10 VStrOff 2 O
Offset to Vendor string in argument
packet
12 VStrLen 2 O Length of vendor string
14 VendorString N O ASCIIZ vendor string
A-4 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.2 Function 10h - RegisterClient
Register Client registers a single client with Card Services. The client species
through the argument list, what type of client it is, what events it should be no-
tied of, and the version of Card Services the client is expecting. The client also
supplies an address that Card Services calls (callback handler) when one of the
monitored events occurs.
Register Client returns a ClientHandle value. The Client Handle is the client's
identication and must be used for all CS functions that require a Client Handle
eld. After a successful Register Client function call, the client is called back
with a REGISTRATION_COMPLETE event when Card Services completes its
internal registration processing.
Input AH = AFh
AL = 10h
DX = Not used
DI:SI = Client Entry point for callback
CX = Argument Length (14)
ES:BX = Argument Pointer
Out put AX = Return Code
DX = Client Handle
Carry Flag = 0 - Register Client successful
1 - Register Client failed
Related Functions: Deregister Client
General Card Services Information A-5
Table A.2.2: Register Client Argument List
Table A.2.3: ClientData Bindings
Offset
Field
Name
Bytes I/ O Description
0 Attributes 2
I
Bit Mapped
Bit Description
0 1 = Memory client driver
1 1 = Memory technology driver
2 1 = I/O client driver
3 1 = CARD_INSERTION events for sharable
PC Cards
4 1 = CARD_INSERTION events for cards
being exclusively used
15:5 Reserved (zeros)
2 EventMask 2
I
When any one of these bits are set, the corresponding
event is prevented from causing an event callback to
this client.
Bit Description
0 Write Protect
1 Card Lock Change
2 Ejection Request
3 Insertion Request
4 Battery Dead
5 Battery Low
6 Ready Change
7 Card Detect Change
8 Power Management Change
9 Reset Events
10 Socket Services Change
15:11 Reserved (zeros)
4 Client Data 8
I
Data for client - see ClientData bindings below
12 Version 2
I
Card Services Version this client expects in BCD
Offset
8086 real
mode
286
protect
386
protect
386 flat
protect
OS/ 2
0
16 bit
client data
16 bit
client data
16 bit
client data
16 bit
client data
16 bit
client data
2
16 bit segment
for client data
16 bit selector
for client data
area
16 bit selector
for client data
area
16 bit reserved
(zeros)
16 bit selector
for client data
area
4 16 bit offset 16 bit offset 32 bit offset 32 bit offset 16 bit offset
6
16 bit reserved
(zeros)
16 bit reserved
(zeros)
16 bit reserved
(zeros)
A-6 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.3 Function 1Fh - RequestIO
Request an I/O address range for a socket. Used in conjunction with Request-
IRQ to assign I/O and IRQ resources required for an I/O card. A RequestCon-
guration is used to apply power and place the socket into an I/O interface. Two
I/O ranges can be specied in the argument list. Since a requested I/O range
may not be available for card use, RequestIO may need to be called multiple
times until a free range is found.
Input AH = AFh
AL = 1Fh
DX = Client Handle
DI:SI = Not used
CX = Argument Length (11)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - RequestIO successful
1 - RequestIO failed
Related Functions: RequestConguration
ReleaseIO
ReleaseConguration
General Card Services Information A-7
Table A.2.4: Request IO Argument List
Offset Field Name Bytes I/ O Description
0 Socket 2 I Logical Socket
2 Base Port1 2 I/O Base I/O port address for I/O window 1
4 Num Ports1 1 I Number of contiguous I/O ports for window 1
5 Attributes1 1 I Bit Mapped
Bit Description
0 1 = Shared I/O ports
1 1 = First of the shared cards
2 1 = Force alias accessibility
3 0 = 8 bit I/O, 1 = 16 bit I/O
7:4 Reserved (zeros)
6 Base Port2 2 I Base I/O port address for I/O window 2
8 Num Ports2 1 I Number of contiguous I/O ports for window 2
9 Attributes2 1 I Bit Mapped
Bit Description
0 1 = Shared I/O ports
1 1 = First of the shared cards
2 1 = Force alias accessibility
3 0 = 8 bit I/O, 1 = 16 bit I/O
7:4 Reserved (zeros)
10 IOAddrLines 1 I Number of I/O address lines decoded
A-8 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.4 Function 21h - RequestWindow
Request a block within system memory that PC Card memory can be mapped
into. The logical socket, window access speed, common/attribute, and data path
width are specied in the argument list. RequestWindow only sets up the win-
dow within system memory and the attributes assigned to that window. The
MapMemPage function species which are of PC Card memory is mapped to
this window.
Input AH = AFh
AL = 21h
DX = Client Handle
DI:SI = Not used
CX = Argument Length (13)
ES:BX = Argument Pointer
Out put AX = Return Code
DX = Window Handle
Carry Flag = 0 - RequestWindow successful
1 - RequestWindow failed
Related Functions: ReleaseWindow
MapMemPage
General Card Services Information A-9
Table A.2.5: Request Window Argument List
Offset
Field
Name
Bytes I/ O Description
0 Socket 2 I Logical Socket
2 Attribute 2 I/O Memory Window Attribute Field
Bit Description
0 Reserved (zero)
1 0 = Common memory, 1 = Attribute memory
2 Window enable control
3 0 = 8 bit, 1 = 16 bit access
4 0 = Window size determined by Size eld
1 = Window must be 16K multiple
5 1 = Memory range may be shared
6 First Shared
7 Binding specic
8 1 = Card offsets are window size
15:9 Reserved (zeros)
4 Base 4 I/O System Base Address
8 Size 4 I/O Memory Window Size
12 Access
Speed
1 I Window Speed
Bit Description
2:0 Device Speed code if speed mantissa is zero
0 = Reserved, 1 = 250ns, 2 = 200ns,
3 = 150ns, 4 = 100ns,
5-7 = reserved
2:0 Speed exponent if speed mantissa is not zero
0 = 1ns, 1 = 10ns, 2 = 100ns, 3 = 1s,
4 = 10s, 5 = 100s, 6 = 1 ms, 7 = 10ms
6:3 Speed Mantissa
0 = Use device speed code
1 = 1.0, 2 = 1.2, 3 = 1.3, 4 = 1.5, 5 = 2.0, 6 = 2.5,
7 = 3.0, 8 = 3.5, 9 = 4.0, A = 4.5, B = 5.0, C = 5.5,
D = 6.0, E = 7.0, F = 8.0
7 1 = Use wait if available
A-10 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.5 Function 14h - MapMemPage
Map an area in PC Card memory to a window into system memory. The win-
dow in system memory is identied with the Window handle argument. The
Window Handle argument is assigned through the RequestWindow function.
Input AH = AFh
AL = 14h
DX = Window Handle
DI:SI = Not used
CX = Argument Length (5)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - MapMemPage successful
1 - MapMemPage failed
Related Functions: RequestWindow
Table A.2.6: Map Mem Page Argument List
Offset Field Name Bytes I/ O Description
0 Card Offset 4 I Card offset address
1 Page 1 I Page number in specied window
General Card Services Information A-11
A.2.6 Function 30h - Request Conguration
Congure socket and PC card for interface type, I/O assignments, and Vpp, Vcc
settings. Power will be applied to the socket if power is off prior to the call. For
I/O cards, RequestIO and RequestIRQ should be called prior to a RequestCon-
guration to set up the IO and IRQ congurations.
Input AH = AFh
AL = 30h
DX = Client Handle
DI:SI = Not used
CX = Argument Length (17)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - RequestConguration successful
1 - RequestConguration failed
Related Functions: ReleaseConguration
A-12 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
Table A.2.7: Request Conguration Argument List
Offset
Field
Name
Byte I/ O Description
0 Socket 2 I Logical Socket
2 Attribute 2 I Bit Mapped
Bit Description
0 Reserved (zero)
1 1 = Enable IRQ steering
15:2 Reserved (zeros)
4 Vcc 1 I Vcc Setting in 0.1 volt increments
5 Vpp1 1 I Vpp1 Setting in 0.1 volt increments
6 Vpp2 1 I Vpp2 Setting in 0.1 volt increments
7 IntType 1 I Interface type
Bit Description
0 1 = Memory Interface
1 1 = Memory and I/O Interface
7:2 Reserved (zero)
8 CongBase 4 I Base address of conguration registers
12 Status 1 I Value in Card Status register if present
13 Pin 1 I Initial value to be written to Pin register if present
14 Copy 1 I Initial value to be written to Copy register if present
15 Option 1 I Initial value to be written to Option register if present
16 Present 1 I Card conguration registers present
Bit Description
0 1 = Option register present
1 1 = Status register present
2 1 = Pin Replacement register present
3 1 = Socket and Copy register present
7:4 Reserved (zero)
General Card Services Information A-13
A.2.7 Function 11h - Reset Card
Resets the specied PC Card in the specied socket. The client is notied of the
completion of the reset through a RESET_COMPLETE callback. Card Servic-
es will notify all other clients that have registered to receive the RESET status
before a reset is performed through a RESET_REQUEST callback. When all
clients have received notication and have approved the reset request, a
RESET_PHYSICAL is sent to all interested clients. After notication, Card
Services will reset the PC card and send a RESET_COMPLETE event to the re-
questing client.
Input AH = AFh
AL = 11h
DX = Client handle
DI:SI = Not used
CX = Argument Length (4)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - ResetCard successful
1 - ResetCard failed
Related Functions: RESET_REQUEST
RESET_PHYSICAL
RESET_COMPLETE
Table A.2.8: ResetCard Attribute List
Offset Field Name Bytes I/ O Description
0 Socket 2 I Logical Socket
2 Attributes 2 I Bit mapped
Bit Description
15:0 Reserved (zeros)
A-14 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.8 Function 1Eh - Release Conguration
Place selected socket and PC Card into a memory only interface. Card Services
may also remove power if no other clients are currently using the card. Card
Services is not allowed to reset or cycle power to the card.
Input AH = AFh
AL = 1Eh
DX = Client Handle
DI:SI = Not used
CX = Argument Length (2)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - ReleaseConguration successful
1 - ReleaseConguration failed
Related Functions: RequestConguration
ReleaseIO
RequestIO
Table A.2.9: Release Conguration Argument List
Offset Field Name Bytes I/ O Description
0 Socket 2 I Logical Socket
General Card Services Information A-15
A.2.9 Function 1Dh - Release Window
Release the area of memory previously allocated through a RequestWindow
function call. The Window handle passed in the function argument identies the
window to be released.
Input AH = AFh
AL = 1Dh
DX = Window Handle
DI:SI = Not used
CX = Argument Length (0)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag =0 - ReleaseWindow successful
1 - ReleaseWindow failed
Related Functions: RequestWindow
A-16 PCMCIA Socket Controller Setup
Doc: AppA.fm, ve r 2.0, 1 Jun 1999, 09:37
A.2.10 Function 1Bh - Release IO
Release I/O addresses previously allocated with a Request IO function. The in-
puts to this function should be the same as from the previous Request IO func-
tion call. No changes are made to the socket controller, only the Card Services
resource table is updated.
Input AH = AFh
AL = 1Bh
DX = Client handle
DI:SI = Not used
CX = Argument Length (11)
ES:BX = Argument Pointer
Out put AX = Return Code
Carry Flag = 0 - ReleaseIO successful
1 - ReleaseIO failed
Related Functions: RequestConguration
RequestIO
ReleaseConguration
General Card Services Information A-17
Table A.2.10: Release IO Argument List
Offset Field Name
Byte
s
I/ O Description
0 Socket 2 I Logical Socket
2 Base Port1 2 I Base I/O port address for I/O window 1
4 Num Ports1 1 I Number of contiguous I/O ports for window 1
5 Attributes1 1 I Bit Mapped
Bit Description
0 1 = Shared I/O ports
1 1 = First of the shared cards
2 1 = Force alias accessibility
3 0 = 8 bit I/O, 1 = 16 bit I/O
7:4 Reserved (zeros)
6 Base Port2 2 I Base I/O port address for I/O window 2
8 Num Ports2 1 I Number of contiguous I/O ports for window 2
9 Attributes2 1 I Bit Mapped
Bit Description
0 1 = Shared I/O ports
1 1 = First of the shared cards
2 1 = Force alias accessibility
3 0 = 8 bit I/O, 1 = 16 bit I/O
7:4 Reserved (zeros)
10 IOAddrLines 1 I Number of I/O address lines decoded
A-18 PCMCIA Socket Controller Setup
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A.2.11 Function 02h - Deregister Client
This function removes the specied client from the list of registered clients. All
resources allocated to the client must be returned prior to de-registering.
Input AH = AFh
AL = 02h
DX = Client handle
DI:SI = Not used
CX = Argument Length (0)
ES:BX = Not used
Out put AX = Return Code
Carry Flag = 0 - DeregisterClient successful
1 - DeregisterClient failed
Related Functions: Register Client
B-1
This appendix provides the following information for the A429-PC8, A429-
PC16, A429-PC104, A429-V2, A429-cPCI/PCI, and A429-PCMCIA cards:
General Specs
PC Characteristics
System Timer
B: Car d Speci c Inf or mat i on
B-2 Card Specic Information
Doc: AppB.fm, ve r 2.0, 1 Jun 1999, 09:37
B.1 Module Specicat ions
B.1.1 PC8
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Eight ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 1.5 Amps
+12V @250 mAmps
-12V @ 250 mAmps
PC
Charact erist ics
One-Half size ISA Bus Card
Syst em Timer 1sec, 48-bit time stamp clock
Module Specifications B-3
B.1.2 PC16
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Sixteen ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 1.5 Amps
+12V @250 mAmps
-12V @ 250 mAmps
PC
Charact erist ics
Three-Quarter size ISA Bus Card
Syst em Timer 1sec, 48-bit time stamp clock
B-4 Card Specic Information
Doc: AppB.fm, ve r 2.0, 1 Jun 1999, 09:37
B.1.3 PC104
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Four ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 1.5 Amps
+12V @250 mAmps
-12V @ 250 mAmps
PC
Charact erist ics
Standard PC104 Card
Syst em Timer 1sec, 48-bit time stamp clock
Module Specifications B-5
B.1.4 V2
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Sixteen ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 1.5 Amps
+12V @500 mAmps
-12V @ 500 mAmps
PC
Charact erist ics
6U VME Bus Card
Syst em Timer 1sec, 48-bit time stamp clock
B-6 Card Specic Information
Doc: AppB.fm, ve r 2.0, 1 Jun 1999, 09:37
B.1.5 cPCI/ PCI
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Eight ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 0.63 Amps
+12V @ 330 mAmps
-12V @ 280 mAmps
PC
Charact erist ics
3U cPCI card
Approximately one-half PCI card (length = 6.9 inches)
Syst em Timer 1sec, 48-bit time stamp clock
Module Specifications B-7
B.1.6 PCMCIA
General Concurrent and Independent ARINC Capabilities
Full Transmit Operation
100% Bus monitoring (Independent Receiver Monitoring or Sequential
Monitoring)
Eight ARINC 429 Channels
Each Channel Congurable for Transmit or Receive Operation
Maximum Power Consumption
5V @ 0.75 Amps
+12V @125 mAmps
-12V @ 125 mAmps
PC
Charact erist ics
PCMCIA Type II
Syst em Timer 1sec, 48-bit time stamp clock
B.1.7 Customer Support Service
SBS Technologies, Inc. is dedicated to providing technically superior products
and the best support possible. Full support for the A429 product line is provided,
including any reasonable assistance with the entire integration effort. For assis-
tance, please contact SBS Technologies via phone, fax, regular mail, or email.
SBS Technologies, Inc.
2400 Louisiana Boulevard NE, Building 5, Suite 600
Albuquerque, New Mexico 87110
1-800-SBS-1553 505-875-0600
FAX: 505-875-0400
e-mail: sbshelp@sbs1553.com
B-8 Card Specic Information
Doc: AppB.fm, ve r 2.0, 1 Jun 1999, 09:37
B.2 Design Review
The design of the A429 incorporates an open systems philosophy. The A429 is
a generic processing engine (the DSP processor and most of the hardware clock
and control circuits are software programmable) that can be congured through
various application programs. This manual explains the application program
(rmware) SBS has designed for optimal ARINC 429 bus processing and sim-
ulation. In this application, processing for each of the four, eight, or sixteen
channels is performed independently through host-dened Transmit, Receive,
and Monitoring data structures. The board's design allows for custom programs
(written by the customer or SBS) to correlate data between channels, or provide
advanced processing to off-load the host system.
For all boards except cPCI, PCI, and PCMCIA, you need to set address DIP
switches in order for the host to access the board. For the PC8, PC16, and
PC104, you use the switches to set the boards base I/O register. The PCMCIA
appears to the host processor as a 64K or 138K byte region of memory. PCM-
CIA settings for base I/O address, memory base address, and interrupt level are
software programmable.
The A429 V2 and PC16 appear as two independent 8-channel devices. These are
Device 1 and Device 2. Channels 1 through 8 are contained in Device 1 and
channels 9 through 16 are contained in Device 2. Each device has 256K of in-
ternal RAM.
Other host settings for interrupt level and vectors are software programmable
and are detailed in Chapter 2: Control Registers.
The following paragraphs provide an architectural overview of the A429. The
small blocked letter corresponds to the respective paragraph.
Design Review B-9
Figure B.2.1: A429-PC Block Diagram
B.2.1 Block (a): PC Interface
Figure B.2.1 illustrates the basic block diagram of the A429 module. From
bottom to top, the rst box shows the host interface. This circuitry includes the
D16 slave interface and interrupt logic.
B.2.2 Block (b): Memory Arbiter and Main Memory
The A429 provides a high speed bus arbiter for memory access between the
device and the host.
FRONT PANEL
(g)
A429 I/O
(h)
Triggers
(f)
LEDs
(d)
DSP
(b)
256k
byte SRAM
(b) High Speed
Arbiter
&
Drivers
(f) LOCAL I/O BUS
(e)
I/O Control
Registers
(a) Host Interface
(c) I/O Data
Port
(i)
IRIG
(optional)
B-10 Card Specic Information
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B.2.3 Block (c): I/ O Data Port
This circuit provides the host with access to the device RAM.
B.2.4 Block (d): DSP Processor
The DSP is a general purpose digital signal processor which executes the rm-
ware code to provide the low level Arinc functionality.
B.2.5 Block (e): I/ O Control Registers
This circuit provides the basic control functions of the A429-PC, including rm-
ware start/stop, PC interrupt control, memory base address, memory window
control, and memory access control.
B.2.6 Block (f): Local I/ O Bus
The local I/O bus of the board channel is a general purpose local bus. The bus
interconnects the ARINC 429 channels, hardware clock, and LED logic.
B.2.7 Block (g): A429 I/ O
The circuit provides the transmitter or receiver function for the actual A429
busses.
B.2.8 Block (h): Triggers
This circuit provides a dual latching 48-bit, 1-sec timer. The latching of a
48-bit time stamp is controlled by the DSP through discrete logic. The latching
ensures accurate and consistent time marks for each ARINC 429 message. The
48-bit timer may be preset or reset by the host system.
B.2.9 Block (i) IRIG
This circuit provides decoding of an IRIG-B signal for use to synchronize the
onboard clock with a common time base.
Memory Organization B-11
B.3 Memory Organizat ion
PC8 and PC16 For the PC8 and Device 1 of the PC16, use ADRS_PORT, DATA_PORT, and
the window select bit (bit 0 of the CSR), to access the following windows :
1. De vice Me mory Window 1 (000000h-00FFFFh)
2. De vice Me mory Window 2 (010000h-01FFFFh)
To access Device 2 of the PC16, use ADRS_PORT2, DATA_PORT2, and the
Device 2 window select bit (bit 0 of CSR2).
1. De vice 2 Me mory Window 1 (000000h-00FFFFh)
2. De vice 2 Me mory Window 2 (010000h-01FFFFh)
When the window select bit is cleared to 0, Memory Window 1 in the PC8 or
PC16 is selected and memory access is between 000000h and 00FFFFh. When
the window select bit is set to 1, Memory Window 2 is selected and memory
access is between 010000h and 01FFFFh. Using only two or four PC I/O ports
to access A429 PC8 or PC16 memory allows the use of multiple boards without
depleting limited PC address space.
Table B.3.1: Device Window Select Bit
P
C
8
P
C
1
6
P
C
1
0
4
V
2
c
P
C
I
,

P
C
I
P
C
M
C
I
ACSR, Bit 0
Window
Select 1
CSR, Bit 2
Window
Select 1
CSR, Bit 1
Window
Select 0
Internal Address
Range
0 000000h-00FFFFh
1 010000h-01FFFFh
0 0 00000h-07FFFH
0 1 08000h-0FFFFh
1 0 10000h-17FFFh
1 1 18000h-1FFFFh
0 0 000000h-007FFFh
0 1 008000h-00FFFFh
1 0 010000h-017FFFh
1 1 018000h-01FFFFh
flat memory
flat memory
B-12 Card Specic Information
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PC104 When the base memory address of the PC104 is set between 100000h and
FFFFFFh, the PC104 is in Extended Memory Mode. In this mode the PC104
appears as a 256K Byte memory mapped window. When in this mode, the state
of the Select 0 and Select 1 bits in the I/O Control/Status Register is ignored. In
this mode, the host software has access to all of the internal memory with no
windowing.
PCMCIA Set the base memory address of the PCMCIA between 100000h and FFFFFFh
to map the device as a Large Window in the DOS Memory Area In this mode,
the PCMCIA appears as a 64K byte memory mapped window. Use the Select 0
and Select 1 bits in the I/O Control Register to select one of four 64K regions of
the internal memory. Table B.3.1 provides internal address ranges for the win-
dow with all of the possible values for the select bit.
NOTE: You should not acce ss the re se rve d inte rnal addre sse s
be twe e n 000000h and 0007FFh and 10000h and 0107FFh.
V2, cPCI, and PCI The V2, cPCI, and PCI use a at memory organization.
B.3.1 Application Memory Organization
The ARINC 429 application program controls key segments of main memory
containing the pointer table, and the receiver denition table for each channel.
Each channel contains these elements in separate areas of main memory.
The memory map for each of the two devices (Device 1 and Device 2) of the
PC16 and V2 have the same structure.
Figure B.3.1 illustrates the A429 memory map and the areas reserved for vari-
ous functions.
Memory Organization B-13
Figure B.3.1: A429 Memory Map
Separate control areas for each of the eight channels permit the A429 device to
operate each channel simultaneously. The transmit and receive registers for a
channel are located at offsets from the base address of that channel's control ta-
ble. Channel control tables start at 900h and have a length of 1Fh. Therefore, the
control table for channel 1 occupies 900h to 91Fh, the control table for channel
2 occupies 920h to 93Fh, and so forth.
RESERVED
00000h
007FFh
POINTER
TABLE and BIT
status area
00800h
00AFFh
Transmit
Structures,
Receive
Structures,
Trigger
structures, and
Interrupt
Queues
00B00h
0FFFFh
RESERVED
10000h
107FFh
Sequential
Monitor Buffers
10800h
1FFFFh
Word Address
256K Bytes of Memory
B-14 Card Specic Information
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The pointer table and hardware control registers are detailed in the Chapter 2:
Control Registers. Module startup and test functions are detailed in the Section
3.1: Module Startup/Test, and data structure control for Receive tables, Transmit
command blocks, Sequential Monitor, and Interrupt functions are detailed in
their respective subsections.
Compiler Issues C-1
C.1 Compiler Issues
The following compiler related issues should be taken into account prior to
building applications utilizing the ARINC 429 Standard Libraries:
Compiling 16-bit
Microsof t C/C++
Applicat ions and
DLLs.
The Microsoft Visual C/C++ compile Version 1.52 is required to compile
Microsoft 16-bit applications.
Compiling
Applicat ions
using t he 16-bit
Microsof t DLLs.
If you are compiling an application using the Microsoft 16-bit DLLs supplied
with the ARINC 429 Standard Libraries distribution, your application project
must be set to the large memory model. To set this feature, follow the steps listed
below:
1. Se le ct Project from the Options me nu.
2. Click on the Compiler button.
3. Click on Memory Model unde r Category: and change Model: to Large.
4. Click on the OK button.
5. Click on the OK button.
Compiling 32-bit
Windows 95
Borland C/C++
Applicat ions and
DLLs.
The current version of the ARINC 429 Standard Libraries does not support this
feature due to the fact that the Borland C/C++ compiler does not support direct
inport/outport calls in Win32 applications. However, the Microsoft Visual C++
4.x does support direct inport/outport calls and can be used to build 32-bit Win-
dows 95 applications.
C: A429 St andar d Int er f ace Li br ar i es
C-2 A429 Standard Interface Libraries
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C.2 Library Ref erence Table of Cont ent s
Device Management and Low Level Routines ................................... 5
a429_close_device ............................................................................................5
a429_get_block .................................................................................................6
a429_get_channel_address ...............................................................................7
a429_get_csr .....................................................................................................8
a429_get_device_record ...................................................................................9
a429_get_error_exception ...............................................................................10
a429_get_error_msg .......................................................................................11
a429_get_interrupt_vector ..............................................................................12
a429_get_num_channels .................................................................................13
a429_get_num_receive_channels ...................................................................14
a429_get_ram ..................................................................................................15
a429_init_device .............................................................................................16
a429_is_device_open ......................................................................................17
a429_is_device_valid ......................................................................................18
a429_load_ram ................................................................................................19
a429_malloc ....................................................................................................20
a429_malloc_high ...........................................................................................21
a429_open_device ...........................................................................................22
a429_parse_le ...............................................................................................23
a429_put_block ...............................................................................................24
a429_put_csr ...................................................................................................25
a429_put_ram .................................................................................................26
a429_soft_reset ...............................................................................................27
a429_start_application ....................................................................................28
a429_start_io ...................................................................................................29
a429_stop_io ...................................................................................................30
a429_wait_a_millisecond ...............................................................................31
a429_wait_a_second .......................................................................................32
Library Reference Table of Contents C-3
BIT Management Routines ................................................................ 33
429_bit (int device_number) ...........................................................................33
Receive Management Routines .......................................................... 34
a429_create_rc_cb ..........................................................................................34
a429_set_rc_control ........................................................................................35
a429_start_rc ...................................................................................................36
a429_stop_rc ...................................................................................................37
a429_get_current_value ..................................................................................38
a429_init_lter_table ......................................................................................39
a429_set_lter_table .......................................................................................40
a429_convert_label .........................................................................................41
Transmit Management Routines ....................................................... 42
a429_initialize_chain_pointers .......................................................................42
a429_create_tx_cb ..........................................................................................43
a429_halt_cb ...................................................................................................44
a429_add_mf_cmd_blk ...................................................................................45
a429_add_tx_cmd_blk ....................................................................................46
a429_load_chain .............................................................................................47
a429_read_type_word .....................................................................................48
a429_write_type_word ...................................................................................49
a429_write_tx_cb_data ...................................................................................50
Monitor Management Routines ........................................................ 51
a429_create_global_sm_buffers .....................................................................51
a429_add_global_sm_buffer ...........................................................................52
a429_create_channel_sm_buffers ...................................................................53
a429_add_channel_sm_buffers .......................................................................54
a429_add_sm_buffer_to_channels ..................................................................55
a429_read_global_sm_buffers ........................................................................56
a429_read_channel_sm_buffers ......................................................................57
a429_create_trigger_control_block ................................................................58
a429_load_trigger ...........................................................................................59
a429_halt_trigger ............................................................................................60
a429_set_trigger_pointer ................................................................................61
C-4 A429 Standard Interface Libraries
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Interrupt Management Routines ...................................................... 62
a429_disable_interrupts ..................................................................................62
a429_enable_interrupts ...................................................................................63
a429_handle_interrupts ...................................................................................64
a429_init_interrupt_queue ..............................................................................65
a429_get_interrupt_log_count ........................................................................66
a429_get_interrupt_log_entry .........................................................................67
Device Management and Low Level Routines C-5
C.3 Device Management and Low Level Rout ines
The low_lvl.c le contains common driver functions and low level routines
needed to initialize, setup, and run the ARINC 429 board.
C.3.1 a429_close_device
Close access to an open ARINC device.
Synt ax #include 429_incl.h
void a429_close_device (int device_number)
Descript ion a429_close_device ags an open ARINC device as being closed.
Paramet ers The device_number parameter indicates which ARINC device to close.
device_number - 1 can also be used as the index into a device array if one was
dened.
See Also a429_init_device, a429_open_device
C-6 A429 Standard Interface Libraries
Doc: AppC.fm, ve r 2.0, 1 Jun 1999, 09:37
C.3.2 a429_get_block
This function fetches a block of 16-bit values from the ARINC board.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_get_block(int device_number,
ULONGstart,
UWORDsize,
UWORD*p_data)
Descript ion a429_get_block reads a block of words beginning at offset start.
Paramet ers The device_number parameter species the ARINC device from which to re-
trieve the data. The start parameter is the offset of the rst location to be read
in ARINC memory. The size parameter is an integer number that species the
number of words to read. The parameter p_data is a pointer to a user dened
buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_get_csr, a429_put_csr, a429_put_block
Device Management and Low Level Routines C-7
C.3.3 a429_get_channel_address
Gets the channel address.
Synt ax #include 429_incl.h
UWORD a429_get_channel_address (int channel_number)
Descript ion Returns the channel address of the specied channel_number.
Paramet ers The channel_number parameter species the channel on the ARINC device.
The ARINC device designates which channels operate as receive channels and
which operate as transmit channels, based on the num_receive and
num_transmit values specied in a429dev.cfg. The receive channels are al-
ways assigned to the lower channel numbers.
Ret urn Value The channel address of the specied channel number.
C-8 A429 Standard Interface Libraries
Doc: AppC.fm, ve r 2.0, 1 Jun 1999, 09:37
C.3.4 a429_get_csr
Gets the Control/Status Register(CSR) of an open ARINC device.
Synt ax #include 429_incl.h
UWORD a429_get_csr (int device_number)
Descript ion a429_get_csr fetches and returns the CSR of a valid open ARINC device. Use
this function to determine the state of the ARINC device. The retrieved infor-
mation is saved in the device record for future reference.
Paramet ers The device_number parameter species the ARINC device from which to
retrieve the data.
Ret urn Value The return value of a429_get_csr is an unsigned word (UWORD) which con-
tains the 16 bits of the CSR or 0 if an error occurs.
See Also a429_put_csr, a429_get_block, a429_put_block
Device Management and Low Level Routines C-9
C.3.5 a429_get_device_record
Copy the record for a device into the user's buffer.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_get_device_record(int
device_number,
A429_DEVICE_RECORD
*device_record)
Descript ion This routine takes a device_number and a pointer to a user's
A429_DEVICE_RECORD structure and copies the device_record into that
structure.
Paramet ers The device_number parameter species the ARINC device from which to
retrieve the data. The device_record parameter is a pointer to the user buffer
into which the device record will be copied.
Ret urn Value This function returns either A429_OK or A429_BAD.
C-10 A429 Standard Interface Libraries
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C.3.6 a429_get_error_exception
Returns the local error exception.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_get_error_exception (void)
Descript ion Returns the value of the local static variable error_exception. This routine is
provided because the variable is local to this module and, hence, the values con-
tained therein are not visible to the outside world.
Ret urn Value Returns the value of error_exception.
See Also a429_get_error_msg
Device Management and Low Level Routines C-11
C.3.7 a429_get_error_msg
Returns a pointer to a string describing an error.
Synt ax #include 429_incl.h
char* a429_get_error_msg (void)
Descript ion Returns a pointer to a string that describes the error reported by the
error_exception number.
Ret urn Value The return value from a429_get_error_msg is a pointer to a NULL-terminated
string.
See Also a429_get_error_exception
C-12 A429 Standard Interface Libraries
Doc: AppC.fm, ve r 2.0, 1 Jun 1999, 09:37
C.3.8 a429_get_interrupt_vector
Returns the interrupt vector of an open ARINC device.
Synt ax #include 429_incl.h
UWORD a429_get_interrupt_vector (int device_number)
Descript ion Returns the interrupt vector of an open ARINC device.
Paramet ers The device_number parameter species the ARINC device from which to re-
turn the interrupt vector.
Ret urn Value The return value from a429_get_interrupt_vector is the interrupt vector of
an open ARINC device.
See Also a429_is_device_open
Device Management and Low Level Routines C-13
C.3.9 a429_get_num_channels
Gets the total number of channels of an open ARINC device.
Synt ax #include 429_incl.h
UWORD a429_get_num_channels (int device_number)
Descript ion Returns the total number of channels of an open ARINC device. This number
should agree with the value assigned to the num_channels parameter in the
a429dev.cfg le.
Paramet ers The device_number parameter species the ARINC device from which to re-
turn the number of channels.
Ret urn Value This function returns the total number of channels of an open ARINC device or
0 if an error occurs.
See Also a429_get_num_receive_channels
C-14 A429 Standard Interface Libraries
Doc: AppC.fm, ve r 2.0, 1 Jun 1999, 09:37
C.3.10 a429_get_num_receive_channels
Returns the number of receive channels of an open ARINC device.
Synt ax #include 429_incl.h
UWORD a429_get_num_receive_channels (int device_number)
Descript ion Returns the number of receive channels of an open ARINC device. This number
should agree with the value assigned to the num_receive parameter in the
a429dev.cfg le.
Paramet ers The device_number parameter species the ARINC device from which to
return the number of receive channels.
Ret urn Value This function returns the total number of receive channels of an open ARINC
device.
See Also a429_open_device, a429_get_num_channels.
Device Management and Low Level Routines C-15
C.3.11 a429_get_ram
Read a value from ARINC device memory.
Synt ax #include 429_incl.h
UWORD a429_get_ram (int device_number,
ULONG offset)
Descript ion Reads a value from ARINC 429 device memory.
Paramet ers The device_number parameter species the ARINC device from which to re-
trieve the data. The offset parameter is the offset of the location to be read
in ARINC memory.
Ret urn Value The a429_get_ram function returns result which is the value read from the
offset in memory or 0 if an error occurs.
See Also a429_put_csr
C-16 A429 Standard Interface Libraries
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C.3.12 a429_init_device
Opens and initializes an ARINC device.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_init_device (int device_number,
UWORD queue_length)
Descript ion a429_init _device initializes and opens one ARINC device for access by the
application. This function calls a set of ve library subprograms that provide the
initialization steps required for proper rmware operation. The subprograms
called are a429_open_device, a429_load_ram, a429_start_application,
a429_init_interrupt_queue, and a429_wait_a_second. This function
must be called for an ARINC device before further operation can proceed.
Paramet ers The device_number parameter indicates which 1553 device to open. The
queue_length parameter contains the number of interrupt queue entries de-
sired for each interrupt queue buffer. Two interrupt queue buffers, for double
buffering purposes, will be initialized. Interrupt queue initialization is required
for proper rmware operation even though interrupts may not be used by the ap-
plication.
Ret urn Value a429_init_ device returns either A429_ok or A429_BAD.
Diagnost ics A call is made to A429_get_error_message() which will return one of the fol-
lowing: A429_OPEN_FAIL or A429_OUT_OF_MEMORY.
See Also a429_open_device, a429_load_ram, a429_start_application,
a429_init_interrupt_queue, a429_wait_a_second
Device Management and Low Level Routines C-17
C.3.13 a429_is_device_open
Veries that the device is open.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_is_device_open (int device_number)
Descript ion This routine veries that the specied device number is valid and that the device
has been opened. The device_record structure contains all of the devices de-
ned in the a429dev.cfg le if at least one of these devices is open.
Paramet ers The device_number parameter indicates which open device to verify.
Ret urn Value The return value of a429_is_device_open is either A429_OK or A429_BAD.
C-18 A429 Standard Interface Libraries
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C.3.14 a429_is_device_valid
Validates a device number
Synt ax include 429_incl.h
A429_EXCEPTION a429_is_device_valid (int device_number)
Descript ion This routine validates the specied device number. The device_record struc-
ture contains all of the devices dened in the a429dev.cfg le if at least one of
these devices is open. This routine is necessary because the a429_device struc-
ture array is not accessible to the user.
Paramet ers The device_number parameter indicates which device to validate.
Ret urn Value This function returns either A429_OK or A429_BAD.
Diagnost ics A call is made to A429_get_error_message() which will return
A429_DEVICE_NOT _DEFINED.
Device Management and Low Level Routines C-19
C.3.15 a429_load_ram
Loads the rmware from the rmware le onto the ARINC PC card and veries
the results.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_load_ram (int device_number)
Descript ion The a429_load_ram will download the rmware le specied in a429dev.cfg
from the host to the ARINC device. Note that if the rmware is already running,
this function will stop the rmware.
Paramet ers The device_number parameter indicates on which device to download the rm-
ware.
Ret urn Value The return value of a429_load_ram is either A429_OK or A429_BAD.
Diagnost ics A call is made to A429_get_error_message() which will return one of the fol-
lowing: A429_FILE_OPEN_ERROR, A429_DOWNLOAD_ERROR,
A429_NO_CHANNEL_CFG_MODE, A429_INVALIDE_CHANNEL_CFG,
A429_POWER_UP_TEST_FAIL, or A429_BIT_ERRORS_DETECTED.
See Also a429_get_ram, a429_put_ram, a429_put_csr, a429_wait_a_second
C-20 A429 Standard Interface Libraries
Doc: AppC.fm, ve r 2.0, 1 Jun 1999, 09:37
C.3.16 a429_malloc
Allocates memory on the ARINC 429 device.
Synt ax #include 429_incl.h
UWORD a429_malloc (int device_number,
UWORD size)
Descript ion This function allocates the indicated number of words in the A429 RAM space
for the given device and returns the offset to the beginning of that space.
Paramet ers The device_number parameter indicates the ARINC device on which to allo-
cate memory. The size parameter is the amount of memory, in words, to allo-
cate.
Ret urn Value This function returns either the offset of the buffer or NULL.
Diagnost ics If the ARINC device exceeds the available RAM space, a call is made to
A429_get_error_message() which will return A429_OUT_OF_MEMORY.
See Also a429_malloc_high
Device Management and Low Level Routines C-21
C.3.17 a429_malloc_high
Allocates memory of an ARINC device located in upper memory.
Synt ax #include 429_incl.h
ULONG a429_malloc_high (int device_number,
USHORT size)
Descript ion This function allocates the indicated number of words in high RAM space for
the given device and returns the offset to the beginning of that space.
Paramet ers The device_number parameter indicates the ARINC device on which to allo-
cate memory. The size parameter is the amount of memory, in words, to allo-
cate.
Ret urn Value This function returns either the offset of the buffer or NULL.
Diagnost ics If the ARINC device exceeds the available RAM space, a call is made to
A429_get_error_message() which will return A429_OUT_OF_MEMORY.
See Also a429_malloc
C-22 A429 Standard Interface Libraries
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C.3.18 a429_open_device
Opens an ARINC device.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_open_device (int device_number)
Descript ion The a429_open_device function opens one ARINC device for access by the
application. This function is required for proper rmware initialization. The
rst time a device is opened, it parses the conguration le and reads the con-
guration of all devices. This function reads the CSR, sets IRQ levels, calls
a429_put_ram, and then probes the board to verify its presence.
Paramet ers The device_number parameter indicates which device to open.
Ret urn Value This function returns either A429_OK or A429_BAD.
Diagnost ics A call is made to A429_get_error_message() which will return one of the fol-
lowing: A429_DEVICE_PROBE_FAIL, A429_NO_429_ERROR, or A429_MEMORY_
ALLOCATION.
See Also a429_parse_file, a429_get_csr, a429_get_ram, a429_put_ram
Device Management and Low Level Routines C-23
C.3.19 a429_parse_le
Parses the ARINC device conguration le.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_parse_file (void)
Descript ion a429_parse file parses the ARINC device conguration (a429dev.cfg) le,
and retrieves the parameters for each of the devices into the device_record
structure. This routine is called to initialize the device_record structure the
rst time one of the devices is opened.
Diagnost ics A call is made to A429_get_error_message() which will return A429_MEMORY
ALLOCATION.
Ret urn Value The return value of a429_parse_file is either A429_OK or A429_BAD.
C-24 A429 Standard Interface Libraries
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C.3.20 a429_put_block
Writes a block of 16-bit values to the A429 board.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_put_block(int device_number,
ULONG start,
UWORD size,
UWORD *p_data)
Descript ion a429_put_block writes a block of words of size size starting at offset start.
This function is useful for writing large chunks of memory.
Paramet ers The device_number parameter indicates to which device the words will be
written. The start parameter is the offset of the rst location to be written in
ARINC memory. The size parameter is an integer that refers to the number of
words to write. The parameter p_data is a pointer to a user dened buffer.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_put_csr, a429_get_csr
Device Management and Low Level Routines C-25
C.3.21 a429_put_csr
Writes a 16-bit word to the Control/Status Register (CSR).
Synt ax #include 429_incl.h
A429_EXCEPTION a429_put_csr(int device_number,
UWORD value)
Descript ion a429_put_csr writes a 16-bit word to the CSR of an open ARINC device.
Paramet ers The device_number parameter selects an open ARINC device. The value pa-
rameter contains the 16-bit word to be written to the CSR.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_csr
C-26 A429 Standard Interface Libraries
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C.3.22 a429_put_ram
This function writes a 16-bit value to an ARINC device.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_put_ram(int device_number,
ULONG offset,
UWORD value)
Descript ion a429_put_ram writes a 16-bit word to an offset in the memory of the specied
ARINC device.
Paramet ers The device_number parameter selects an open ARINC device. The offset
parameter contains an offset to the location in memory where the word will be
written. The value parameter contains the 16-bit word to be written.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_ram
Device Management and Low Level Routines C-27
C.3.23 a429_soft_reset
Performs a soft reset on an ARINC device.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_soft_reset (int device_number)
Descript ion This routine turns off all receivers, stops I/O processing, clears memory, dis-
ables interrupts, and resets all library variables back to their default values.
Paramet ers The device_number parameter indicates which ARINC device to reset.
Ret urn Value The return value from the a429_soft_reset function will be either A429_OK or
A429_BAD.
See Also a429_stop_rc, a429_init_filter_table, a429_halt_cb,
a429_halt_trigger, a429_disable_interrupts
C-28 A429 Standard Interface Libraries
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C.3.24 a429_start_application
Starts application mode.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_start_application (int device_number)
Descript ion a429_start_application starts the execution of the rmware by switching
from BIT mode to application mode.
Paramet ers The device_number parameter species the ARINC device on which to start
the application.
Ret urn Value This function returns either A429_OK or A429_BAD.
Diagnost ics A call is made to a429_get_error_message() which will return
A429_START_APPLICATION_ FAIL.
See Also a429_get_ram, a429_put_ram, a429_wait_a_second, a429_init_device,
a429_open_device, a429_start_io
Device Management and Low Level Routines C-29
C.3.25 a429_start_io
Starts input and output operations on the bus.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_start_io (int device_number)
Descript ion This function enables the specied ARINC device to perform bus operations by
writing a nonzero value to the CMD register located at offset 0x880. This func-
tion should be called after the transmit, receive, and monitor structures have
been dened.
Paramet ers The device_number parameter species the ARINC device to start I/O.
Ret urn Value a429_start_io returns either A429_OK or A429_BAD.
Diagnost ics A call is made to A429_get_error_message() which will return
A429_START_IO_FAIL.
See Also a429_put_ram, a429_stop_io
C-30 A429 Standard Interface Libraries
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C.3.26 a429_stop_io
Stops input and output operations on the bus.
Synt ax #include 429_incl.h
A429_EXCEPTION a429_start_io (int device_number)
Descript ion This function disables the specied ARINC device from performing bus opera-
tions by resetting the CMD register at offset 0x880.
Paramet ers The device_number parameter species the ARINC device to stop I/O.
Ret urn Value a429_start_io returns either A429_OK or A429_BAD.
See Also a429_put_ram, a429_start_io
Device Management and Low Level Routines C-31
C.3.27 a429_wait_a_millisecond
Pauses execution for the specied number of milliseconds.
Synt ax #include 429_incl.h
void a429_wait_a_millisecond (int wait)
Descript ion If the specied wait value is 0 or less, control is returned to the calling routine.
Otherwise, this routine loops until the specied number of milliseconds has
elapsed.
Paramet ers The wait parameter is the number of milliseconds to pause.
See Also a429_wait_a_second
C-32 A429 Standard Interface Libraries
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C.3.28 a429_wait_a_second
This routine pauses execution for the specied number of seconds.
Synt ax #include "429_incl.h
void a429_wait_a_second (int wait)
Descript ion If the specied wait value is 0 or less, control is returned to the calling routine.
Otherwise, this routine loops until the specied number of seconds have
elapsed.
Paramet ers The wait parameter is the number of seconds to pause.
See Also a429_wait_a_millisecond
BIT Management Routines C-33
C.4 BIT Management Rout ines
BIT Management functions are contained in bit_mgmt.c. This le provides a
procedure to run a Built-In-Test (BIT) on a specied ARINC 429 device. This
test should be run before any data structures are initialized.
C.4.1 429_bit (int device_number)
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_bit (int device_number)
Descript ion a429_bit executes all of the Built-In-Tests resident in the A429 rmware. In
order to execute this function, you must be in BIT mode. If not, the function
will exit and return to the calling routine.
Argument s The device_number parameter species the ARINC device on which to exe-
cute the Built-In-Tests.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_put_ram, a429_get_ram
C-34 A429 Standard Interface Libraries
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C.5 Receive Management Rout ines
The rc_mgmt.c le contains functions that can be used to set up the ARINC 429
card to perform receive operations.
C.5.1 a429_create_rc_cb
Create a receiver control block.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_create_rc_cb (int device_number,
int channel_number,
A429_CHANNEL_SPEED speed,
A429_RC_SORT sort_type)
Descript ion a429_create_rc_cb creates a control block for a specied receive channel. It
sets the channel speed and sort type. Received words can either be sorted by
SDI and label or label only.
Argument s The device_number parameter species the device on which to create the receiv-
er control block. The channel_number parameter species the channel on the
ARINC device. The speed parameter determines the frequency of the receiver.
The frequency defaults to 100 KHz unless speed is set to A429_SLOW, in which
case the frequency is set to 12.5 KHz. The sort_type parameter determines how
the received words are sorted, either SORT_BY_SDI or SORT_BY_LABEL.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram,
a429_malloc_429
Receive Management Routines C-35
C.5.2 a429_set_rc_control
Sets the receiver control word.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_set_rc_control(int device_number,
intchannel_number,
UWORD control_word)
Descript ion This function writes the control_word to the receive channels Receive Con-
trol Word (RCVCW).
Argument s The device_number parameter species the device on which to set the receiver
control word. The channel_number parameter species the channel on the
ARINC device. The control_word parameter is the 16-bit word written to off-
set 01h (RCVCW) in the receive rmware data structure.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram
C-36 A429 Standard Interface Libraries
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C.5.3 a429_start_rc
Starts receiver operations.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_start_rc(int device_number,
int channel_number)
Descript ion This function enables receiver operations for a specied receive channel by set-
ting bit 0 of the receiver control word (RCVCW) to 1. RCVCW is located at offset
01h in the receive rmware data structure.
Argument s The device_number parameter species the device on which to start receiver
operations. The channel_number parameter species the channel on the
ARINC device.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram, a429_stop_rc
Receive Management Routines C-37
C.5.4 a429_stop_rc
Stops receiver operations.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_stop_rc(int device_number,
int channel_number)
Descript ion This function halts receiver operations for a specied receive channel by setting
bit 0 of the receiver control word (RCVCW) to 0. RCVCW is located at offset 01h
in the receive rmware data structure.
Argument s The device_number parameter species the device on which to stop receiver
operations. The channel_number parameter species the channel on the
ARINC device.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram,
a429_start_rc
C-38 A429 Standard Interface Libraries
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C.5.5 a429_get_current_value
Reads the last received word.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_get_current_value (int device_number,
int channel_number,
UWORD label,
UWORD *value
Int nSwap)
Descript ion This routine sets the swap bit in the RCVCW word (offset 01h) to 1 and reads
the current values of the last received word and its three associated time stamp
words.
Argument s The device_number parameter species the device from which to read the last
received word. The channel_number parameter species the channel on the
ARINC device. The label parameter is sdi/label. The value parameter is a
pointer to an array in which the current value and time stamp are written. The
nSwap parameter is set to non-zero to force a buffer swap.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_get_ram, a429_put_ram
Receive Management Routines C-39
C.5.6 a429_init_lter_table
Initializes the lter table.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_init_filter_table (int device_number,
int channel_number,
UWORD flag,
UBYTE value)
Descript ion a429_init_filter_table initializes a global or channel lter table to a spec-
ied 8-bit value. Entries in a lter table govern interrupts and sequential mon-
itoring for each possible receive SDI and/or label and are packed on 8-bit
boundaries. Even labels occupy the eight least signicant bits and odd labels
occupy the eight most signicant bits.
Argument s The device_number parameter species the device on which to initialize the l-
ter table. The channel_number parameter species the channel on the ARINC
device. The flag parameter indicates whether it is a global or channel lter
table (0 = Global, 1 = Channel). The value parameter is the 8-bit value to write
to the table.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram,
a429_set_filter_table
C-40 A429 Standard Interface Libraries
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C.5.7 a429_set_lter_table
Writes a value to a lter table.
Synt ax #include "429_incl.h
429_EXCEPTION a429_set_filter_table (int device_number,
int channel_number,
UWORD label,
UWORD flag,
UBYTE value)
Descript ion a429_set_filter_table writes a value to a global or channel lter table for a
specied label. The label passed is the offset into the table. Entries in a lter
table govern interrupts and sequential monitoring for each possible receive SDI
and/or label and are packed on 8-bit boundaries. Even labels occupy the eight
least signicant bits and odd labels occupy the eight most signicant bits.
Argument s The device_number parameter species the device on which to write to the l-
ter table. The parameter channel_number species the channel on the ARINC
device. The label parameter is a raw SDI label. The flag parameter indicates
whether it is a global or channel lter table (0 = Global, 1 = Channel). The val-
ue parameter is the 8-bit value to write to the table.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_get_ram, a429_put_ram,
a429_init_filter_table
Receive Management Routines C-41
C.5.8 a429_convert_label
Converts a label to or from a bit-swapped value.
Synt ax #include "429_incl.h"
UBYTE a429_convert_label (UBYTE value)
Descript ion Per ARINC specications, the label has a reversed bit order. (For example,
label AAh is transmitted as 55h.) Labels are bit swapped prior to being stored
in the current value buffer This routine converts a label to or from a bit-
swapped value.
Argument s The value parameter is the value to be converted.
Ret urn Value a429_convert_label returns the converted label.
C-42 A429 Standard Interface Libraries
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C.6 Transmit Management Rout ines
The tx_mgmt.c le contains functions that are used to set up an ARINC 429 card
to perform transmit operations.
C.6.1 a429_initialize_chain_pointers
Initializes the chain head and tail pointer arrays.
Synt ax #include "429_incl.h"
static void a429_initialize_chain_pointers (void)
Descript ion The rst time this function is called, the chain head pointer and tail pointer ar-
rays are initialized to NULL.
Transmit Management Routines C-43
C.6.2 a429_create_tx_cb
Creates a transmit control block.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_create_tx_cb(int device_number,
int channel_number,
A429_CHANNEL_SPEED speed,
UWORD minor_frame_count,
UWORD major_frame_count,
UWORD gap_time)
Descript ion a429_create_tx_cb creates a control block for a specied transmit channel. It
sets the transmitter speed, major frame count, minor frame count, and the inter-
word gap time.
Argument s The device_number parameter species the device on which to create the trans-
mit control block. The channel_number parameter species the channel on the
ARINC device. The speed parameter determines the frequency of the transmit-
ter. The frequency defaults to 100 KHz unless speed is set to A429_SLOW, in
which case the frequency is set to 12.5 KHz. The minor_frame_count param-
eter indicates the number of desired minor frames and the major_frame_count
parameter indicates the number of desired major frames. The gap_time param-
eter species the interword gap time in microseconds.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_create_rc_cb, a429_halt_cb,
a429_add_tx_cmd, a429_load_chain
C-44 A429 Standard Interface Libraries
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C.6.3 a429_halt_cb
Halts the control block for a specied channel.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_halt_cb(int device_number,
int channel_number)
Descript ion This function halts the control block of an ARINC channel by setting the halt
bit (bit 0) of the command block control word (CMDBCW) for a transmit channel
or the receive control word (RCVCW) for a receive channel. CMDBCW is located at
offset 01h in the transmit control block rmware structure and RCVCW is located
at offset 01h in the receive rmware data structure.
Argument s The device_number parameter species the device on which to halt the control
block. The channel_number parameter species the channel on the ARINC de-
vice.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_create_rc_cb, a429_create_tx_cb,
a429_add_tx_cmd, a429_load_chain
Transmit Management Routines C-45
C.6.4 a429_add_mf_cmd_blk
Adds or creates a minor frame command block.
Synt ax #include "429_incl.h"
UWORD a429_add_mf_cmd_blk (int device_number,
UWORD chain_id,
ULONG frame_time,
int loop_flag,
UWORD command_type
Descript ion This function adds a minor frame to an existing chain of minor frame and trans-
mit command blocks. If no minor frames exist, a new chain is created.
Argument s The device_number parameter species the device on which to add the minor
frame command block. The channel_number parameter species the channel
on the ARINC device. The chain_id parameter species the number of the
chain to create or manipulate. The frame_time parameter indicates the time in
microseconds allotted for a minor frame. The loop_flag parameter can be ei-
ther TRUE or FALSE; set it to TRUE to loop through the chain. The command_type
parameter indicates the Minor Frame Command type.
Ret urn Value a429_add_mf_cmd_blk returns a pointer (offset from the base address of the
card) to the command block or NULL.
See Also a429_initialize_chain_pointers
C-46 A429 Standard Interface Libraries
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C.6.5 a429_add_tx_cmd_blk
Adds a transmit command block to a chain.
Synt ax #include "429_incl.h"
UWORD a429_add_tx_cmd_blk (int device_number,
UWORD chain_id,
ULONG scheduled_time,
UWORD xmit_count,
UWORD start_frame,
UWORD repeat_rate,
int loop_flag,
UWORD transmit_type,
UWORD *pData)
Descript ion a429_add_tx_cmd_blk adds a transmit command block to an existing chain of
minor frame and transmit command blocks.
Argument s The device_number parameter species the device on which to add the trans-
mit command block. The chain_id parameter species the number of the chain
to create or manipulate. The scheduled_time parameter indicates the time in
microseconds that must expire before the transmit command block is processed.
The xmit_count parameter indicates the number of data words to transmit for
the associated command block. The start_frame parameter indicates in
which frame the transmit command block will begin executing. The
repeat_rate parameter indicates how often to process a transmit command
block after the start_frame parameter is met. The loop_flag parameter can
be either TRUE or FALSE; set it to TRUE to loop through the chain. The
transmit_type parameter indicates to the rmware that it is a transmit type
command block. The pData parameter is a pointer to the associated data buffer
for the transmit command block.
Ret urn Value This function returns a pointer (offset from the base address of the card) to the
command block or NULL.
See Also a429_initialize_chain_pointers
Transmit Management Routines C-47
C.6.6 a429_load_chain
Loads a chain for execution.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_load_chain (int device_number,
int channel_number,
UWORD chain_id)
Descript ion The a429_load_chain function prepares a chain program for execution by
loading a pointer to the rst command block into the CBIPTR word (offset 02h).
A chain can be constructed using a429_add_tx_cmd_blk or
a429_add_mf_cmd_blk.
Argument s The device_number parameter species the ARINC device on which to load
the chain. The channel_number parameter species the channel on the ARINC
device. The chain_id parameter species the number of the chain to load.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_channel_address, a429_add_tx_cmd_blk,
a429_add_mf_cmd_blk
C-48 A429 Standard Interface Libraries
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C.6.7 a429_read_type_word
Reads a minor frame/transmit type word.
Synt ax #include "429_incl.h"
UWORD a429_read_type_word (int device_number,
UWORD p_xmit_tcb)
Descript ion a429_read_type_word reads the minor frame/transmit type word of a com-
mand block.
Argument s The device_number parameter species the ARINC device on which to read a
type word. The p_xmit_tcb parameter is a pointer to a transmit command
block.
Ret urn Value This routine returns the transmit type word or 0 if an error occurs.
See Also a429_write_type_word
Transmit Management Routines C-49
C.6.8 a429_write_type_word
Writes a minor frame/transmit type word.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_write_type_word (int device_number,
UWORD p_xmit_tcb,
UWORD typeword
Descript ion a429_write_type_word writes the minor frame/transmit type word of a com-
mand block.
Argument s The device_number parameter species the ARINC device on which to write a
type word. The p_xmit_tcb parameter is a pointer to a transmit command
block. The typeword parameter species the type word to be written.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_read_type_word
C-50 A429 Standard Interface Libraries
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C.6.9 a429_write_tx_cb_data
Writes chain link transmit data.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_write_tx_cb_data (int device_number,
UWORD p_xmit_cb,
UWORD xmit_count,
UWORD *p_data)
Descript ion This function gets the address of the data buffer from the Transmit Control
Block and then writes the data to a chain link transmit data buffer. Note that
there are three words for each Transmit entry.
Argument s The device_number parameter species the ARINC device on which to write
transmit data. The p_xmit_tcb parameter is a pointer to a transmit command
block. The xmit_count parameter species the number of data words to trans-
mit. The *p_data parameter is a pointer to the array of data to be written.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_create_tx_cb
Monitor Management Routines C-51
C.7 Monit or Management Rout ines
The mon_mgmt.c le contains functions that create and read sequential monitor
buffers.
C.7.1 a429_create_global_sm_buffers
Creates global sequential monitor buffers.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_create_global_sm_buffers(int device_number,
int buffer_count,
UWORD buffer_size,
int loop_flag)
Descript ion This function creates the specied number of global sequential monitor buffers
in upper memory. A global monitor lter table is used to lter received words
by label.
Argument s The device_number parameter species the ARINC device on which to create
the global sequential monitor buffers. The buffer_count parameter indicates
the number of buffers to create. Two or more buffers must be dened for proper
monitor operation. The buffer_size parameter is the size, in words, of the glo-
bal monitor buffer. If the parameter loop_flag (1=loop, 0=snapshot) is set, the
buffer chain will loop back to the rst buffer.
Ret urn Value a429_create_global_sm_buffers returns either A429_OK or A429_BAD.
See Also a429_add_global_sm_buffer
C-52 A429 Standard Interface Libraries
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C.7.2 a429_add_global_sm_buffer
Adds a buffer to an existing global sequential monitor buffer chain.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_add_global_sm_buffer (int device_number,
UWORD buffer_size,
int loop_flag)
Descript ion a429_add_global_sm_buffer adds a buffer to the end of the global sequential
monitor buffer chain.
Argument s The device_number parameter species the ARINC device on which to add a
global monitor buffer. The buffer_size parameter is the size, in words, of the
global monitor buffer to be added. The new buffer is added to the end of the
existing monitor buffer chain. If the parameter loop_flag (1=loop, 0=snap-
shot) is set, the buffer chain will loop back to the rst buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_create_global_sm_buffers, a429_read_global_sm_buffers
Monitor Management Routines C-53
C.7.3 a429_create_channel_sm_buffers
Creates the channel sequential monitor buffers.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_create_channel_sm_buffers (int
device_number,
int buffer_count,
UWORD buffer_size,
int loop_flag)
Descript ion This function creates the specied number of channel sequential monitor buff-
ers in upper memory for each of the receive channels congured on the card. All
sequential monitor structures are dened above offset 0x10800. A channel
monitor lter table is used to lter received words by label.
Argument s The device_number parameter species the ARINC device on which to create
the channel monitor buffers. The buffer_count parameter indicates the num-
ber of buffers to create on each receive channel. Two or more buffers must be
dened for proper monitor operation. The buffer_size parameter species the
size, in words, of the channel monitor buffer. If the parameter loop_flag
(1=loop, 0=snapshot) is set, the buffer chain will loop back to the rst buffer.
Ret urn Value a429_create_channel_sm_buffers returns either A429_OK or A429_BAD.
See Also a429_get_num_receive_channels, a429_add_channel_sm_buffers
C-54 A429 Standard Interface Libraries
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C.7.4 a429_add_channel_sm_buffers
Adds a buffer to the channel sequential monitor chain for the specied channel.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_add_channel_sm_buffer(int device_number,
int channel_number,
UWORD buffer_size,
int loop_flag)
Descript ion Adds a buffer to the channel sequential monitor buffer chain for the specied
channel.
Argument s The device_number parameter species the ARINC device on which to add a
channel monitor buffer. The parameter channel_number species the channel
on which to add the channel monitor buffer. The buffer_size parameter spec-
ies the size, in words, of the channel monitor buffer to be added. The new buff-
er is added to the end of the existing channel monitor buffer chain. If the
parameter loop_flag (1=loop, 0=snapshot) is set, the buffer chain will loop
back to the rst buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_create_channel_sm_buffers
Monitor Management Routines C-55
C.7.5 a429_add_sm_buffer_to_channels
Adds a buffer to each of the existing channel sequential monitor chains.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_read_global_sm_buffers (int device_number,
UWORD *data_buffer,
int buffer_size)
Descript ion This function adds a buffer to each of the existing channel sequential monitor
buffer chains.
Argument s The device_number parameter species the ARINC device on which to add the
channel monitor buffers. The *data_buffer parameter is a pointer to the users
receive data buffer that is to be added. The new buffer is added to the end of the
existing monitor buffer chain. The buffer_size parameter indicates the size,
in bytes, of the users buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
C-56 A429 Standard Interface Libraries
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C.7.6 a429_read_global_sm_buffers
Reads the last global sequential buffer written.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_read_global_sm_buffers (int device_number,
UWORD *data_buffer,
int buffer_size)
Descript ion This function reads the global monitor buffer pointed to by the GMLPTR software
control register (offset 8ACh).
Argument s The device_number parameter species the ARINC device on which to read
the last global buffer. The *data_buffer parameter is a pointer to the users
receive data buffer. The buffer_size parameter indicates the size, in bytes, of
the users buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_create_global_sm_buffers, 429_add_global_sm_buffers
Monitor Management Routines C-57
C.7.7 a429_read_channel_sm_buffers
Reads the last channel sequential monitor buffer written.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_read_channel_sm_buffers (int device_number,
int channel_number,
UWORD *data_buffer,
int buffer_size)
Descript ion This function reads the channel monitor buffer pointed to by the CMLPTR soft-
ware control register (offset 04h from the base of the channel control table).
Argument s The device_number parameter species the ARINC device on which to read
the last channel buffer. The channel_number parameter species the channel on
the ARINC device. The *data_buffer parameter is a pointer to the users re-
ceive data buffer. The buffer_size parameter indicates the size, in bytes, of
the users buffer.
Ret urn Value This function returns either A429_OK or A429_BAD.
C-58 A429 Standard Interface Libraries
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C.7.8 a429_create_trigger_control_block
This routine creates a new trigger block.
Synt ax #include "429_incl.h"
UWORD a429_create_trigger_control_block (int device_number,
UWORD *pTCB)
Descript ion This function creates a new trigger control block (TCB) in low memory.
Argument s The device_number parameter species the ARINC device on which to create
a new trigger block. The pTCB parameter is a pointer to the trigger control block
array.
Ret urn Value a429_create_trigger_control_block either returns the pointer (offset from
the base address of the card) of the trigger control block in board memory or
NULL.
Diagnost ics A call is made to A429_get_error_message() which will return
A429_OUT_OF_MEMORY.
See Also a429_load_trigger, a429_halt_trigger, a429_set_trigger_pointer
Monitor Management Routines C-59
C.7.9 a429_load_trigger
Loads a trigger chain program for execution.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_load_trigger (int device_number,
UWORD pTCB)
Descript ion This routine prepares a trigger chain program for execution by loading the
pointer to the rst control block in the chain into the TGIPTR software control
register (offset 8A4h).
Argument s The device_number parameter species the ARINC device on which to load a
trigger chain program. The pTCB parameter is a pointer to the trigger control
block.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_create_trigger_control_block, a429_halt_trigger,
a429_set_trigger_pointer
C-60 A429 Standard Interface Libraries
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C.7.10 a429_halt_trigger
Halts execution of the trigger chain program.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_halt_trigger (int device_number)
Descript ion This routine halts the execution of the trigger chain program by clearing the
TGIPTR software control register (offset 8A4h).
Argument s The device_number parameter species the ARINC device on which to halt the
trigger chain program.
Ret urn Value a429_halt_trigger returns either A429_OK or A429_BAD.
See Also a429_create_trigger_control_block, a429_load_trigger,
a429_set_trigger_pointer
Monitor Management Routines C-61
C.7.11 a429_set_trigger_pointer
Sets pointers to the next trigger control block (TCB).
Synt ax #include "429_incl.h"
void a429_set_trigger_pointer (int device_number,
UWORD pTCB,
UWORD pointerA,
UWORD pointerB)
Descript ion This routine sets the TRUE and FALSE path pointers to the next trigger control
block.
Argument s The device_number parameter species the ARINC device on which to set the
pointers. The pTCB parameter is a pointer to the trigger control block. The
pointerA parameter is the pointer to TRUE TCB and the pointerB parameter is
the pointer to FALSE TCB.
Ret urn Value This function returns either A429_OK or A429_BAD.
See Also a429_create_trigger_control_block, a429_halt_trigger,
a429_load_trigger
C-62 A429 Standard Interface Libraries
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C.8 Int errupt Management Rout ines
The int_mgmt.c le provides a set of procedures to manage interrupts generated
by the ARINC board.
C.8.1 a429_disable_interrupts
Disables the ARINC device host interrupts.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_disable_interrupts (int device_number)
Descript ion This function disables the ARINC device from generating host interrupts. In-
terrupts are disabled by clearing bit 3 of the Control/Status Register (CSR).
Argument s The device_number parameter species the ARINC device on which to disable
host interrupts.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_csr, a429_put_csr
Interrupt Management Routines C-63
C.8.2 a429_enable_interrupts
Enables the ARINC device host interrupts.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_enable_interrupts (int device_number)
Descript ion This function enables the ARINC device to generate host interrupts. Interrupts
are enabled by setting bit 3 of the Control/Status Register (CSR).
Argument s The device_number parameter species the ARINC device on which to enable
host interrupts.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_csr, a429_put_csr, a429_get_interrupt_vector
C-64 A429 Standard Interface Libraries
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C.8.3 a429_handle_interrupts
Handles interrupts generated by the ARINC device.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_handle_interrupts (int device_number)
Descript ion This function services interrupts generated by the ARINC device and is the main
interrupt handler for the device. It is called by an interrupt service routine (ISR).
Argument s The device_number parameter species the ARINC device on which to handle
interrupts.
Ret urn Value Returns either A429_OK or A429_BAD.
See Also a429_get_csr, a429_put_csr
Interrupt Management Routines C-65
C.8.4 a429_init_interrupt_queue
Creates and initializes the interrupt queue.
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_init_interrupt_queue (intdevice_number,
int number_of_entries)
Descript ion This routine sets the interrupt queue length and allocates memory for the queue.
Argument s The device_number parameter species the ARINC device on which to initial-
ize the interrupt queue. The number_of_entries parameter indicates the num-
ber of queue entries to allocate.
Ret urn Value This function returns either A429_OK or A429_BAD.
C-66 A429 Standard Interface Libraries
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C.8.5 a429_get_interrupt_log_count
Returns the number of interrupts.
Synt ax #include "429_incl.h"
int a429_get_interrupt_log_count (void)
Descript ion This routine returns the number of interrupts that have been logged.
Ret urn Value a429_get_interrupt_log_count returns the number of interrupts that have
been logged (int_index).
Interrupt Management Routines C-67
C.8.6 a429_get_interrupt_log_entry
Synt ax #include "429_incl.h"
A429_EXCEPTION a429_get_interrupt_log_entry (int index,
USHORT *pBuffer)
Descript ion This routine takes an index and a pointer to a 4-element USHORT array and puts
the interrupt log entry for that index into the users buffer.
Argument s The index parameter indicates the device number. The pBuffer parameter is a
pointer to a 4-element USHORT array.
Ret urn Value The routine returns either A429_OK or A429_BAD.
C-68 A429 Standard Interface Libraries
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D-1
This chapter is currently under construction.
Please call SBS technical support toll free at 1-877-TECHSBS with any
questions.
D: Oper at i ng Syst em Speci c Inf or mat i on
D-2 Operating System Specic Information
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Library Reference Table of Contents E-1
E.1 Library Ref erence Table of Cont ent s
Unit Test Application ............................................................................ 2
Using the Unit Test Application ........................................................................3
Device Management Package ...........................................................................4
Interrupt Management Package ........................................................................7
Transmit Management Package ........................................................................8
Receive Management Package ........................................................................10
Bus Monitor Management Package ................................................................12
Sample Applications ........................................................................... 14
Brief Overview of the Sample ARINC 429 Applications ...............................14
Building the Sample Application(s) ................................................................16
Conguring the Sample Application(s) for Execution ....................................17
E: ARINC 429 St andar d Uni t Test
E-2 ARINC 429 Standard Unit Test
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E.2 Unit Test Applicat ion
The Unit Test application uses the ARINC-429 library to provide basic ARINC-
429 bus operations and the ability to exercise the library subprograms. The li-
brary requires some conguration and tuning which is dependent on the target
hardware and operating system. Since the Unit Test application is a level above
the library, conguring and tuning should not be required.
Unit Test uses ANSI escape sequences to control output to the screen. You must
have an ANSI compatible terminal or driver. For PC systems, check your con-
g.sys le and make sure the ansi.sys driver is installed. There should be a line
that reads: DEVICE=C:\DOS\ANSI.SYS. Add this line if it is not present and re-
boot your computer.
The unit test application source code must be compiled and linked with the
ARINC-429 library. Required les for the C ARINC-429 library are listed in
Table E.2.1.
Table E.2.1: Unit Test Files
The distribution format for the unit test application les is illustrated below:
File Name Description
unit_test.c Main procedure of the Unit Test Application
crt_io.c General screen input and output routines
dev_test.c Routines that test the device management routines in dev_mgmt.c
rc_test.c Routines that test the receive management routines in rc_mgmt.c
int_test.c Routines that test the Interrupt management routines in int_mgmt.c
mon_test.c Functions that tests all monitor routines
tx_test.c Routines that test the transmit management routines in tx_mgmt.c
\unittest
\borland
\ms
\msdos
\win_16
\win_95
\win_nt
\msdos
\win_16
\win_95
\win_nt
Unit Test Application E-3
Files required to a create a Borland or Microsoft project are located under each
operating system subdirectory for the respective compiler.
E.2.1 Using the Unit Test Application
To run unit_test, type unit_test <CR> at your command prompt.
The following screen will be displayed:
Figure E.2.1: Unit Test Main Menu
This application is divided into ve sections:
Table E.2.2: Sections of Unit Test Application
unit_test.c main() displays the main menu shown in Figure E.2.1 and waits
for the user to make a menu selection.
Menu Selection Description Function Call
1 Device Management dev_test()
2 Interrupt Management int_test()
3 Transmit Management tx_test()
4 Receive Management rc_test()
5 Bus Monitor Management mon_test()
E-4 ARINC 429 Standard Unit Test
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E.2.2 Device Management Package
Type 1<CR> at the main menu prompt to branch to the Device Management
menu illustrated in Figure E.2.2.
Figure E.2.2: Device Management Menu
Device Management provides several general routines that initialize and set up
the board. A description of each choice is listed below:
Unit Test Application E-5
Table E.2.3: Device Management Menu Options
Menu
Selection
Description Function(s) Called
1 Performs initialization functions. On
the call to a429_init_device,
the ARINC 429 device is opened and a
write/read test is performed to verify
that the card is present. The firmware is
loaded into board ram, tables are initial-
ized, the firmware is started in applica-
tion mode, and the interrupt queue is
initialized.
a429_init_device
a429_get_error_msg
a429_create_global_sm_buffe
rs
a429_create_channel_sm_buff
ers
2 Opens one ARINC device for access. a429_open_device
3 Closes the device. a429_close_device
4 Loads the data ram and instruction RAM
files to the ARINC device.
a429_is_device_open
a429_load_ram
5 Starts operations on the ARINC-429 bus
by writing a nonzero value to RAM at
offset 880h.
a429_is_device_open
a429_start_io
6 Stops operations on the ARINC-429 bus
by writing a 0 to RAM at offset 880h.
a429_is_device_open
a429_stop_io
7 Starts the execution of the firmware by
switching from BIT mode to application
mode.
a429_is_device_open
a429_start_application
8 Runs diagnostic BIT tests. a429_is_device_open
a429_bit
9 Performs a soft reset on the system. a429_is_device_open
a429_soft_reset
c Gets information for a specified chan-
nel.
a429_is_device_valid
a429_get_num_channels
a429_get_channel_address
a429_get_ram
d Gets the device record for a selected de-
vice and then displays the device record
information.
a429_is_device_open
a429_get_device_record
r Displays a 128-word block of RAM on
the ARINC-429 device beginning at a
user specified offset. Figure 3 illustrates
a 128-block of RAM beginning at offset
880h.
ram_io (device_number);
dev_print_menu();
q Returns to the main menu
E-6 ARINC 429 Standard Unit Test
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If an error occurs, a message will be displayed at the Message prompt. The se-
lection chosen by the user is displayed at the Selection prompt. Initialize the
ARINC-429 board following the steps below.
Init ializing t he
Device
1. Type 1<CR> at the De vice Manage me nt me nu to e xe cute a full de vice
initialization proce dure .
This routine prompts the use r for the information be low.
Device Number? 1<CR>
The device number corresponds to the board channel you wish to open.
Interrupt Queue Length[4]? 4<CR>
Note: The inte rrupt que ue le ngth is use r se le ctable but must
be a minimum of 4.
After receiving responses to the prompts, the initialize routine makes a call to
a429_init_device. This routine prompts the user for the information below.
#of Global SM Buffers? [2]? <CR> (Selects the default of 2)
Global Monitor Length [4096]? <CR> (Selects the default of 4096)
Loop [Y]? >
If the call is not successful, the following message will be displayed:
Initialize ARINC device failed!
2. The initialize routine make s a call to a429_create_global_sm_buffers.
This routine prompts the use r for the information be low.
#of Channel SM Buffers [2]? >
Channel Buffer Length [256]? >
Loop [Y]? >
If the call is not successful, the following message will be displayed:
Create Global Monitor Buffers Failed!
3. The initialize routine calls the a429_create_channel_sm_buffers
function.
If the call is not successful, the following message will be displayed:
Create Channel SM Buffers Failed!
Unit Test Application E-7
Read/Writ e RAM Read/Write RAM displays a 128-word block of RAM on the A429 device
beginning at a user supplied offset. After initializing the board and performing
a Start ARINC I/O (Option #3), memory will be displayed. Figure E.2.3
illustrates a 128-block of RAM beginning at offset 880h.
Figure E.2.3: Read/ Write RAM Page
This function may also be used to modify memory.
E.2.3 Interrupt Management Package
Type 2<CR> at the main menu prompt to branch to the Interrupt
Management menu illustrated in Figure E.2.4.
Figure E.2.4: Interrupt Management Menu
E-8 ARINC 429 Standard Unit Test
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Interrupt Management provides several routines that initialize and handle the
ARINC interrupts. Menu selections are described in Table E.2.4.
Table E.2.4: Interrupt Management Menu Options
E.2.4 Transmit Management Package
Type 3<CR> at the main menu prompt to branch to the Interrupt
Management menu illustrated in Figure E.2.5.
Figure E.2.5: Transmit Management Menu
Transmit Management provides several routines that handle maintenance of a
Transmit Control Block. Table E.2.5 details the menu selections.
Menu
Selection
Description Function(s) Called
1 Initializes the interrupt queue, sets the
interrupt queue length, and allocates
memory for the queue. This function
prompts you for the following param-
eters: Device Number and Queue
Length.
a429_init_interrupt_queue
2 Disables ARINC interrupts. a429_disable_interrupts
3 Enables ARINC interrupts. a429_enable_interrupts
4 Handles the ARINC interrupt queue.
This function prompts you for the fol-
lowing parameters: Device Number
and Interrupt Index.
a429_handle_interrupts
a429_get_interrupt_log_entry
r Read and writes to RAM (Figure 3
illustrates a 128-block of RAM begin-
ning at offset 880h.
ram_io()
q Returns to the main menu.
Unit Test Application E-9
Table E.2.5: Transmit Management Menu Options
Menu
Selection
Description Function(s) Called
1 Creates a transmit control block. This func-
tion prompts you for the following parame-
ters: Number of major frames, Number of
minor frames, Inner Word gap(sec), and
Transmit speed (KHz). All this information is
required to create the data structure for the
control block.
a429_get_num_receive_channels
a429_get_num_channels
a429_create_tx_cb
2 Adds a minor frame control block. This func-
tion prompts you for the following parame-
ters: Chain ID, Minor Frame Time
(seconds), Loop (Y/N) and Command Type
(hex).
a429_add_mf_cmd_blk
3 Adds a transmit control block. This function
prompts you for the following parameters:
Device Number, Chain ID, Scheduled Time
(seconds), Transmit Word Count, Minor
Frame to execute, Repetition Rate, Loop
Chain (Y/N), and Command Type (hex).
Function allocates the data buffer and fills the
data structure with an easily-recognizable
pattern. It then calls the
a429_add_tx_cmd_blk function.
4 Load Chain. This function prompts you for
the following parameters: Device Number,
Channel Number and Chain ID
a429_load_chain
5 Halt Tx Control Block. In order to halt the
Transmit Control Block, you must provide the
Device Number and Channel Number param-
eters.
a429_halt_cb
6 Read Type Word reads the minor frame/trans-
mit type word for a specified command block.
This function prompts you for the following
parameters: Device Number, Transmit CB
address (hex), and Type Word.
a429_read_type_word
7 Write Type Word tests writing the minor
frame/transmit type word for a command
block. This function prompts you for the fol-
lowing parameters: Device Number, Trans-
mit CB address (hex), and Type word
a429_write_type_word
8 Write TX CB Data. This routine tests writing
data to a chain link transmit data buffer. This
function prompts you for the following pa-
rameters: Device Number, Transmit Com-
mand Block Address (hex), Word Count. The
function then attempts to allocate a buffer
large enough to hold the count requested.
You will be prompted for Transmit Control
Word [0x0000], Transmit Low Data Word
[0x0000], and Transmit High Data Word
[0x0000]
a429_write_tx_cb_data
r Read/Write RAM. Reads and writes to RAM.
Figure 3 illustrates a 128-block of RAM be-
ginning at offset 880h.
ram_io
q Returns to the main menu.
E-10 ARINC 429 Standard Unit Test
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E.2.5 Receive Management Package
Type 4<CR> at the main menu prompt to branch to the Receive
Management menu illustrated in Figure E.2.6.
Figure E.2.6: Receive Management Menu
Receive Management provides several routines that handle maintenance and
operations of a Receive Control Block. Table E.2.6. details the menu selections.
Unit Test Application E-11
Table E.2.6: Receive Management Menu Options
Menu
Selection
Description Function Called
1 Create RC Control Block tests creating a re-
ceiver control block for a receive channel.
This function prompts you for the following
parameters: Device number, Channel Num-
ber, Sort Type (Enter [1] SDI/Data or [2] La-
bel), and Transmit Speed (KHz): (Enter [1]
12.5 or [2] 100).
a429_is_device_open
a429_get_num_receive_channels
a429_create_rc_cb
2 Setup RC Control Word sets the receiver
control word (RCVCW). This function
prompts you for the following parameters:
Device Number, Channel Number, Swap
Current Values [y/n], Interrupt on Swap [y/
n], Force Monitor Swap [y/n], Restart Mon-
itor [y/n], and Interrupt on Error [y/n],
a429_is_device_open
a429_get_num_receive_channels
a429_set_rc_control
3 Start RC Operation tests enabling a receive
channel. This function prompts you for the
following parameters: Device Number and
Channel Number.
a429_is_device_open
a429_get_num_receive_channels
a429_ start_rc
4 Halt RC Control Block disables a receive
channel. This function prompts you for the
following parameters: Device Number and
Channel Number,
a429_is_device_open
a429_get_num_receive_channels
a429_stop_rc
5 Get Current Values tests reading the last re-
ceived word and its three time stamps. This
function prompts you for the following pa-
rameters: Device Number and SDI/Label?
The function then either displays the value
or returns an error message
a429_get_current_value
6 Initialize Filter Table initializes an entire
global or channel filter table to a given val-
ue. This function prompts you for the fol-
lowing parameters: Device Number, Global
(0) or Channel (1), Channel Number, and
Value [0x00] (This is the value to initialize.)
a429_init_filter_table
7 Set Filter Table Values writes a value to a
global or channel filter table for a given la-
bel. This function prompts you for the fol-
lowing parameters: Device Number, Label,
Global (0) or Channel (1), Channel Number
and Value [0x00].
a429_set_filter_table
8 Convert Label tests converting a label to or
from a bit-swapped value. This function
prompts you for the following parameters:
Value to convert (hex). The function then
displays the value returned.
a429_convert_label
r Read/Write RAM. Reads and writes to
RAM. Figure 3 illustrates a 128-block of
RAM beginning at offset 880h.
ram_io()
q Return to the Main Menu.
E-12 ARINC 429 Standard Unit Test
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E.2.6 Bus Monitor Management Package
Type 5<CR> at the main menu prompt to branch to the Monitor
Management menu illustrated in Figure E.2.7.
Figure E.2.7: Monitor Management Menu
Monitor Management provides several routines that handle maintenance of
Channel SM Buffers, Channel Global Buffers, and Trigger Control Blocks.
Each menu choice is described in Table E.2.7.
Unit Test Application E-13
Table E.2.7: Bus Monitor Management Menu Options
Menu
Selection
Description Function(s) Called
1 Create Channel SM Buffers tests creating channel
sequential monitor buffers for a receive channel.
This function prompts you for the following param-
eters: Device Number, Number of Buffers [2], and
Buffer Length [256] and whether or not to Loop
[Y].].
a429_create_channel_sm_buffers
2 Add Channel SM Buffer adds a buffer to the channel
sequential monitor buffer chain. This function
prompts you for the following parameters: Device
Number, Channel number [1], Buffer Length [256]
and whether or not to Loop [Y].
a429_add_channel_sm_buffer
3 Create Global SM Buffers tests creating global se-
quential monitor buffers. This function prompts you
for the following parameters: Device Number,
Number of Buffers [2], Monitor Length [4096], and
Loop [Y].
a429_create_global_sm_buffers
4 Add Global SM Buffer adds a buffer to the global
sequential monitor buffer chain. This function
prompts you for the following parameters: Device
Number, Buffer Length [256], and Loop [Y].
a429_add_global_sm_buffer
5 Read Channel SM Buffer reads the last Global Mon-
itor Buffer written to for a specific channel. This
function prompts you for the following parameters:
Device Number and Channel number [1]
a429_read_channel_sm_buffers
6 Read Global SM Buffer reads the last Global Moni-
tor Buffer written to. This function prompts you for
the following parameter: Device Number.
a429_read_global_sm_buffers
7 Create Trigger Control Block tests creating a new
trigger block. This function prompts you for the fol-
lowing parameters: Device Number, Type [0x0000]
(Type Word), Channel [1], High Mask [0xffff], Low
Mask [0xffff], High Value [0x0000], Low Value
[0x0000], Event Count [1], A Pointer [0x0000], and
B Pointer [0x0000].
a429_create_trigger_control_block
8 Set Trigger Pointers sets the TRUE (A Pointer) and
FALSE (B Pointer) path pointers to the next trigger
control block. This function prompts you for the
following parameters: Device Number, TCB Point-
er, A Pointer [0x0000], and B Pointer [0x0000]
a429_set_trigger_pointer
9 Load Trigger prepares a trigger chain program for
execution by loading the pointer to its first control
block into TGIPTR. This function prompts you for
the following parameters: Input Device Number,
TCB Pointer, and whether Trigger at Start, Middle,
or End [S]
a429_load_trigger
0 Halt Trigger tests halting the execution of the trigger
chain program by clearing TGCPTR. This function
prompts you for the following parameter: Device
Number.
a429_halt_trigger
r Read/Write RAM Figure 3 illustrates a 128-block
of RAM beginning at offset 880h.
ram_io
q Return to the Main Menu
E-14 ARINC 429 Standard Unit Test
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E.3 Sample Applicat ions
The ARINC 429 Standard Libraries are shipped with sample ARINC 429 appli-
cations. These applications utilize the libraries to perform basic ARINC 429
operations and are intended as learning tools for rst time users and trouble-
shooting tools for more advanced users.
E.3.1 Brief Overview of the Sample ARINC 429 Applications
A number of sample applications are included with the ARINC 429 Standard
Libraries. A program description is presented in Table E.3.1.
Sample Applications E-15
Table E.3.1: Description of Sample ARINC 429 Applications
Name Description
interupt.c This application tests the int_mgmt.c routines by performing the following
steps: initializes Device 1, creates buffers for global and channel sequential
monitoring, starts I/O, creates a receive control block for Channel 1, initializes
the global filter table to receive every label and generate an interrupt, initializes
the channel filter table to receive only Label 1 and generate an interrupt, starts
the receiver for Channel 1, enables interrupts for Device 1, allows 429 data to
be received for 10 seconds, then retrieves and displays the data in the interrupt
queue. This application requires the use of an external device, such as a PASS-
1000, for data transmission.
receive.c This application tests the rc_mgmt.c routines by performing the following
steps: initializes Device 1, creates buffers for global and channel sequential
monitoring, starts I/O, creates a receive control block for Channel 1, initializes
the receiver control word, initializes the global filter table to receive every la-
bel, initializes the channel filter table to receive only Labels 0-9, starts the re-
ceiver for Channel 1, allows 429 data to be received for 10 seconds, then
retrieves and displays the data. This application requires the use of an external
device, such as a PASS-1000, for data transmission.
transmit.c This application tests the tx_mgmt.c routines by performing the following
steps: initializes Device 1, creates buffers for global and channel sequential
monitoring, starts I/O, creates a transmit control block for Channel 5, creates a
transmit command block for Chain 1, creates a minor frame command block
for Chain 1, loads Chain 1, then, after a 10-second pause, modifies the data to
1234h for all Labels. This application requires the use of an external device,
such as a PASS-1000, for data reception.
monitor.c This application tests the mon_mgmt.c routines by performing the following
steps: initializes Device 1, creates buffers for global and channel sequential
monitoring, starts I/O, creates a receive control block for Channel 1, initializes
the receiver control word, initializes the global filter table to receive every la-
bel, initializes the channel filter table to receive only Labels 0-9, starts the re-
ceiver for Channel 1, adds global and channel sequential monitor buffers,
creates three trigger control blocks in a chain, loads the chain, allows 429 data
to be received for 5 seconds, then retrieves and displays the first 100 words of
each monitor buffer. This application requires the use of an external device,
such as a PASS-1000, for data transmission.
test_all.c This application incorporates all four of the sample programs described above
into one program. A loop-back connector may be used (in lieu of an external
device) to accomplish the task of transmitting data on Channel 5 and receiving
data on Channel 1
E-16 ARINC 429 Standard Unit Test
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E.3.2 Building the Sample Application(s)
Follow the steps listed below to prepare a working directory for the sample ap-
plication(s).
1. Cre ate a working dire ctory.
2. Copy all the library le s and the rmware le (s) to the working dire ctory.
3. Se le ct the appropriate compilation dire ctive s in the 429_sys.h le .
4. Ve rify the value for A429_MAX_DEV in the 429_def.h le is e qual to or gre ate r
than the numbe r of de vice s to be te ste d.
5. Copy the de sire d sample application(s) to the working dire ctory.
6. Build the sample application e xe cutable (s) using one of the two proce dure s
liste d in Table E.3.2 or the proce dure liste d in Table E.3.3 if using DLLs.
Table E.3.2: Building the Sample Applications Using A-429 Standard Libraries
MSDOS, Windows 3.1, Windows 95, Windows NT
(Borland & Microsoft Compile rs)
1. Place the de sire d sample application file (s) (<sample >.c) in a proje ct file name d
<sample >.
2. Add the following file s to the <sample> proje ct:
bit_mgmt.c
dev_mgmt.c
int_mgmt.c
low_lvl.c
mon_mgmt.c
rc_mgmt.c
tx_mgmt.c
3. Compile and link the <sample> project.
4. Verify the executable <sample>.exe has been created.
Note: <sample> represents the sample application(s) you wish
to execute. The available applications are interupt, receive,
transmit, monitor, and test_all.
Sample Applications E-17
Table E.3.3: Build Procedure for the Sample Applications using DLLs
E.3.3 Conguring the Sample Application(s) for Execution
The following conguration must be completed in order for the A429 card to
function properly with the sample application(s).
a429dev.cf g
Congurat ion
Edit the a429dev.h le in the working directory and verify the settings are cor-
rect for the A429 card, the operating system, the rmware le(s), and the num-
ber of devices being used. If a setting is not applicable for the card or the
operating system being used, the line and accompanying comment line can be
deleted or the line can be commented out by placing a semi-colon (;) in the rst
character of the line.
MSDOS, Windows 3.1, Windows 95, Windows NT
(Borland & Microsoft Compile rs)
1. Copy the <dll>.dll and <dll>.lib file s to the working dire ctory.
2. Place the de sire d sample application file (s) (<sample>.c) in a proje ct file name d
<sample>.
3. Add the <dll>.lib file to the <sample> proje ct:
4. Edit the 429_sys.h file and uncomme nt the library DLL compile dire ctive s for
the compile r be ing use d.
5. Compile and link the <sample> proje ct.
6. Ve rify the e xe cutable <sample>.exe has be e n cre ate d.
Note: <sample> represents the sample application(s) you wish
to execute. The available applications are interupt, receive,
transmit, monitor, and test_all. <dll> is the DLL library. The
available DLLs are a42916.dll, a42995.dll, and a429nt.dll.
E-18 ARINC 429 Standard Unit Test
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Preface F-1
F.1 Pref ace
Unlike military standards, the ARINC 429 Specication is not a public docu-
ment. Aeronautical Radio, Inc. (ARINC) holds the copyright. Therefore, this
document will not reproduce any sections of the specication. However, this
document presents a commentary and review of the ARINC 429 Specication.
We have taken the liberty to reorganize aspects of the specication that are bet-
ter understood when grouped together as sections. The specic sections are:
Preface
About the ARINC Organization
Introduction To ARINC 429
Electrical Elements
Word And Protocol Methods
Summary
The specication itself contains numerous commentaries provided by the gov-
erning committee. These commentaries are intended to further explain or pro-
vide caveats to that particular area of the specication and are considered in this
commentary. Small commentary areas are incorporated into the discussion
while large areas are explicitly declared. This commentary is designed to pro-
vide you with a basic understanding of the ARINC 429 specication and bus
functionality.
This document provides an overview of the ARINC organization and the
ARINC 429 specication. There are three parts to the ARINC standard;
429P1-15, 429P2-15, and 429P3-15. The information contained within this
document represents an interpretation of ARINC 429P1-15. Separate docu-
ments contain reviews of 429P2-15 and 429P3-15. Please note, some of the
terminology used in ARINC documents is a bit ambiguous. To provide a better
understanding, this commentary introduces some new terminology.
F: An ARINC 429 Comment ar y
F-2 An ARINC 429 Commentary
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F.2 About t he ARINC Organizat ion
ARINC itself is not a standard nor is it a piece of equipment. ARINC is an ac-
ronym for Aeronautical Radio, INC. The ARINC organization is the technical,
publishing and administrative support arm for the Airlines Electronic Engineer-
ing Committee (AEEC) groups. The AEEC was formed in 1949 and is consid-
ered the leading international organization in the standardization of air transport
avionics equipment and telecommunication systems. AEEC standards dene
avionics form, t, function, and interfaces. The AEEC is comprised of 27 airline
and related organizations. Representatives have engineering, operational, and
maintenance experience within their organization.
ARINC specications are divided into four numbering systems and two basic
types. The numbering systems include the 400, 500, 600 and 700 series. The
groups are divided into general design requirements and terminal design stan-
dards (characteristics). General Design requirements include the 400 and 600
series of documents. Specic terminal design and testing criteria (characteris-
tics) are set forth in the 500 and 700 series. The 500 series dene older mostly
analog avionics equipment, many of which are still used in modern aircraft
with updated technologies. The 400 series documents are considered the gen-
eral design and supporting documents for the 500 series avionics equipment
characteristics. Similarly, the 600 series documents are considered the general
design and support documents for the 700 series of avionics equipment charac-
teristics. However, there may be some exceptions; sufce it to say that 700
series terminals are generally digital systems. The 500 and 700 are equipment
specic and among other things denes how the unit shall operate, including
the input and output pathways for digital and analog information.
ARINC standards dene design and implementation of everything from testing
requirements to NAV systems to in-ight entertainment. Some of the newer
specications cover digital systems, testing, development and simulation crite-
ria. Aside from the specications themselves, there are a number of subgroups,
other avionics organizations, and private manufacturers, all of whom publish
information regarding the implementation of avionics systems, e.g. the General
Aviation Manufacturers Association (GAMA) who denes subgroup function-
ality.
Some of the most prevalent ARINC standards are ARINC 419, ARINC 575,
ARINC 429, ARINC 615 and ARINC 629. Of course, numerous others exist
and many of the 500 series are considered obsolete. Generally, three specica-
tions dene the characteristics of avionics buses. These are ARINC 419,
ARINC 429 and ARINC 629. A few of the avionics terminal specications
dene their own unique bus architecture, such as ARINC 709 which includes a
high speed RADAR imaging bus. ARINC 419 is the oldest and is considered
obsolete. However, it is important from a maintenance viewpoint. The vast
majority of avionics terminals employ the usage of ARINC 429 for their avion-
ics bus. Currently, only the Boeing 777 employs the usage of ARINC 629.
Introduction To ARINC 429 F-3
F.3 Int roduct ion To ARINC 429
The
Predecessor:
ARINC 419
ARINC 419 is a collection of the various avionics buses in use at its creation.
The ARINC 419 specication was the rst digital communications specication
for commercial aviation. This specication was developed in 1966 and last up-
dated in 1983. ARINC 419 was created to provide a central point of reference
for the different variations of buses, providing both electrical and protocol dec-
larations. Although the 419 specication declares four different wire topologies
and clock rates between transmitter and receiver, all buses use a shout bus to-
pology (simplex) and the Label identication method for data words. The four
wire topologies are declared in Table F.3.1: ARINC 419 Topologies.
Table F.3.1: ARINC 419 Topologies
Among the four declared, the most widely known implementation of 419 is the
Serial; one twisted shielded pair topology used by the DADS system (known as
ARINC 575), followed by the six wire (three twisted shielded pairs).
DADS 575 Although ARINC 419 is no longer used in terminal design and is considered ob-
solete, the DADS 575 twisted shielded pair bus served as the model for the
ARINC 429 topology.
Note: In re trot de signs, it is not uncommon to still have the
re quire me nt to pe rform and/or monitor as an ARINC 419
DADS 575 LRU.
F.3.1 About the ARINC 429 Specication
ARINC 429 denes the Air Transport Industrys standard for the transfer of dig-
ital data between avionics systems. ARINC 429 is formally known as the
MARK 33 Digital Information Transfer System (DITS) specication. The cur-
rent release of the specication is known as ARINC 429-15 and is divided into
the three parts shown in Table F.3.2 on the following page.
Topology Description
Parallel One wire per bit
Six wire One clock, one data, one synch (3 twisted shielded pairs)
Serial One twisted shielded pair
Serial Coaxial cable
F-4 An ARINC 429 Commentary
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Table F.3.2: ARINC Specication Parts
Part 1 ARINC Specication 429P1-15, provides the Functional, Electrical Interface,
Label and Address Assignment and Word Format Descriptions.
Part 2 ARINC Specication 429P2-15, provides a list of discrete word bit assignments
in label order.
Part 3 ARINC Specication 429P3-15, describes protocol and message denitions for
data block and le transfer techniques.
The ARINC 429 Specication technology had its origins in the ARINC 419
Specication, Digital Data System Compendium and the DADS, 575 Speci-
cation. Unlike the 419 Specication, ARINC 429 denes a particular bus de-
sign and to be implemented widely across virtually all modern ARINC LRU
systems.
The 429
Transmission
Model
[Subsect ion 1.4]
The ARINC 429 specication describes the avionics bus as an open loop
transmission model. Typically, this type of bus is described as a simplex bus
with multiple receivers. Other terminology would refer to it as a shout or
broadcast bus. When looking at a 429 bus, the transmitting Line Replacable
Unit (LRU) is known as the source while each receiving LRU is known as a
sink. Any particular LRU may have multiple sources and/or sinks. A twisted
shielded pair carries the ARINC 429 signal and the sets of information are trans-
mitted at periodic intervals. The periodic interval of data transmission must be
sufcient to provide a minimal rate of change in the data, so that if a data set is
lost, the loss would be of little consequence. To detect errors, the specication
prescribes the use of odd parity indication and optional error checking.
Typically, a data set is composed of one word and consists of either Binary
(BNR), Binary Coded Decimal (BCD) or alphanumeric data encoded per ISO
Alphabet No. 5. ARINC 429 also provides for le data transfers which use more
than one word. The transfer of graphic text and symbols used for CRT maps and
other displays has not been dened.
Part ARINC Specification Description
1 429P1-15:
Functional Description, Electrical Interface, Label Assign-
ments, and Word Formats
2 429P2-15: Discrete Word Data Formats
3 429P3-15: File Data Transfer Techniques
Introduction To ARINC 429 F-5
A Specication,
Not a Standard
[Sections 1.1 - 1.3]
If you lack experience reading ARINC 429 documents, you should understand
that ARINC 429 documents are not standards; they are specications developed
to provide a high degree of interchangeability between common functional
units, typically known as Line Replaceable Units (LRUs). Although common
implementation was the purpose of the specication on all LRUs, manufacturers
are by no means required to comply.
F.3.2 ARINC 429P1-15 Specication
The ARINC 429 specication provides the electrical, timing, and protocol
requirements necessary to implement design and proper communication on the
MARK 33 DITS bus. ARINC 429 is implemented as a simplex, broadcast bus.
The ARINC 429 wiring topology is based upon a 78 ohm, unbalanced, twisted
shielded pair. A Line Replaceable Unit (LRU) is typically connected to the bus
in a star or bus drop conguration.
Each bus has only one transmitter and up to 20 receivers, however, one termi-
nal may have many transmitters or receivers on different buses. The transmitter
sends out the 32 bit word, LSB rst, over the wire pair in a tri state clocking,
RZ methodology. The actual transmission rate may be at the low or high speed
of operation: 12.5kHz (12.5k to 14.5kHz) and 100kHz (1%). A receiver is not
allowed to ever respond on the same bus where a transmission has occurred.
However, since a LRU may have one or more transmitters and/or receivers
(each being on a separate bus), an LRU may respond over another bus. An LRU
on the ARINC 429 bus does not have an address. LRUs have equipment num-
bers which are then further grouped into equipment/system types. Equipment
and system identication numbers are used for system management and are not
typically encoded into the ARINC Word. An LRU is programmed to listen on
the bus for ARINC data words. Remember, the data word begins with a Label
identifying data of interest.
[2.1.1 Direct ion
of Inf ormat ion
Flow]
Transmission of information occurs from a port on the LRU that is designated
for transmission only. Similarly, receive ports are used for receive only. Infor-
mation cannot ow into a port designated for transmission. This is the basic
denition of a simplex bus. To obtain bidirectional dataow between LRUs,
you must use at least two ARINC 429 buses.
F.3.3 ARINC 429 Physical Aspects
Since its often easier to develop an understanding of a system when you have
a visual/physical image of its topology in your mind, the physical aspects of
ARINC 429 are presented rst. Physical aspects include bus topology (how to
wire the bus), transmission media, electrical characteristics and LRU interac-
tion.
F-6 An ARINC 429 Commentary
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F.4 Elect rical Element s
This section discusses cabling, transmission characteristics, and waveform
characteristics as related to Section 2.2 of ARINC 429P1.
F.4.1 Cabling
The transmission media for the ARINC 429 bus is a 78 ohm twisted shielded
pair. A schematic illustration of a twisted pair appears below.
Figure F.4.1: Twisted Pair
One end of the twisted pair should terminate into the data source and the other
end should terminate into the data sink(s). The shields should be grounded at
both ends and at all production breaks in the cable. Only a single source is per-
mitted per bus and a maximum number of 20 sinks may be connected. Either a
star or line drop topology is permitted. A source must be capable of handling a
maximum load of 400 . A receiver sink must have a minimum effective input
impedance of 8 k. No particular bus length is specied, partially due to the
direct connect nature of bus and that each sink acts like an electrical drain.
Some of the newer transmitters can handle 20 receivers and over 300 feet of
bus length. Most systems are designed for under 175 feet.
Choosing a
Wiring Topology
The choice of wiring topology is usually related to the distance and proximity
of the sinks to the source. There are two topologies; Star and Bus Drop. The
illustrations on the next page show each topology.
In earlier designs, especially, the star topology was implemented. Many con-
sider star topology safe since each LRU has its own connection to the source.
Therefore, any break along a bus length results in loss of only one listener.
However, the star topology requires much more wire, thus adding more weight,
and also tends to create a rats nest within harness areas.

+
Grounded shielding
Electrical Elements F-7
Figure F.4.2: Star Topology for LRU Wiring
Therefore, many argue effectively for the Bus Drop topology. The same num-
ber of connections are still present and there is a signicant reduction in weight
from dropping each LRU off of a central bus. Additionally, the bus drop topol-
ogy avoids the rats nest issue and replaces multiple terminators with a single
termination while maintaining very similar source to sink characteristics.
Figure F.4.3: Bus Drop Topology for LRU Wiring
Transmitter
LRU
LRU
Receiver
LRU
Receiver
LRU
Receiver
LRU
Receiver
LRU
Receiver
Transmitter
LRU
LRU
Receiver
LRU
Receiver
LRU
Receiver
LRU
Receiver
F-8 An ARINC 429 Commentary
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F.4.2 Transmission Characteristics
ARINC 429 has two speeds of operation: 12.5kHz (12.5k to 14.5kHz) and
100kHz (1%). The 32 bit word is transmitted LSB rst over the wire pair with
a tri state clocking, RZ methodology. Separate words are identied by having
an intermessage (or interword) gap time of at least 4 bit times, from end of
cycle to beginning of next rise or fall time. A one is created by the transmit-
ter when a rising edge goes from zero to 101 positive volts, plateaus then
drops down to the zero volt line which is known as the null area (null level
0.5). A zero is created by the transmitter when a falling edge drops from
zero down to 101 negative volts, plateaus, then rises up to return to the null
area. One and zero pulses are considered a complete cycle only when followed
by a null area plateau as depicted by B in Figure F.4.4. Every plateau should
be of equal length.
F.4.3 Waveform Characteristics
The signal waveform generated is a Return to Zero (RZ) bipolar tri-state mod-
ulation. The three states are identied as HI, NULL and LOW. Figure
F.4.4 below depicts each state.
Figure F.4.4: A429 Waveform Characteristic
C D
A
B
TX
Voltage Side
RCV
Voltage Side
HI 10 V 1 V
NULL 0 V 0.5 V NULL
HI
LOW LOW 10 V 1 V
6.5 V
13 V
6.5 V
2.5 V
2.5 V
13 V
Electrical Elements F-9
Table F.4.1: ARINC 429 Output Signal Tolerances
Transmitter
[Sect ions 2.2.3.1
& 2.2.4.1]
Figure F.4.4 is the depiction of an ideal waveform. The gure also shows
boundaries for both transmitter and receiver conditions. In order to create the
wave, the transmitter needs to generate a differential output signal across the
twisted pairs. The transmitter needs to be balanced to ground and should emit a
differential signal as depicted on the left hand side of Figure F.4.4. The volt-
ages depicted are when the transmitter line is at open circuit. The voltage scale
on the left are the values that transmitters are expected to generate. Even
though a valid signal should not exceed 13 volts in either direction, a transmit-
ter should be designed so as to prevent a voltage transmission in excess of 30
VAC across the wire pair and 29 VDC from either wire to ground. Transmit-
ters should be able to withstand indenite shorts across the wire pair and/or to
ground.
Most ARINC 429 transmitters are designed using an RC circuit to control the
rise time. This implementation is preferred in order to minimize overshoot
ringing, typically associated with rapid rise times. The rise and fall times are
delineated by the letters C and D. The letter A delineates the threshold
area while the letter B delineates the bit time area. The rise and fall times for
the 100 kHz rate is 1.5 0.5 sec while the rise and fall times for the 12.5 kHz
bus is 10 5 sec. The transmitter should exhibit a continuous output imped-
ance of 75 5 in a balanced fashion between each wire of the twisted pair.
Cable impedance should be selected to match the 75 transmitter require-
ment. However, actual values from 60-80 falls within the expected charac-
teristics.
Receiver
[Sect ion 2.2.3.2
& 2.2.5 & 2.2.6]
The voltage scale on the right of Figure F.4.4 are the values for which receivers
are expected to decode. Even though the receiver should not see an amplitude
any greater than 13 volts, each receiver should be designed to withstand
steady state voltages of 30 VAC RMS across the wire pair and 29 VDC from
either wire to ground. In proper decoding operations, the 429 specication
declares the receivers valid null area to be 2.5 V, it is not uncommon to have
receivers that have a null area up to 3.5 V and will not decode a one or
zero until the signal amplitude reaches +4.5 V or -4.5 V, respectively. These
adjusted thresholds are typically implemented to overcome noise problems on
LTR Parameter High Speed Low Speed
Bit Rate 100KBPS 1% 12-14.5 KBPS
A 1st half of pulse 5 sec 5% B/2 5%
B Full pulse cycle 10 sec 2.5% Z* sec 2.5%
C Pulse Rise Time ** 1.5 0.5 sec 105 sec
D Pulse Fall Time** 1.5 0.5 sec 105 sec
* Z = 1/Bit Rate; Bit Rate is the selected rate of transmission of 12 - 14.5 KBPS
** The Pulse Rise (C) and Pulse Fall (D) times are measured between their 10% to 90% amplitude.
F-10 An ARINC 429 Commentary
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the bus. On the other hand, the specication encourages designers to try a 1
volt separation between decoding values.
Most ARINC 429 receivers are designed around an operational amplier
matrix which typically includes a clock speed identier to establish timing
requirements for differentiating high and low speed signals. The differential
input resistance and resistance to ground of a receiver should be no less than
12,000 , with a total input resistance no less than 8,000 . The differential
input capacitance and capacitance to ground should not be greater than 50 pF.
F.5 Word And Prot ocol Met hods
F.5.1 The ARINC 429 Word Overview
Each sink is programmed to look for only data relevant for its operation. Rele-
vant data is identied by the rst eight bits of the ARINC word, known as the
Label. Each ARINC 429 word consists of 32 bits with the rst 8 bits (label)
octally encoded to represent the type of information contained within the 32 bit
word. Figure F.5.1 shows the organization of the 32 Bit ARINC 429 word. A
typical 32 bit word has ve parts:
8 bit label
Data area
Odd parity bit
Source/Destination Identier (SDI)
Sign/Status Matrix (SSM)
Note: Usage of SDI and SSM is not mandatory.
Figure F.5.1: 32 Bit ARINC Word
P SSM Most Significant Data DATA - 19 bits Least Significant Data SDI 8 BIT OCTAL LABEL
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MSB 32 Bit ARINC 429 Word LSB
Word And Protocol Methods F-11
[Subsect ion
2.1.2
Inf ormat ion
Element ]
The specication refers to the ARINC 429 word as the basic information ele-
ment. The basic information element is composed of the data element which is
categorized into ve application groups:
BNR data
BDC data
Discrete data [discussed in detail in Part 2 of the specication]
Maintenance data and Acknowledgment
ISO Alphabet No. 5 and its Maintenance data subset known as AIM.
Subsection 2.3.1 and Attachment 6 of the specication discusses these groups
in detail. Although the specication declares 5 types of data groups, there are
arguably 6. The sixth data group would be the current le transfer methodol-
ogy described in PART 3 of specication: Williamsburg/Buckhorn Protocol.
Note: The fth data type , AIM has be e n discontinue d and re -
place d with the Williamsburg Protocol.
Any unused bits of a dataword are required to be padded (zeros are to be placed
in the bit positions).
[2.1.2
Comment ary]
In actual use, the basic structure of the ARINC 429 word is very exible. The
only two parts of the word needing to stay intact are the Information Identier
(label) and the parity bit. However, earlier use of the word did allow the
removal of the parity bit. BCD words did not use parity. When greater data res-
olution was required within the word then the parity could be replaced with
data.
F.5.2 Details
Inf ormat ion
Ident ier
[Sect ion 2.1.3]
The Information Identier is a term used in the specication to associate two
different types of information: Label and Equipment Identier. The ARINC
429 specication denes these two together as a six character label that pro-
vides distinct designation for any type of ARINC 429 data. This six character
label consists of a three character octal identier known as the Label and a
three character hexadecimal identier known as the Equipment Identier.
These two are listed together as part of the specication in Attachment 1
Label Codes. An example of the Label Codes table follows.
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Table F.5.1: ARINC Label Codes Example
The Label identies the type of information contained within BNR and BCD
numeric and the word application for discrete, maintenance, and le transfer
methods (also described in ARINC 429P2 and P3). Labels can have system
instruction or data reporting functionality. The structure for assigning Label
numbers appears in ARINC 429P1 Appendix 5, Guidelines for Label Assign-
ments.
The binary representation of the Octal Label information and its bit position
within the ARINC 429 data word is seen under the TRANSMISSION
ORDER BIT POSITION heading of the table above. The most signicant bit
of the octal word is located in the least signicant ARINC 429 bit and is trans-
mitted rst out onto the bus. Since the LSB of the ARINC word is transmitted
rst, this in effect, causes the label to be transmitted onto the bus in reverse bit
position order. The Label is part of every ARINC 429 32 bit word and each
word begins with a Label. A Label is always transmitted in the rst 8 bits of the
ARINC 429 word.
Note: Whe n pe rforming data block or data le transfe rs, as
de scribe d in ARINC 429P3-15, the Labe l is re place d with the
Syste m Addre ss Labe l (SAL).
The Equipment Identier (Eqpt. ID) is used administratively and identies the
ARINC 429 bus source and must be associated with the source-sink combina-
tion. Each bus source may have up to 255 of the Labels, as dened above,
assigned for its usage. Since each type of equipment (black box) has its own
sets of Labels (and data) and a distinct equipment identity, the ARINC designer
can use the combination of the Label and Equipment Identier to prevent the
conict of unlike parameters having the same Label. Many times this Equip-
ment Identier code identies a system on the aircraft, i.e. Ground Proximity
Warning System, 023. A table of the various Equipment codes and the respec-
tive equipment type is located in Attachment 1, EQUIPMENT CODES.
The Equipment Identier is not transmitted out onto a bus unless the Label 377
is used. In association with that label, the number is encoded just following the
Source/Destination Identier (SDI).
CODE
NO.
(OCTAL)
EQPT
ID
(HEX)
TRANSMISSION ORDER and
BIT POSITION in 429 WORD
PARAMETERS
DATA
B N R B C D
1 2 3 4 5 6 7 8
374 005 1 1 1 1 1 0 1 1 E-W Velocity-Magnetic X
Word And Protocol Methods F-13
F.5.3 SDI
Source/
Dest inat ion
Ident ier (SDI)
[Sect ion 2.1.4]
The Source/Destination Identier (SDI) is optional and when used, occupies
bits 9 and 10 of the ARINC word. When used, the SDI is considered to add an
extension onto the ARINC words Label and ARINC systems are expected to
decode the Label/SDI combination as a different label than an ARINC word
with the same Label and no SDI implementation.
The SDI has two functions:
1. To ide ntify which source of a multi-syste m installation is transmitting the data
containe d.
2. To dire ct which sinks (de stination) on a multi-liste ne r bus (known as a multi-
syste m installation) should re cognize the data containe d within the ARINC
word
When used in the destination function, subsystems are given an installation
number: 01, 10 or 11 (binary). A zero in both bits 9 and 10 (00) conveys that all
sinks on the bus should decode the data or can be used as the address for a
fourth listener on the bus. An example of the multi-system destination installa-
tion appears below.
Figure F.5.2: Use of SDI in Destination Mode with Multiple Sinks
As stated, the use of the SDI is optional and is not available if transmitting ISO
Alphabet #5 alphanumeric data words or when additional bit resolution is
needed for BNR or BCD numeric data (data requiring a higher resolution than
typically provided with the 19 data bits). An example of the multi-system
source identication installation is provided below.
Source
LRU
SDI 01
LRU
Sink
SDI 00
LRU
Sink
SDI 10
LRU
Sink
SDI 11
LRU
Sink
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Figure F.5.3: SDI Usage with Multi-System Installation
F.5.4 Sign Status Matrix
The Sign/Status Matrix (SSM) eld may be used to report equipment condi-
tions or the sign (+, -, north, south, east, west, etc.) Bits 30 and 31 are typically
assigned to the SSM with bit position 29 also used for BNR words. In the sta-
tus function, the SSM eld reports hardware equipment conditions (fault/nor-
mal), operation mode (functional test) or validity of data word content
(veried/no computed data).
Sign/St at us
Mat rix
The Sign/Status Matrix (SSM) is used for two purposes 1) to provide a sign or
direction indicator for data contained within the ARINC 429 word or 2) to pro-
vide source equipment status information as related to the data word for the
sinks. Each Label has its own unique implementation of the SSM Sign func-
tion.
When used to provide equipment status information the SSM reports three
general conditions:
1. Re port hardware e quipme nt condition (fault/normal)
2. Ope rational Mode (functional te st)
3. Validity of data word conte nts (ve rie d/no compute d data).
Status information may also be accompanied by other bit settings within the
data word or data within the ARINC word indicating the type of status or
related values. This additional information would be specic for each system.
The following is valid for BCD, BNR and Discrete data words.
Source
Source
Source Source
Source Source
LRU
SDI 01
LRU
SDI 00
LRU
Sink
SDI 10
LRU
Sink
Sink Sink
SDI 11
LRU
Sink
Sink
Word And Protocol Methods F-15
Table F.5.2: Denitions
Functional Test status encoding is used with instruction Labels and data report-
ing Labels. When an ARINC word has an instruction Label and is accompa-
nied by a the Functional Test being set, then the decoding sink should interpret
the instruction as a command to exercise a functional test. When the ARINC
word has a data reporting Label and the Functional Test is set, the data con-
tained within are the results of a Functional Test. Typical BCD test report data
has values of 1/8th of full scale, unless otherwise dened. [Extracted from
BCD section but applies to all Part 1 and 2 systems. No further discussion is
presented in other sections.]
F.5.5 Sign/ Status Matrix as Related to BCD Numeric Data [Section 2.1.5.1]
St at us
Report ing
When encoding bits 30 and 31, the highest priority status (Priority 1) should be
encoded as a 1 1" 1 1" is used to indicate the Failure Warning. Priority 2,
typically encoded as 1 0", is used to indicate No Computed Data. Priority 3,
typically encoded as 01 is the Functional Test indicator while 00" indicates
Normal Operation.
Each LRU should cease transmission of unreliable data upon failure detection.
If a system is capable of partial data resolution and the Information Identier
supports the functionality, the system may ll the unreliable BCD digits with
1111" while continuing to transmit valid data portion. Displays should show
unreliable data as a dash (-) or equivalent symbol. Upon a No Computed
Data detection, the LRU should encode into the BCD data word elds the pre-
dened unreliable data reasons.
Definition Meaning
Invalid Data:
An indication from the source to the sink(s) declaring it is unable to
deliver reliable data. Invalid data includes two categories 1) No
Computed Data and Failure Warning.
No Computed Data:
This condition declares that the black box is unable to deliver valid
data as related to a set of predefined events or conditions, not relat-
ed to inability to compute reliable data. The exact meaning for the
No Computed Data indication is specific for each black box system
and is always predefined.
Failure Warning:
This condition declares that black box system monitors detected
one or more failures within or related to the system. The failures in-
dications detected are specific for each black box system and are al-
ways predefined.
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F.5.6 Sign Usage with BCD Numeric Data
Use of the Sign function is optional with BCD Data. If the function is not used,
bits 30 and 31 should be padded (set to zero). If the Sign function is used then
00 will stand for Plus, North, East, Right, To and Above. A 01 will indicate
No Computed Data. A 10 will indicate the Functional Test mode while a 11
will indicate Minus, South, West, Left, From and Below.
Sign/Status Matrix as Related to BNR Numeric Data [Section 2.1.5.2]
St at us
Report ing
When encoding bits 30 and 31, the highest priority status (Priority 1) should be
encoded as a 00" A 00" is assigned to indicate the Failure Warning. Priority
2, typically encoded as 01", is used to indicate No Computed Data. Priority 3,
typically encoded as 10 is the Functional Test indicator while 11" indicates
Normal Operation.
If an LRU has the ability to detect a fault condition that indicates a degradation
of data accuracy (i.e. input failure) and the data Label denes 17 or less data
bits, the LRU shall continue to transmit a 00 in bits 30 and 31 (reporting NOR-
MAL) and should encode a 1 into bit location 11 of the respective ARINC
word. [Attachment 2 notes column provides detailed information.]
Sign Usage wit h
BNR Numeric
Dat a
Use of the Sign function is optional with BNR Data and is restricted to bit loca-
tion 29. If the function is not used, bit 29 should be padded (set to zero). If the
Sign function is used, zero (0) will stand for Plus, North, East, Right, To and
Above while a one (1) will indicate Minus, South, West, Left, From and Below.
F.5.7 Discrete Data Words SSM usage [Section 2.1.5.3.]
St at us Usage
Only
When encoding bits 30 and 31, the highest priority status (Priority 1) should be
encoded as a 1 1 1 1 is used to indicate the Failure Warning while No
Computed Data should be encoded as 01. The Functional Test indicator should
set the bits to 10 while 00" indicates Veried Data, Normal Operation.
Each transmitting LRU (source) should notify its sink(s) upon detection of a
fault condition that indicates a degradation of data (unreliable condition). The
source has three different methods to notify its sinks:
1. Se t the SSM to Failure Warning (11).
2. Ce ase transmission of unre liable data upon failure de te ction (re comme nde d
for display syste ms).
3. Encoding of failure condition information into the data e lds. (Do not mix
ope rational data and failure condition data.)
Word And Protocol Methods F-17
F.5.8 Dataelds - 2.1.6, etc.
As seen in the table below, a typical ARINC 429 word provides 19 bits for
data. However, since the SDI is optional, 21 bits are available for use. Some
manufacturers custom data word congurations use only the Label and the
Parity, providing 23 bits available for their data.
The specic method and organization of data for each Information Identier ap-
pears in ARINC 429-P1, Attachment 2.
Table F.5.3: 32 Bit ARINC 429 Word
All BCD data are encoded using bit numbers 1-4 of the seven-bit-per character
code as dened in ISO Alphabet #5. Alphanumeric data requires the use of all
seven bits per character. (See Attachment 5 of ARINC 429P1.)
BNR data parameters are dened by rst determining the parameters maxi-
mum value, then the resolution required. The least signicant bit of the data
word is then assigned a value equal to the resolution increment. The number of
signicant bits for the BNR data are chosen such that the maximum value of
the fractional binary series (each increment of the resolution) just exceeds the
parameters maximum value. The maximum value of the fractional binary
series equals the next whole binary number that permits the presentation of the
parameters required maximum value.
For detailed information about how negative numbers, twos complement frac-
tional notation, and angular data presentation, see Section 2.1.6 within ARINC
429P1.
F.5.9 Protocol
Most ARINC 429 data is transmitted integrally as part of the labeled word, i.e.
Binary, BCD, Alphanumeric. However, a combination of 32 bit words may
also be used in a block transfer (i.e. AIM) mode. The AIM block transfer proto-
col (now discontinued) was the original manner dened for data block transfer,
being replaced with the Williamsburg le transfer protocol, as introduced in
ARINC 429-12. The Williamsburg protocol is a bus response le transfer pro-
tocol. Williamsburg is implemented using two or more buses between two
LRUs. Each LRU has a transmit bus and a receive bus and a control protocol is
implemented to manage the data transfer. In addition, these buses are point to
P SSM Most Significant Data DATA - 19 bits Least Significant Data SDI 8 BIT OCTAL LABEL
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MSB 32 Bit ARINC 429 Word LSB
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point and are typically designed with the ability to perform under typical 429
single word transfer format.
An ARINC 429 data word has a predened rate at which it must be retransmit-
ted. The exact data may or may not be repeated. Most systems require data to
be transmitted at the predened transmission repeat interval whether the data
has changed or not. Each label has a minimum and maximum transmit interval
that has been predened. A labels rate and interval are dened in the ARINC
429 specication, or in a specication by another governing body (i.e. GAMA)
or by a particular avionics system supplier.
The minimum interword gap time at which ARINC 429 words can be transmit-
ted is four bit times. As seen in Figure 1, ARINC 429 Waveform Characteris-
tics - letter B, an ARINC 429 bit time consists of the positive or negative pulse
and the return to zero period. Four of these bit times are the minimum required
to separate two ARINC 429 words. It is not uncommon to see systems
designed with a standard 60-80 bit time intermessage gap.
The table below exemplies how an ARINC 429 word is used when encoded for
BCD information.
Table F.5.4: Sample ARINC 429 Word Encoded for BCD Information
P SSM BCD CH#2 BCD CH# SDI 8 BIT OCTAL LABEL
LABEL
0 0
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
MSB DME Distance - BCD Example LSB
Summary F-19
F.6 Summary
Although this commentary should not be used to replace the ARINC 429 Part 1
Specication, we hope the information presented in this commentary helps to
clarify the specication.
For copies of the specication, please contact the following organizations:
Aeronautical Radio, Inc.
2551 River Road
Annapolis, MD
21401
USA
IHS
15 Inverse Way East
Englewood, CO
80112
USA
Email: custsvc@ihs.com
SBS welcomes your feedback about this commentary. Please direct it to:
bschuh@sbse.com
or call 800-727-1553 extension 227.
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