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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 5, MAY 2000
I. INTRODUCTION
ward network consists of a voltage divider (comprised of resistors R1 and R2 ) and a pulse-width modulator Tm . Fig. 2 depicts a dc model of an open-loop PWM buck converter [7] with
feedforward control. The average parasitic resistance r of the
circuit is [7]
r = DrDS + (1 0 D )RF + rL
Kf (dc)
A. General DC Characteristics
Fig. 1 shows a general circuit of an open-loop PWM buck
converter with input-voltage feedforward control. The feedforManuscript received February 4, 1999; revised October 10, 1999. This paper
was recommended by Associate Editor A. Ioinovici.
The authors are with the Department of Electrical Engineering, Wright State
University, Dayton, OH 45435 USA (e-mail: mkazim@cs.wright.edu).
Publisher Item Identifier S 1057-7122(00)03964-7.
(1)
D
:
VI
(2)
(3)
where IO = VO =RL and VF is the diode offset voltage. Substitution of (2) into (3) produces the general dc input-to-output
KAZIMIERCZUK AND EDSTRM: OPEN-LOOP PEAK VOLTAGE FEEDFORWARD CONTROL OF PWM BUCK CONVERTER
741
s
!0 =
and
"
L + C [r(RL + rC ) + RLrC ]
2
voltage transfer function of the PWM buck converter with feedforward control
Mv(dc)
=
D
RL + r
VF Kf (dc)
+ VF Kf (dc)
: (4)
(13)
= 0
RL
RL + r
(14)
VO
VI
RL
LC (RL + rC )(RL + r)
(12)
=
At s
RL + r
LC (RL + rC )
0 VD :
(15)
This is a general condition for achieving a zero audio susceptibility in a PWM buck converter.
C. General Small-Signal Input Impedance
From Fig. 3, the ac component of the input current is
v:
Z1 + Z2
= vi (s) D + Kf (ac) VI
Z2
il (s) =
(17)
Z2
(16)
(5)
IO =
(6)
Z1 + Z2
DVI
0 (1 0 D)VF :
(18)
(RL + r )
where
Z1 = r + sL
(7)
and
(8)
Mv (s)
vvo((ss)) =
i
D + Kf (ac) VI
Z2
Z1 + Z2
(9)
RL rC
(10)
where
!zn =
rC C
Z1 + Z2
:
ii (s)
DVI Kf (ac)
(19)
(RL + r )
Z1 + Z2
L(RL + rC )
)
2 (s2 +(s2+!!zn
s + !2 )
0
(RL + r )
DKf (ac) VI + D2
Zi (s)
vi (s)
=
0 (1 0 D)VF
From (6), one obtains the audio susceptibility for the open-loop
PWM buck converter with feedforward control
DVI
(11)
(20)
Substituting (7) and (8) into (20) gives the small-signal input
impedance for the open-loop PWM buck converter with feedforward control
Zi (s) = Zic
s2 + 2!0s + !02
s2 + s(2!0 + ZA ) + (!02 + ZB )
(21)
742
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 5, MAY 2000
where
Zic =
ZA =
(RL + r )
Kf (ac) [DVI 0 (1 0 D)VF ]
0
1
(RL + r ) DVI Kf (ac) + D 2
LKf (ac) [DVI 0 (1 0 D)VF ]
and
ZB =
At
(22)
(23)
r DVI Kf (ac) + D2
:
LCKf (ac) (RL + rC )[DVI 0 (1 0 D)VF ]
( L+ )
(24)
= 0
Zi (0) =
( L+ )
3:
VT m = vt(T )
c = Cc Rc +
R1R2
:
R1 + R2
(26)
vt = VI (1 0 e0t=c )
VI
t
c
(27)
VI
(28)
where
A. Control Circuit
Fig. 4 shows an open-loop PWM buck converter with peak
voltage feedforward control circuit. The feedforward control
circuit consists of a sawtooth generator SG, a reference dc
voltage source VREF , and a comparator (called a pulse-width
modulator). Fig. 5 depicts a sawtooth generator whose peak
voltage is proportional to the supply voltage vI [1]. The
sawtooth generator consists of a voltage divider R1 and R2 , a
resistor Rc , a solid-state switching device (e.g., MOSFET), a
capacitor Cc , and a clock oscillator CLK with a fixed frequency
fs . When the MOSFET is OFF, the capacitor Cc is charged
through the combination of resistors R1; R2 , and Rc with a
time constant
VI
T
c
R2
R1 + R2
(29)
and
T
= :
c
(30)
If c T = 1=fs , the sawtooth voltage waveform is approximately linear and its magnitude is proportional to the input
voltage VI . The sawtooth voltage vt is applied to the inverting
input of the comparator and the reference voltage VREF is applied to the noninverting input. When the sawtooth voltage vt is
lower than the reference voltage VREF , the comparator output
voltage goes high and, therefore, the gate-to-source voltage vGS
of the power MOSFET in the buck converter also goes high. The
crossing time of the two voltages determines the duty cycle D .
Fig. 6 shows the waveforms for the buck converter with peak
voltage feedforward control. From the figure and geometry
D=
Thus, the duty cycle
increases.
VREF
VT m
VREF
:
VI
(31)
VI
KAZIMIERCZUK AND EDSTRM: OPEN-LOOP PEAK VOLTAGE FEEDFORWARD CONTROL OF PWM BUCK CONVERTER
743
B. DC Characteristics
For a lossless buck converter, the relationship between the dc
input and output voltages is
VO = VI D:
(32)
VO =
VREF
:
(33)
This equation shows that, ideally, the output voltage of a lossless buck converter with peak voltage feedforward control is independent of the input voltage VI . Since both VREF and are
constant, the output voltage VO also remains constant. However,
this assumes that the generator produces a strictly linearly increasing output signal vt and the parasitic components r and VF
of the buck converter dc model are neglected. Using (31), the
dc control voltage-to-duty cycle transfer function of the pulse
width modulator is
Tm(dc)
D
VI
= (VVREF)2
(34)
Fig. 7. Output voltage VO versus input voltage VI for a lossy open-loop PWM
buck converter with peak voltage feedforward control at various values of load
resistance for rDS = 0:18
, VF = 0:4 V, RF = 28 m
, rL = 50 m
,
VREF = 5 V, and = 0:347.
Kf (dc)
D
VI
REF
= VV
:
2
(35)
VO =
RL
RL + r
VREF
from which
VREF
0 VF + VFV
I
(36)
1 + VVFI
=
:
1 + RrL VO + VF
VREF
(37)
to 200
.
C. Small-Signal Characteristics
Fig. 9 shows a small-signal model of the open-loop PWM
buck converter [7] with peak voltage feedforward control.
Fig. 10 depicts the waveforms in the converter, in which a
small-signal component vi is superimposed on the dc component VI , resulting in the large-signal input voltage
vI = VI + vi
(38)
dT
= D + d:
(39)
dT
REF
= Vv
:
(40)
744
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 5, MAY 2000
d
Tm(ac) =
vi
= 0 (VVREF)2 :
I
(45)
d
Kf (ac) =
vi
Fig. 10. Waveforms in open-loop PWM buck converter with peak voltage
feedforward control.
dT
For vi
1
REF
= VV
:
= D + d = (VVREF
+
v
)
(1
+
v
I
i
I
i =VI )
(41)
VI ;
1
1 + vi =VI
1 0 Vvi :
I
(42)
dT
= D+d
VREF
VI
vi
0 VREF
:
2
VI
(43)
d=0
VREF vi
:
VI2
(44)
REF
= 0 VV
= 0 VD
2
I
I
(46)
(s + !zn )
D
RL rC
Mv (s) = D 0 VI
2
VI
L(RL + rC ) (s + 2!0 s + !02 )
= 0:
(47)
Substitution of (46) into (21) yields the input impedance for
the open-loop PWM buck converter with peak voltage feedforward control
V (R + r)
Zi (s) = Ri = 0 2 I L
[D VI 0 D(1 0 D)VF ] :
(48)
KAZIMIERCZUK AND EDSTRM: OPEN-LOOP PEAK VOLTAGE FEEDFORWARD CONTROL OF PWM BUCK CONVERTER
745
Fig. 12. Experimental circuit of open-loop PWM buck converter with peak
voltage feedforward control.
Fig. 14. Experimental results (solid line) and calculated results (dashed line)
of dc output voltage VO versus dc input voltage VI for the open-loop PWM
buck converter with peak voltage feedforward control at RL = 200
and
RL = 50
for VI nom = 28 V, VO nom = 14 V, L = 320 H, rL = 20 m
,
C = 47 F, rC = 430 m
, rDS = 0:18
, VF = 0:4 V, RF = 28 m
,
VREF = 1:5 V, and = 0:104.
746
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: FUNDAMENTAL THEORY AND APPLICATIONS, VOL. 47, NO. 5, MAY 2000
Fig. 15. Measured magnitude and phase of the audio susceptibility Mv for
the open-loop PWM buck converter with peak voltage feedforward control at
VI nom = 28 V, VO nom = 14 V, RL = 200
, L = 320 H, rL = 20 m
,
C = 47 F, rC = 430 m
, VF = 0:4 V, RF = 28 m
, rDS = 0:18
,
VREF = 1:5 V, and = 0:104.
vI = 28
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1821, 1996, pp. 885888.
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143148, Feb. 1997.
[6] B. Arbetter and D. Maksimovic, Feedforward pulse width modulators
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[7] M. K. Kazimierczuk and D. Czarkowski, Energy-conservation approach to modeling PWM dc-dc converters, IEEE Trans. Aerospace
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