Abstract-- In this paper digital voltage-mode controller design

for a zero-voltage turn-on high gain boost converter is presented.

Firstly, the converter steady-state performance is analyzed by
using circuit theory principles. This analysis shown that this
converter circuit exhibits five different modes of operations in
one switching cycle and also results in zero-voltage transition to
the switching devices. Control-to-output z-domain transfer
function is formulated, using system identification toolbox of the
MATALB, and then used in the direct digital controller design. A
pole-zero placement technique is adopted to arrive at final digital
voltage-mode controller. Closed-loop converter performance is
predetermined, for a 24 to 100 V 100 Watt prototype both in
matlab and PSIM software, and then compared with
experimental measurements. Experimental measurements are in
close agreement with simulations.

Index Terms Digital Controller, High gain Boost Converter,
Soft-switching, Voltage Regulation.

I. INTRODUCTION
IGH frequency switching converters application in low
power compact electronic circuits is increasing in the
recent years. As the power conversion system is becoming
miniaturized, increasing the power density is one of
challenging issue for the power supply designers. One of the
main orientations in switch-mode conversion [1]-[4] is to
reduce the size of the magnetic elements, if possible avoiding
use of transformers wherever isolation is not required, and
more important concern is reducing the electromagnetic
interference (EMI), etc. Light weight, small size and high
power density are possible, nowadays, by use of high
frequency switching. Several different kinds of power circuit
configurations have been reported in literature to meet the
load demand and they are broadly classified into: (i) buck, (ii)
boost, and (iii) buck-boost topologies, etc. These converter or
their derivatives find application in several different areas, of
which most important one are: (i) power supply applications
for miniaturized integrated circuits, (ii) automotive industry,
(iii) internet services/ LAN and WANs, (iv) telecom industry
etc.


M. Veerachary and R. Sekhar are with Dept. of Electrical Engineering,
Indian Institute of Technology Delhi, Hauz Khas, New Delhi 110016,
INDIA (e-mail: mvchary@ee.iitd.ac.in).

978-1-4244-7882-8/11/$26.00 2011 IEEE

Dc-dc boost converter is most popular for delivering higher
load voltages from given low voltage source. Although the
conventional boost converter is capable of stepping-up of
voltages and meeting the load demand at a predefined voltage
levels, but its full load efficiency is low on account of higher
switching losses. Recently, soft-switching techniques are
coming-up to overcome the excessive switching losses
occurring in the conventional hard-switched dc-dc converters
and to realize higher efficiencies for the dc-dc converter at
full-load conditions. One such high gain soft-switching boost
converter (HSFBC) topology is reported in the literature [8]-
[9]. However, there is not enough literature covering the
development of controllers for such kinds of converters. In
order to bridge this gap, this paper presents some
investigations on digital controller design, which ensures load
voltage regulation while rejecting source and load
disturbances.

Although analogue controllers are well established for
SMPSs [1][4], digital controllers offer many advantages over
their analogue counterparts. Due to recent advances in
microcontrollers/digital signal processors, there has been a
growing interest in the application of digital controllers for
high frequency conversion systems and low to medium power
dc-dc converters (DDC), due to the low price-to-performance
ratio for implementing complex control strategies [5][7].
Several compensator design approaches have been reported in
the literature for Op-Amp or IC based analogue controllers.
However, in the case of digital controller design, two main
approaches are widely used, that is: (i) digital redesign method
(DRM), (ii) direct digital design method (DDDM). In the first
case, the compensator is designed in the conventional way by
using s-domain transfer functions together with linear system
theory and the resulting compensator is transformed into the
digital domain using appropriate z-transformations. On the
other hand, in DDDM, the compensator design is carried out
in the z-domain itself and hence there is no need for s -to- z-
domain transformation. The main difficulty of the DDDM is
that if the plant model is approximate then digital controller
design will be a tedious task. In view of this here DRM is used
for the digital controller design.




Voltage-mode Controller Design for
Soft-Switching High Gain Boost Converter
Mummadi Veerachary, Senior Member, IEEE, Ruddireddy Sekhar
H

II. DEVELOPMENT OF DISCRETE-TIME MODEL FOR SOFT-
SWITCHING HIGH GAIN BOOST CONVERTER
A high gain soft-switching boost converter is shown in Fig.
1. In comparison to the conventional boost converter, this
circuit has an additional soft-switching network, formed by L,
C elements, together with two diodes (D
1
, D
2
). Another
difference is that the diode of the conventional boost converter
is now replaced with an auxiliary switch (S
a
) in order to allow
the current through the resonant tank in either directions. This
HSFBC operates in five different operating modes [13] in one
PWM cycle, as shown in Fig. 1, and the conducting devices in
each mode of operation are: (i) mode-1: D-ON, (ii) mode-2:
S
m
, S
a
and D are in ON-state, (iii) mode-3: S
m
, S
a
are in ON-
state; L
r
, and C
r
are resonating, (iv) mode-4: S
m
, S
a
, D
1
and D
2

are in ON-state, (v) mode-5: D
1
and D
2
are in ON-state, L
r
,
and C
r
are resonating.

The steady-state voltage gain of this HSFBC has an
identical form,
0
2 (1 ) ,
g ef f
V V D =
to the conventional
boost converter, except to that it uses an effective duty ratio
( ) ,
e f f
D D D =
where D is the duty ratio loss due to
the soft-switching [10]. On account of soft-switching
operation this HSFBC undergoes five intermediate modes of
operations and during some of these modes the converter
circuit is under quasi-resonance. In view of this the
conventional state-space modelling can not applied directly.
For modelling such kind of converters, and the corresponding
resonant behaviour, a generalized state-space method has been
reported in literature [9].However, this model formulation
methodology assumes variables associated with the resonant
tank (L
r
, C
r
) as input control variables, rather than as state
variables. In view of this, the resulting model accuracy is low.
Furthermore, the accuracy of the model obtained through this
methodology is essentially governed by the (i) accuracy of
time durations, obtained through the expressions which are
developed after including simplifying assumptions, (ii)
depending on loading conditions the number of operating
modes might be changing and hence expressions need to be
updated to this effect, and (iii) complexity of the discrete-time
model increases with increase in number of operating modes.

To improve the model accuracy, a larger number of
harmonics needs to be included in the generalized state-space
method. This increases the order of the model and its
mathematical analysis now becomes much more complex. To
alleviate some of these problems, system identification
technique [10] is employed here for discrete-time model
formulation. The advantages of these techniques are: (i) the
internal structure of the converter need not be known in
advance as long as one can obtain a satisfactory statistical
distribution of the data, (ii) in some cases this approach is very
effective at generating a reduced order model to represent a
complex subsystem of the distributed power electronic
system, and (iii) this method is particularly useful in SMPS
where there are many modes of operation and difficulty in
finding the duty ratio of each mode operation, etc.

Although several system identification tools can be
employed for soft-switching converter model formulation,
here a Box-Jenkins methodology is used for discrete-time
transfer functions generation. Taking the designed converter
parameters, firstly the HSFBC is formulated in the
SIMULINK platform and then the response of the desired
parameter is generated for a given range of perturbation of the
pre-defined parameter. For a given source voltage and load
resistance range, Table I, the duty ratio varies between 0.3 ~
0.7 and this is used as the range for the perturbation duty ratio
control signal. Taking these boundaries, equally spaced
intermediate points with step time equal to the sampling time
period are generated using a random generator. This signal is
then compared with the triangular ramp and used to generate
an equivalent duty ratio signal which is used to drive the
switching device of the converter. Since there is a perturbation
in the converter, various current and voltage quantities will
have corresponding variations. In order to find the converter
discrete transfer function of interest, the corresponding
samples of current or voltage and the perturbation signals are
passed on to the system identification toolbox of Matlab. In
this toolbox, the user has the option to choose linear
parametric model formulation methodology and its fitting
order for the given input-output data pattern. Once these are
decided, then the model is estimated and its accuracy is
verified by residual analysis. If the residual of the model is
within the allowable confidence interval, then the
corresponding estimated model represents the true behaviour
of the converter.

L
2
C
r
L
m
S
a
S
1
D
2
D
1
C
3
C

(a) Main circuit diagram



(b) Equivalent circuit during mode-I
operation

(c) Equivalent circuit during mode-II
operation




(d) Equivalent circuit during
mode-III operation
(e) Equivalent circuit during mode-IV
operation



(f) Equivalent circuit during mode-V operation
Fig. 1. Soft-switching high gain boost converter and its equivalent circuits
during various modes of operation.

10
0
10
1
10
2
10
3
10
4
10
5
-450
-360
-270
-180
-90
0
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (Hz)
-150
-100
-50
0
50


M
a
g
n
i
t
u
d
e

(
d
B
)
Gvd
Gc
Loopgain

Fig. 2. Bode plots of open-loop(red), compensator(blue) and Loopgain(pink).
(GM=30 dB, PM=70
0
, fc=30 Hz)

For the parameters listed in Table I the discrete-time
control-to-output transfer function, G
vd
(z), is obtained from
system identification is
3 2
4 3 2
( ) 0.04372 0.07185 0.02556 0.02155
( )

1.961 0.9664 ( )
o
vd
v z Z Z Z
G z
Z Z Z d z
+ +
= =
+
(1)
Taking this transfer function the control-loop is designed here.
If the digital controller transfer function is
c
G (z) then the
loopgain is defined as

vd c
T(z)=G (z)G (z) (2)
Although several different types digital compensators can
easily be designed, but a second order digital compensator is
sufficient enough for the HSFBC closed-loop regulation
purpose and its form is:
( )( )
( )
( 1)( )
c
k z a z b
G z
z z c

=

(3)

III. DIGITAL CONTROLLER DESIGN
There are several controlling methods such as single-loop
and multi-loop control techniques are reported in literature.
Each of these controlling techniques has their own advantages
and limitations. In load voltage regulation control applications
single-loop voltage-mode strategy is simple in implementation
and also results in reasonably good dynamic response. In view
of this a single-loop voltage-mode digital controller is
discussed in this section. The converter transfer function
G
vd
(z) has three poles and three zeros and its frequency
response is almost flat upto 1 kHz. In view of this
characteristic the controller must be of kind to shape the low
frequency behavior such that the loopgain falls at least 20
dB/dec. In order to have this, a pole at z=1 is added in the
controller section. The second pole and two other zeros
location is decided based on the required gain and phase
margins. The following controller parameter selection: a=0.7,
b-0.93, c=0.989, k=0.000345 yields the loopgain stability
margins of GM=11 dB, PM=58
0
. One can optimize these
parameters, but the other combinations will either increase the
overshoot or settling time. Taking above control-loop transfer
function and digital controller the loopgain bode plot has been
obtained using MATLAB [11] and it is shown in Fig. 2. In
order to test the feasibility of the designed controller the
corresponding control law is transformed into discrete-transfer
function given by
1 2
3 4 5
( ) ( 1) ( 2 )
( ) ( 1) ( 2 )
d n k d n k d n
k e n k e n k e n
= +
+ + +
(4)

where, d(n) is control output duty ratio, e(n) is the error
voltage/current at n
th
sampling instant. This control laws is
then used in the closed loop simulations and experimentation.

IV. SIMULATION AND EXPERIMENTAL RESULTS
To verify the developed modeling and controller design, a
70 W HSFBC system was designed to supply a constant load
voltage of 100 V from a source voltage of 24 V and the power
stage, controller parameters, designed to meet the
specifications, are listed in Table I. Initially the soft-switching
performance of the proposed HSFBC converter is verified

through PSIM simulations and for illustration purpose steady-
state waveforms of switch current and voltage is shown in Fig.
3. These waveforms clearly indicate the soft-switching
transitions: zero voltage turn-ON of the switching devices and
zero-current turn-OFF of the diodes. The converter voltage
gain variation is computed against duty for different transition
time durations (a1~a5; 0.05 ~ 0.25 in steps of 0.05) and the
corresponding plot is shown in Fig. 4. Normalized voltage
stresses of the switching devices as well as diodes have been
computed against duty ratio variation as shown in Fig. 5. It is
clear that at higher voltage gains the diode stress will more
than the corresponding switch stress.

For the parameters given in Table I the closed-loop
converter system regulation capability is tested for: (i) load
perturbation of 100 50%, (ii) supply voltage change 24 V
20%. For simulation PSIM [12] power electronics simulator
was used. The simulation results for the above mentioned
cases are shown in Fig. 6. In both the cases the load voltage is
achieved and the dynamic response is taking about 5 msec
time. The designed compensator validity was also verified in
experiments and dynamic response measurements were
recorded for almost identical cases as that were created in
simulations and the corresponding measurement results are
shown in Fig. 7. These measurement results clearly indicate
controller regulation feature. Although there is no steady-state
error in the simulation and experimental results, but there is a
slight deviation in the responses. This is on account of non-
ideal parasitic components, which were present in the
experimentation, which are helping in damping out the
dynamic response oscillations.

Fig. 3. Steady-state waveforms showing switching transition of the HSFBC.

TABLE I
CONVERTER AND COMPENSATOR PARAMETERS
Power stage Digital compensator

L=250 H, Lr=10 H
C1=50 nF, C2=110 F,
C3=110 F
R= 150 , Vg=24 V
fs = 50 kHz

0.00345( 0.7)( 0.93)
( 1)( 0.983)
z z
z z




0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0
2
4
6
8
10
12
14
16
18
Duty ratio(D)
V
o
/
V
i
n
a1
a5

Fig. 4. Converter voltage gain variation with duty ratio.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
D
n
o
r
m
a
l
i
s
e
d

v
o
l
t
a
g
e

s
t
r
e
s
s
e
s
Diode voltage stress
Switching devices stress

Fig. 5. Normalized voltage stress of switch/diode variation with duty ratio.

(a) Load resistance perturbation (R: 100 50 )


(b) Source voltage perturbation (V
g
: 24 30 V)
Fig. 6. Dynamic response of load voltage against perturbation.


(a) Load resistance perturbation (R: 150 100 )

(b) Source voltage perturbation (V
g
: 24 30 V)
Fig. 7. Experimentally measured dynamic response of load voltage.

V. CONCLUSIONS
In this paper the HSFBC converter steady-state
performance was analyzed by using circuit theory principles.
This analysis shows that the converter switching devices were
operating at zero-voltage turn-ON in each switching cycle.
Control-to-output z-domain transfer function was formulated,
using system identification toolbox of the MATALB, and then
used in the direct digital controller design using a pole-zero
placement technique. Closed-loop converter performance was
obtained both in simulation and experiment. These results
were in close agreement with each other and thus validated the
controller design.
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