Robust Digital Voltage-Mode Controller Design

For Split-Inductor SEPIC Converter

M. Veerachary
Dept. of Electrical Engineering, IIT Delhi, Hauz Khas, New Delhi, INDIA
E-mail: mvchary@ee.iitd.ac.in


Abstract- In this paper a robust digital voltage-mode controller
design is designed for a split inductor SEPIC converter to
achieve load voltage regulation. Split-inductor SEPIC converter
salient features are compared with the conventional SEPIC
converter and then discrete-time mathematical models are
established. Digital controller is designed using discrete-time
model through direct digital design approach. A two-pole two-
zero compensator is adopted in the design and then an edge
theorem is employed for testing the robustness of the controller.
Compensator design is validated through simulations and then
experimental measurements. Load voltage regulation
characteristics are obtained against line and load perturbations.
A 15 to- 36 V, 25 Watt laboratory prototype converter is built
for experimental investigations. Simulation and experimental
results are demonstrating the robustness feature of the designed
digital controller.

I. INTRODUCTION
Switch-mode power conversion application is increasing
in the low power compact electronic circuits. To realize
compact power supply system, increasing the power density
is one of the challenging issues for the power supply
designers. One of the main orientations in power electronics
in the last decade has been the development of switching-
mode converters with higher power density and low
electromagnetic interference (EMI). Light weight, small size
and high power density are also some of the key design
parameters [1]-[3].

High frequency switch-mode power supplies are becoming
an integral part of many power electronic systems [1] and the
dc-dc converters are mainly used in these application areas.
Technological developments are is taking place in order to:
(i) improve converter performance, (ii) achieve better
reliability, and (iii) increasing the power density, etc. The
aspect of increasing the power density is mainly related to the
converter design and packaging. Performance improvement
of the dc-dc converter topologies is broadly classified into
two different categories, which are: (i) steady-state
performance, and (ii) dynamic performance. Among these
two, the converter system dynamic performance mainly
governed by the type of controller used. Conventional SEPIC
converter based topologies are well established for
applications requiring both bucking and boosting the up-
stream voltages. However, in the applications where the
voltage gain requirement is higher, not possible to realize
with single conventional converter, then there are two
alternate solutions, which are: (i) cascading the boost
converters, (ii) cascading the SEPIC converters. Although
these methods are capable of resulting higher transformation
ratios, but more number of components are required for their
realization and also results in lesser efficiency. Some times to
realize the predefined transformation ratio the converter
needs to be operated at the extreme duty ratios wherein the
device utilization is poor with increased thermal loading. In
order to alleviate some of these limitations coupled inductor
boost converters and quadratic topologies have been proposed
in the literature [1]-[4]. However, more device stress is the
major limitation of these topologies. By using the split-
inductor [2] concept it is possible to increase the voltage gain
of the conventional SEPIC converter. In this paper the input
side inductance of the conventional SEPIC converter has been
replaced with split inductor, and then voltage transformation
properties, load voltage regulation, and robustness issues
have been addressed.

The dynamic performance and its robustness are primarily
decided by the control strategy employed for a particular
topology. The two most commonly used control schemes in
dc-dc switching power converters are: (i) voltage-mode
control, (ii) two-loop current-mode control. It is well known
that the voltage-mode control is slow in its response against
supply disturbances on account of single-loop voltage
feedback. On the other hand the two-loop control strategy,
inner current mode control together with outer voltage loop,
results in faster dynamic response. However, selection of a
particular control scheme is essentially decided by the
complexity and cost trade-offs requirements together with
robustness requirements dictated by the end-user.
Considering robustness as the requirement a single-loop
digital voltage-mode controller is designed in this paper for
the split-inductor SEPIC (SI-SEPIC) converter and detailed
design methodology is given in the following paragraphs.
2 2
, L r
3
3
,

L
r
1 1
,
c
C r
0
0
,

c
C
r
1 1
, L r

Fig. 1. SI-SEPIC circuit diagram
II. STEADY-STATE ANALYSIS AND DISCRETE-TIME MODEL
FORMULATION OF THE SPLIT-INDUCTOR SEPIC
CONVERTER
The split-inductor SEPIC converter is shown in Fig. 1.
This converter is derived from the conventional SEPIC
converter where-in the source side inductance is divided into
two halves and then arranged in a bridge form using two
additional diodes as shown in Fig. 1. The main purpose of
such split inductance is to provide additional boosting in the
load voltage. In comparison to the conventional SEPIC
converter, as it is indicated within the box, it consists of three
additional diodes (D
1
, D
2
and D
3
) and inductors (L
1
,

L
2
). Due
to this structural arrangement the circuit exhibits more
important features as compared to the conventional SEPIC
converter, which are: (i) the SI-SEPIC is capable of giving
higher load voltage boosting at lower duty ratios, (ii) switch
voltage/current stress is almost same as conventional
converter, and (iii) inductance requirement is almost same as
the conventional converter. Steady-state performance
comparison of this converter with conventional SEPIC
converter is given in Table I for ready reference.

This SI-SEPIC can operate either in continuous or
discontinuous inductor current mode of operation. However,
for a given power rating and boosting factor requirement the
source current magnitude is high for most of the loading
conditions and correspondingly the current is continuous in
all the three inductors. In view of this, the SI-SEPIC analysis
as well as its discrete-time model formulation is discussed
here for the continuous inductor current mode of operation.
As stated earlier the high voltage gain of this converter is
mainly due to the presence of the split inductors (L
1
, L
2
),
while there is no change in the load side ripple current as
there is no structural change in the circuit configuration. The
split inductor combination will draw the energy from the dc-
voltage source during switch-ON time period and then pumps
into the load for the remaining time period. In this process the
split inductors will be connected in series during the switch-
OFF period contributing to additional boosting as compared
to conventional SEPIC converter.

A. Converter parameter Design Equations
A steady-state analysis of the SI-SEPIC is established in
this section and the analysis is based on the following
simplifying assumptions: (i) switching devices are ideal, and
effect of non-idealities of the passive and energy storage
components on the steady-state performance is negligible, (ii)
ripple current/ voltage magnitude is very small, (iii) converter
time constant is very high as compared to the switching
period, and (iv) non-idealities of the energy storage elements
are neglected. By employing the kirchoffs voltage and
current laws the steady-state relationships among the various
voltage and currents are established. Assuming voltage drops
across inductors L
1
, L
2
are same, various voltages across
inductor elements L
1
, L
2
and L
3
during switch-ON/OFF
periods respectively are:
Inductor ON-time OFF-Time
L
1
V
g
(V
g
- V
c
- V
o
)/2
L
2
V
g
(V
g
- V
c
- V
o
)/2
L
3
V
c
-V
o


0
v

Fig. 2. Control block diagram of voltage-mode controlled SI-SEPIC.

TABLE I
PERFORMANCE COMPARISON


SEPIC SI-SEPIC
Voltage gain Low High
Efficiency Moderate Moderate
Transient response Moderate Low
Switching stresses
on elements
High Low

Applying volt-sec balance to the inductors L
1
, L
2
and L
3
and
then simplifying results in the following voltage
transformation ratio [7] for the converter.
( )
( )
0
1
1 -
g
D D V
V D
+
=
(1)

Using the power balance, V
g
I
g
=V
0
I
0
, and time-domain
analysis the SI-SEPIC design equations are established. The
minimum and maximum inductor current expressions can
easily be obtained by using the ripple quantities,
L1 g 1
i V DT L ; =
L2 g 2
i V DT L = and the capacitor
voltage ripple relationships are:
C1 L2 1
V I DT C , =
2
C0 g 2 0
V V (DT) (8L C ). = These
expressions together with current/ voltage ripple requirements
give the basis for the design of energy storage components
L
1
, L
2
, L
3
and C
1
, C
2
.

B. State-space Models For Continuous Inductor Current
Mode of Operation

Application of state-space modeling is widely used in the
switch-mode power conversion systems. Conventionally, the
discrete-time models are obtained through suitable
transformation applied to the state-space models. However,
accuracy of such discrete-time models mainly governed by
the type of transformation used and the switching frequency
employed. In ref[4] discrete-time modeling of digitally
controlled converters has been reported, where-in it has been
demonstrated that it is possible to include type of pulse width
modulation strategy as well as the sampling instant
information in the model itself. This methodology is used to
formulate the discrete-time model for the proposed SI-SEPIC
operating at trailing-edge OFF-time sampling [7]. In
continuous inductor current mode of operation the circuit has
two operating modes; Mode-1: S-ON (0<t<DT
s
); Mode-2: S-
OFF (DT
s
<t<T
s
). In each mode of operation the circuit is
linear, and its behavior can easily be described by the state-
space model [13] given by
[ ] [ ] [ ]
[ ] [ ]
( 1)
j j
j j
j
x A x B u
t t t
y E x
+
= +

< <
=

(2)
where [A
j
]- state matrix, [B
j
]- input matrix, [E
j
]- output
matrix, and [x]- state vector, [y]- output vector, [u]- forcing
function vector.

1 1
1 3 3
1
2
1 2
/ 0 0 0
0 / 1/ 0
;
0 1/ 0 0
0 0 0 1/ ( ( ))
c
c
r L
r L L
A
C
C R r




=


+



2
3 3 3 3 3
2
1
2 2 2 2
[ ] / / 1/ / ( * )
/ [ ] / 0 / ( * )
;
1/ 0 0 0 0
/ ( ) / ( ) 0 1/ ( ( ))
e c
c c
c
a r L a L L a r L
a L a r L a r L
A
C
R C R R C R C R r
+

+

=


+


[ ]
2 1
1/ 0 0 0 ;
T
B L = [ ]
2
1/ 0 0 0
T
B L =
C3
1 2
C3 C3
Rr R
E =E = 0 0 0
(R+r ) (R+r )





The above matrices gives an idea of the system that they are
linear in each mode of operation, and the circuit behavior can
easily be obtained by the discrete-time state-model [4] given
by eqns. (3) and (4).
^ ^ ^
[ ] [ 1] [ 1] x n x n d n = + ; (3)
0 k
v = E x ; (4)
s d d 1 2 1
DT -t ) T A ( A A D Ts
=e e e ;

s d 2 1
DT -t ) A A ( D Ts
s
=KTe e


where
[ ]
T
L1 L3 c1 c0
x = i i v v ,
g
u=[V ]. Detailed discrete-
time formulations are reported in ref[4] are used and they are
listed here, eqns. (5)-(9), for ready reference.

-1
vg
G ( ) E (z- ) +F z =
(5)

-1
vd
G ( ) E (z- ) z = (6)

-1
( ) P [(ZI- ) ]
in
Z z = (7)

-1
( ) [E (zI- ) +J ]
o
Z z = (8)
3 2
3 2 1 o
vd
4 3 2
4 3 2 1 o
p z +p z +p z+a
G (z)=
[q z +q z +q +q z+q ] z


(9a)

Substituting the converter parameters, given in Section IV,
results in the following control-to-output transfer function.
3 2
vd
4 3 2
12.68z -31.85z +28.66z-8.982
G (z)=
[z -3.519z +4.833 -3.072z+0.76] z


(9b)
II. DIGITAL CONTROLLER DESIGN GUIDELINES
Fig. 2 shows the digitally controlled SI-SEPIC system,
where the loop gain is defined by ( ) ( ) ( )
v c vd
T z G z G z = . Here,
we need to design a robust digital voltage-mode controller,
G
c
(z), such that the load voltage must be constant irrespective
of the uncertainties in the converter parameters, disturbances
caused by input dc bus, or load fluctuations. The selection of
compensator is more important and its structure depends on
the order of the converter system. The converter under
consideration is fourth order and hence simple compensators,
like one-zero one-pole or one pole and two zeros, will not be
suitable as they will not provide sufficient gain margin (GM)
or phase margin (PM). Simple second order compensator is
the viable solution for this converter. Several other higher
order digital compensators can easily be designed for this
converter, but for the sake of simplicity the 2
nd
order
compensator with two pole two zero configuration is enough
in order to reveal the performance trade-offs. Although this
compensator is simple to implement, judicious selection of
pole-zero location is required to meet robustness performance
specifications. The SI-SEPIC has three zeros and four poles.
The main steps that are useful at the design stage are: (i)
better speed of response can be achieved through higher
bandwidths, but in reality the loopgain crossover frequency
lies somewhere in the range (f
s
/10 < f
c
< f
s
/5), (ii) the pole at
the origin needs to be placed so as to get a higher low
frequency gain, (iii) in the case where the converter transfer
function has RHP zeros, the maximum achievable bandwidth,
with a single-loop control strategy, is limited by the RHP zero
frequency and the pole-zero placement must be such that it
has the effect of reshaping the loopgain well below the
crossover frequency, and (iv) due to the presence of complex
conjugate pole/zero pairs, the loop gain shows up-down
glitches and if these are near the loopgain crossover
frequency, then the controller pole-zero locations must be
properly chosen so as to avoid multiple crossover points.
These are only a few important guidelines to the designer and
the final design trade-off depends on several factors, wherein
the designer has to use engineering judgment to ensure the
nominal as well as robust performance specifications are
achieved.
( ) ( ) ( ) ( ) ,
v c v d p
T z G z G z G z =
(10)

1 2
3
( )( )
( )
( 1)( )
v
cv
k z a z a
G z
z z a

=

(11)
Among the listed transfer functions the control-to-output
transfer function, G
vd
(z), is required while designing the outer
voltage-loop controller. After substituting the required
matrices in the mathematical identities the resulting transfer
function is given by (9). Once having this transfer function
the loop design can easily be carried out and the
corresponding steps explained above the compensator is
designed with the help of MATLAB [11] platform, wherein
almost all linear system theory related functions are readily
available. Check all the closed-loop converter performance
specifications, GM at least 6 dB and PM in between 40
0
~
75
0
, and if the design is not fulfilling the requirements repeat
the process by changing the crossover frequency,
locations of poles/zeros of the compensator.
III. ROBUSTNESS ANALYSIS THROUGH EDGE THEOREM
The presence of uncertain causes variations in the
coefficients of the system's characteristic polynomial. Thus,
the study of uncertain linear time-invariant systems and the
study of families of characteristic polynomials are bound
together. Moreover, if these polynomial families are taken as
sets of coefficient space, then the shape and orientation of
these sets reflect the structure of the uncertainty. Edge
Theorem first introduced by A.C. Bartlett, C.V. Hollot and
Huang Lin based on the above mentioned polynomial
families [8]. The theorem is computationally feasible test for
determining the roots of every member of a polynomial
family. Edge theorem overcomes the disadvantage of the
Kharitonov's Theorem. The polytope of polynomial family
formed, in this theorem will completely describes the case
when the polynomial's coefficients depend linearly on the
uncertainty range and when these parameters are confined to
a specific range. The root locations of the polytope of
polynomial determine the roots of every member of the
polynomial family and decide whether the system is stable
within that uncertain range or not.

Let P
1
(z), P
2
(z) are the polynomials corresponding to the
maximum and minimum uncertain uncertainties. According
to the Edge theorem, the polytope of polynomial is
1 2
( ) ( ) (1 ) ( ) P z P z P z = +


(4)
where, [0, 1]. By changing the value one can easily
generate roots locations against the given parameter
uncertainty.

IV. SIMULATION AND EXPERIMENTAL RESULTS

In order to demonstrate the proposed converter salient
features and its controlling capability a 12 to- 36 V, 25
Watt, split-inductor SEPIC converter has been considered
here, and its parameters are: L
1
=100 H, L
2
=100 H, L
3
=200
H, C
1
=50 F, C
0
=110 F, R= 50 , f
s
= 50 kHz. State-
space models derived in Section II have been used and the
control-to-output transfer function bode plot has been
generated as shown in Fig. 3. It is clear that this transfer
function has flat gain upto the corner frequency and then
dropping at -40 dB/dec in the high frequency region. In order
to stabilize this system a two pole two zero compensators is
now included in the closed-loop and the corresponding
loopgain frequency response plot is also shown in Fig. 3. The
digital controller parameters are: k=0.497, a=0.964, b=0.697,
c=0.867. This loopgain plot is exhibiting a GM= 12 dB,
PM=73
0
which are within the stable limits.

Although higher gain margin is recommended for
robustness point of view, but the corresponding increase in
phase margin gives oscillatory behavior for the dynamic
response, which is indirectly increases the settling time. To
test the controller robustness the roots of polytope
polynomial, generated using edge theorem, have been plotted
for the parameter variation (i) Vg: 15 20 V, (ii) R: 26
50 and the corresponding plots, showing the closed-loop
system pole-zero movement against parameter variation, are
shown in Fig. 4. This clearly indicates that although the
parameter variation is wider range (R: 26 to- 50 ; V
g
: 15
to- 20 V) but, still the designed digital controller maintains
the closed-loop system stability and hence this feature verifies
the robustness of the designed controller.

To validate the analysis and simulation results an
experimental prototype converter with closed controller
realized, controller is realized using ADMC401 DSP, has
been fabricated and then controller regulation capability is
tested for the following cases: (i) load disturbance from 52
26 , (ii) supply voltage change from 15 12 V. The
measured results, Fig. 5, clearly indicate the controller
regulation capability. To test the robustness of the designed
controller the dynamic response of load voltage has been
recorded against gradual variation of the supply voltage V
g
:
15 to- 20 V as shown in Fig. 6. This observation clearly
indicates the robustness of the designed controller and is also
in agreement with the pole-zero plot observations.

Fig. 3. Frequency response bode plot of Gvd, controller and Loopgain
transfer functions.


-1 -0.5 0 0.5 1
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
-1.5 -1 -0.5 0 0.5 1 1.5
x 10
-3
-1.5
-1
-0.5
0
0.5
1
1.5
x 10
-3
0.96 0.97 0.98 0.99 1 1.01 1.02
-0.03
-0.02
-0.01
0
0.01
0.02
0.03

(a) R : 26 250
-80
-60
-40
-20
0
20
40


Magnitude (dB)


10
1
10
2
10
3
10
4
10
5
-720
-540
-360
-180
0
Phase (deg)
Bode Diagram
Frequency (Hz)
Loopgain
vod(z
Gc(z

(b) Vg: 20 15 V
Fig. 4. Trajectory of root of the polytope polynomials, P(z), against
parameter variation.


R: 52 26

Vg: 12 20 V
Fig. 5. Measured dynamic response of the load voltage.



Fig. 6. Controller robustness against gradual supply voltage variation.



IV. CONCLUSIONS
Robust digital voltage-mode controller has been designed
for SI-SEPIC converter and its performance was compared
with the conventional SEPIC converter. These comparisons
suggest that the proposed SI-SEPIC is capable of delivering
higher voltage gains without degrading the steady-state
performance for duty ratios greater than 0.5. Edge theorem
was successfully employed for robustness verification.
Analytical predictions of robustness indicating studies were
validated through experimental results.

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