DIGITAL FUNDAMENTALS AND ARCHITECTURE

UNIT-V CASE STUDY

What is a Microcontroller
A Microcontroller is a programmable digital processor with necessary peripherals.
Both microcontrollers and microprocessors are complex sequential digital circuits meant to
carry out job according to the program / instructions. Sometimes analog input/output
interface makes a part of microcontroller circuit of mixed modeboth analog and digital
nature!.
A microcontroller sometimes abbre"iated #$% u$ or M$&! is a small computer on
a single integrated circuit containing a processor core% memory% and programmable
input/output peripherals. 'rogram memory in the form of ()* flash or )+' *)M is also
often included on chip% as well as a typically small amount of *AM. Microcontrollers are
designed for embedded applications% in contrast to the microprocessors used in personal
computers or other general purpose applications.
Microcontrollers are used in automatically controlled products and de"ices% such as
automobile engine control systems% implantable medical de"ices% remote controls% office
machines% appliances% power tools% toys and other embedded systems. By reducing the si,e
and cost compared to a design that uses a separate microprocessor% memory% and
input/output de"ices% microcontrollers make it economical to digitally control e"en more
de"ices and processes. Mixed signal microcontrollers are common% integrating analog
components needed to control non-digital electronic systems.
Some microcontrollers may use four-bit words and operate at clock rate frequencies
as low as . k/,% for low power consumption milliwatts or microwatts!. +hey will
generally ha"e the ability to retain functionality while waiting for an e"ent such as a button
press or other interrupt0 power consumption while sleeping $'& clock and most
peripherals off! may be just nanowatts% making many of them well suited for long lasting
battery applications. )ther microcontrollers may ser"e performance-critical roles% where
they may need to act more like a digital signal processor 1S'!% with higher clock speeds
and power consumption.
Microcontrollers Vs Micro!rocessors
2. A microprocessor requires an external memory for program/data storage. 3nstruction
execution requires mo"ement of data from the external memory to the
microprocessor or "ice "ersa. &sually% microprocessors ha"e good computing power
and they ha"e higher clock speed to facilitate faster computation.
4. A microcontroller has required on-chip memory with associated peripherals. A
microcontroller can be thought of a microprocessor with inbuilt peripherals.
5. A microcontroller does not require much additional interfacing 3$s for operation and
it functions as a stand alone system. +he operation of a microcontroller is
multipurpose% just like a Swiss knife.
.. Microcontrollers are also called embedded controllers. A microcontroller clock
speed is limited only to a few tens of M/,. Microcontrollers are numerous and
many of them are application specific.
De"elo!#ent$Classi%ication o% #icrocontrollers &In"isi'le(
Microcontrollers ha"e gone through a silent e"olution in"isible!. +he e"olution can
be rightly termed as silent as the impact or application of a microcontroller is not well
known to a common user% although microcontroller technology has undergone significant
change since early 26789s. 1e"elopment of some popular microcontrollers is gi"en as
follows.
3ntel .88. . bit 4588 'M)S trans% 28: k/,! 2672
2
3ntel :8.: : bit
267;
3ntel :852 : bit *)M-less!
.
3ntel :8<2 : bit Mask *)M! 26:8
Microchip '3$2;$;. : bit 26:<
Motorola ;:/$22 : bit on chip A1$!
.
3ntel :8$26; 2; bit
26:4
Atmel A+:6$<2 : bit =lash memory!
.
Microchip '3$ 2;=:77 : bit =lash memory > A1$!
.
De"elo!#ent o% #icro!rocessors &Visi'le(
Microprocessors ha"e undergone significant e"olution o"er the past four decades.
+his de"elopment is clearly perceptible to a common user% especially% in terms of
phenomenal growth in capabilities of personal computers. 1e"elopment of some of the
microprocessors can be gi"en as follows.
3ntel .88. . bit 4588 'M)S transistors! 2672
3ntel :8:8
:8:<
: bit (M)S!
: bit
267.
3ntel :8::
:8:;
2; bit
2; bit
267:
3ntel :82:;
:84:;
2; bit
2; bit
26:4
3ntel :85:; 54 bit 47<888 transistors! 26:<
3ntel :8.:; S?
1?
54 bit
54 bit built in floating point unit!
26:6
3ntel :8<:; 3
MM?
$eleron 33
333
3@
;. bit
2665
2667
2666
4888
A-:8 Ailog! : bit
267;
Motorola 'ower '$ ;82

;84

;85
54-bit

2665
266<
Be use more number of microcontrollers compared to microprocessors.
Microprocessors are primarily used for computational purpose% whereas microcontrollers
4
find wide application in de"ices needing real time processing / control.
Applications of microcontrollers are numerous% starting from domestic applications such as
in washing machines% +@s% air conditioners% microcontrollers are used in automobiles%
process control industries% cell phones% electrical dri"es% robotics and in space applications.
Microcontroller Chi!s
Broad $lassification of different microcontroller chips could be as followsC
Dmbedded Self -$ontained! : - bit Microcontroller
2; to 54 Microcontrollers
1igital Signal 'rocessors
Feat)res o% Mo*ern Microcontrollers
Built-in Monitor 'rogram
Built-in 'rogram Memory
3nterrupts
Analog 3/)
Serial 3/)
=acility to 3nterface Dxternal Memory
+imers
Internal Str)ct)re o% a Microcontroller
Fig. Internal Structure of a Microcontroller
At times% a microcontroller can ha"e external memory also if there is no internal
memory or extra memory interface is required!. Darly microcontrollers were manufactured
using bipolar or (M)S technologies. Most modern microcontrollers are manufactured with
$M)S technology% which leads to reduction in si,e and power loss. $urrent drawn by the
3$ is also reduced considerably from 28mA to a few micro Amperes in sleep modefor a
microcontroller running typically at a clock speed of 48M/,!.
S)##ar+
5
2. :82:; is basically an :8:; with an on-chip pritority controller% programmable timer%
1MA controller and address decoding circuitry. +his processor has been mostly
used in industrial control applications.
4. +he :84:;% another 2; bit enhancement of :8:; has the features like "irtual
management circuitry% protection circuitry and a 2;-MByte addressing capability.
+he :84:; was the first family member designed specifically for use as the $'& in
a multiuser microcomputer.
5. Some of the limitations of the :84:; microprocessor are that it has only a 2;-bit
AE&% its maximum segment si,e is ;. Fbytes and it can not easily be switched back
and forth between real and protected modes. +hese drawbacks are eliminated in 54-
bit microprocessors. +hese microprocessors are not merely more of the same except
bigger and faster. +hey offer some unique features not a"ailable in earlier 2;-bit
processors.
.. 54-bit microprocessors satisfy some major requirements of multitasking/multiuser
systems like higher speed of execution% ability to handle different types of tasks
efficiently% large memory space that can be shared by multiple users% appropriate
memory allocations and the management memory access% data security and data
access etc.
<. 'rotected mode of :85:; is the natural 54-bit en"ironment of the processor. 3n this
mode all instructions and features are a"ailable.
;. *eal-address mode of :85:; is the mode of the processor immediately after reset. 3n
real mode the :85:; appears to programmers as a fast :8:; with some new
instructions. Most applications of the :85:; will use real mode for initiali,ation
only.
7. @irtual :8:; mode of :85:; also called @:; mode! is a dynamic mode in the sense
that the processor can switch repeatedly and rapidly between @:; mode and
protected mode. +he $'& enters @:; mode from protected mode to execute an :8:;
program% then lea"es @:; mode and enters protected mode to continue executing a
nati"e :85:; program.
:. A flat address space consisting of a single array of up to . gigabytes. A segmented
address space consisting of a collection of up to 2;%5:5 linear address spaces of up
to . gigabytes each.
6. +he :85:; supports a "ariety of data types which gi"es a lot of flexibility to the
programmer so that it is easy to write efficient programs.
28. +he :85:; contains a total of sixteen registers that are of interest to the applications
programmer.
22. +he segment registers of the :85:; gi"e systems software designers the flexibility to
choose among "arious models of memory organi,ation.
24. +he :85:; supports a "ariety of addressing modes and hence it is possible to
compute the effecti"e address of the operand in different ways. +his gi"es a lot of
flexibility in arranging the data of the program.
25. +he :85:; is able to handle the interrupts in both synchronous and asynchronous
modes.
2.. +he :85:; supports both memory mapped 3/) as well as direct 3/).
2<. +he major enhancements made in 'entium processors o"er :8.:; $'& are an
impro"ed cache structure% a wider data bus width% a faster numeric coprocessor% a
dual integer processor and branch prediction logic
Intel ,-.,/
+he 3ntel :84:; also called iA'? 4:;!% introduced on 2 =ebruary 26:4% was a 2;-
bit x:; microprocessor with 25.%888 transistors. Eike the :82:;% it could correctly execute
most software written for the earlier 3ntel :8:; and :8::. 3t was employed for the 3BM
'$/A+% introduced in 26:.% and then widely used in most '$/A+ compatible computers
until the early 2668s. +he :84:; is the first member of the family of ad"anced
microprocessors with memory management and wide protection abilities.+he :84:; is a 2;
bit processor running on a 2; bit bus with a 4. bit address. 3t can address 2;mb of memory.
+he :84:; is the most powerful 2;-bit processor in the :8:; series of
microprocessors% which includes the :8:;% the :8::% the :82:;% the :82::% and the :84:;.
3t is designed for applications that require "ery high performance. 3t is also an excellent
.
choice for sophisticated Ghigh endG applications that will benefit from its ad"anced
architectural featuresC memory management% protection mechanisms% task management% and
"irtual memory support.
+he :84:; pro"ides% on a single @ES3 chip% computational and architectural
characteristics normally associated with much larger minicomputers.+he :84:; was the
chip used in 3BM9s A+ ad"anced technology! system. +he 4:; was the first major step up
in '$ processors% pro"iding significant performance increases o"er the :8:: and :8:;--
double or more performance at the same clock speed. +he 4:; also widened the address bus
to allow access to 2; MB of memory% and introduced protected mode operation. 3t was
originally a"ailable in ; M/, and : M/, "ersions% but was later expanded to faster
"ersions% all the way up to 48 M/,.
+he 4:; opened up the '$ world to many users% but still was used mainly as the
equi"alent of a Gturbo-charged :8::G. At this time 1)S was still the "irtually exclusi"e
operating system% and the protected mode the 4:; offered was largely ignored.
3n real mode% it operates the same as an :8:;. +his is the power on reset state. 3n
protected mode% the segment register changes meaning. 3nstead of a segment address left
shifted by . base address!% the segment register is an index into a page descriptor table%
which is a table that supports "irtual mode. Dach element in the page descriptor table also
contains information about the protection status of that page% so that page protection can be
pro"ided. &nfortunately% since the meaning of the segment register changed% the :84:; was
not object code compatible with programs written for the :8:;/:8::. +his is one of the
factors that made the :84:; unpopular.
Architect)re
+he bus unit B&! in the de"ice performs all memory and 3/) readsand writes%
prefetches instruction bytes% and controls transfer of data
toand from processor extension de"ices such as the :84:7 mathcoprocessor.
+he instruction unit 3&! fully decodes up to three prefetchedinstructions and holds
them in a queue% where the execution unit canaccess them.
+he execution unit D&! uses its 2;-bit AE& to executeinstructions it recei"es from
the instruction unit.
+he address unit A&! computes the physical addresses that willbe sent out to
memory or 3/) by the B&. +he :84:; can operate in one of two memory address
modes% real address mode or protected "irtualaddress mode. 3f the :84:; is
operating in the real address mode% theaddress unit computes addresses using a
segment base and an offset just as the :8:; does.
+he processor extension request 'D*DH! input pin willbe asserted by a coprocessor to
tell the :84:; to perform a data transfer to or from memory for it. Bhen the :84:; get
<
around to do the transfer%it asserts the processor extension acknowledgement 'DA$FI!
signal tothe coprocessor to let it know the data transfer has started.
+he B&SJsignal input on the :84:; functions the same way as the +DS+2I inputdoes
on the :8:;. Bhen the :84:; execute a BA3+ instruction% it
willremain in a BA3+ loop until it finds the B&SJI signal from thecoprocessor high. 3f a
coprocessor finds some error during processing%it will assert the D**)*I input of the
:84:;.
+he :84:; was designed for multi-user systems with multitasking applications%
including communications such as automated 'B?s! and real-time process control. 3t had
25.%888 transistors and consisted of four independent unitsC address unit% bus unit%
instruction unit and execution unit% which formed a pipeline significantly increasing the
performance. 3t was produced in a ;:-pin package including 'E$$ 'lastic Eeaded $hip
$arrier!% E$$ Eeadless chip carrier! and 'KA 'in Krid Array! packages.
+he intel :84:; had a 4.-bit address bus and was able to address up to 2; MB of
*AM% compared to 2 MB for its predecessor. /owe"er cost and initial rarity of software
using the memory abo"e 2 MB meant that :84:; computers were rarely shipped with more
than one megabyte of *AM.
Mo*es o% 0!eration
+he :84:; can be operated in either of two different modesC *eal Address Mode or
'rotected @irtual Address Mode also referred to as 'rotected Mode!. 3n either mode of
operation% the :84:; represents an upwardly compatible addition to the :8:; family of
processors.
3n *eal Address Mode% the :84:; operates essentially as a "ery high-performance
:8:;. 'rograms written for the :8:; or the :82:; can be executed in this mode without any
modification. Such upward compatibility extends e"en to the object code le"el0 for
example% an :8:; program stored in read-only memory will execute successfully in :84:;
*eal Address Mode. An :84:; operating in *eal Address Mode pro"ides a number of
instructions not found on the :8:;. +hese additional instructions% also present with the
:82:;% allow for efficient subroutine linkage% parameter "alidation% index calculations% and
block 3/) transfers.
+he ad"anced architectural features and full capabilities of the :84:; are reali,ed in
its nati"e 'rotected Mode. Among these features are sophisticated mechanisms to support
data protection% system integrity% task concurrency% and memory management% including
"irtual storage. (e"ertheless% e"en in 'rotected Mode% the :84:; remains upwardly
compatible with most :8:; and :82:; application programs. Most :8:; applications
programs can be re-compiled or re-assembled and executed on the :84:; in 'rotected
Mode.
A**ressin1 Mo*es
+he :84:; supports eight addressing modes to access the operands stored
in memory. +hey are *egister )perandMode% 3mmediate )perand Mode% 1irect Mode%
*egister Mode% BasedMode% 3ndexed Mode% Based 3ndexed Mode% and Based 3ndexed
Modewith 1isplacement.
+he information encoded in an :84:; instruction includes a specification of the
operation to be performed% the type of the operands to be manipulated% and the location of
these operands. 3f an operand is located in memory% the instruction must also select%
explicitly or implicitly% which of the currently addressable segments contains the operand.
+he fi"e elements of a general instruction are briefly described below.
+he opcode is present in all instructions0 in fact% it is the only required element. 3ts
principal function is the specification of the operation performed by the instruction.
;
A register specifier.
+he addressing mode specifier% when present% is used to specify the addressing mode
of an operand for referencing data or performing indirect calls or jumps.
+he displacement% when present% is used to compute the effecti"e address of an
operand in memory.
+he immediate operand% when present% directly specifies one operand of the
instruction.
)f the four elements% only one% the opcode% is always present. +he other elements may or
may not be present% depending on the particular operation in"ol"ed and on the location and
type of the operands.
3n :84:; and in its co-processor 3ntel :84:7!% arithmetic operations can be performed on
the following different types of numbersC
unsigned packed decimal%
unsigned binary%
unsigned unpacked decimal%
signed binary% and
floating point numbers.
By design% the 4:; could not re"ert from protected mode to the basic :8:;-compatible
Greal modeG without a hardware-initiated reset. 3n the '$/A+ introduced in 26:.% 3BM
added external circuitry as well as speciali,ed code in the *)M B3)S to enable special
series of program instructions to cause the reset% allowing real-mode reentry while
retaining acti"e memory and control!. +hough it worked correctly% the method imposed a
huge performance penalty.
3n theory% real-mode applications could be directly executed in 2;-bit protected
mode if certain rules were followed0 howe"er% as many 1)S programs broke those rules%
protected mode was not widely used until the appearance of its successor% the 54-bit 3ntel
:85:;% which was designed to go back and forth between modes easily. Bhen 3ntel
designed the 4:;% it was not designed to be able to multitask real-mode applications0 real
mode was intended to be a simple way for a bootstrap loader to prepare the system and then
switch to protected mode.
Intro*)ction to the ,-2,/
+he :85:; is an ad"anced 54-bit microprocessor optimi,ed for multitasking
operating systems and designed for applications needing "ery high performance. +he 54-bit
registers and data paths support 54-bit addresses and data types. +he processor can address
up to four gigabytes of physical memory and ;. terabytes 4
.;
bytes! of "irtual memory.
+he on-chip memory-management facilities include address translation registers%
ad"anced multitasking hardware% a protection mechanism% and paged "irtual memory.
Special debugging registers pro"ide data and code breakpoints e"en in *)M-based
software.
7
+he processing mode of the :85:; also determines the features that are accessible. +he
:85:; has three processing modesC
2. 'rotected Mode.
4. *eal-Address Mode.
5. @irtual :8:; Mode.
'rotected mode is the natural 54-bit en"ironment of the :85:; processor. 3n this
mode all instructions and features are a"ailable.
*eal-address mode often called just Greal modeG! is the mode of the processor
immediately after *DSD+. 3n real mode the :85:; appears to programmers as a fast
:8:; with some new instructions. Most applications of the :85:; will use real mode
for initiali,ation only.
@irtual :8:; mode also called @:; mode! is a dynamic mode in the sense that the
processor can switch repeatedly and rapidly between @:; mode and protected mode.
+he $'& enters @:; mode from protected mode to execute an :8:; program% then
lea"es @:; mode and enters protected mode to continue executing a nati"e :85:;
program.
Me#or+ 0r1ani3ation an* Se1#entation
+he physical memory of an :85:; system is organi,ed as a sequence of :-bit bytes.
Dach byte is assigned a unique address that ranges from ,ero to a maximum of 4
54
-2 .
gigabytes!.
+he architecture of the :85:; gi"es designers the freedom to choose a model for
each task. +he model of memory organi,ation can range between the following extremesC
L A GflatG address space consisting of a single array of up to . gigabytes.
L A segmented address space consisting of a collection of up to 2;%5:5 linear address
spaces of up to . gigabytes each.
Intel ,-2,/ - A 2.-'it Micro!rocessor 4ith Me#or+ 5a1in1 Facilit+
3ntel :85:; is a logical extension of the :84:; microprocessor. +he basic architecture of
:85:; is gi"en here.
:
Fig. Basic architecture of 80386 microprocessor
+he 3nternal Architecture of :85:; is di"ided into 5 sections.

M$entral processing unit
MMemory management unit
MBus interface unit
$entral processing unit is further di"ided into Dxecution unit and 3nstruction unit.
Dxecution unit has : Keneral purpose and : Special purpose registers which are either used
for handling data or calculating offset addresses.
M+he 3nstruction unit decodes the opcode bytes recei"ed from the 2;-byte instruction code
queue and arranges them in a 5- instruction decoded instruction queue.

MAfter decoding them pass it to the control section for deri"ing the necessary control
signals. +he barrel shifter increases the speed of all shift and rotate operations.
M +he multiply / di"ide logic implements the bit-shift-rotate algorithms to complete the
operations in minimum time.
MD"en 54- bit multiplications can be executed within one microsecond by the multiply /
di"ide logic.
M+he Memory management unit consists of a Segmentation unit and a 'aging unit.
MSegmentation unit allows the use of two address components% "i,. segment and offset for
relocability and sharing of code and data.
MSegmentation unit allows segments of si,e .Kbytes at max.
M+he 'aging unit organi,es the physical memory in terms of pages of .kbytes si,e each.
M'aging unit works under the control of the segmentation unit% i.e. each segment is further
di"ided into pages. +he "irtual memory is also organi,es in terms of segments and pages by
the memory management unit.
M+he Segmentation unit pro"ides a . le"el protection mechanism for protecting and
isolating the system code and data from those of the application program.
M'aging unit con"erts linear addresses into physical addresses.
M+he control and attribute 'EA checks the pri"ileges at the page le"el. Dach of the pages
maintains the paging information of the task. +he limit and attribute 'EA checks segment
limits and attributes at segment le"el to a"oid in"alid accesses to code and data in the
memory segments.
M+he Bus control unit has a prioriti,er to resol"e the priority of the "arious bus requests.
+his controls the access of the bus. +he address dri"er dri"es the bus enable and address
signal A8N A52.
+he pipeline and dynamic bus si,ing unit handle the related control
signals.
Feat)res o% ,-2,/6
6
More highly pipelined than :84:;
3nstruction fetching% instruction decoding% instruction execution and memory
management are all carried out in parallel.
54-bit data bus
54-bit non-multiplexed address bus
4
54
O . Kigabyte of physical memory
4
.;
or ;. +erabyte of "irtual memory.
S)##ar+ o% ,-2,/
+his :85:; is a 54bit processor that supports% :bit/54bit data operands.
+he :85:; instruction set is upward compatible with all its predecessors.
+he :85:; can run :8:; applications under protected mode in its "irtual :8:; mode
of operation.
Bith the 54 bit address bus% the :85:; can address upto .Kbytes of physical
memory.+he physical memory is organised in terms of segments of .Kbytes at
maximum.
+he :85:; $'& supports 2;F number of segments and thus the total "irtual space
of .Kbytes P 2;F O ;. +errabytes.
+he memory management section of :85:; supports the "irtual memory% paging
andfour le"els of protection% maintaining full compatibility with :84:;.
+he concept of paging is introduced in :85:; that enables it to organise the
a"ailablephysical memory in terms of pages of si,e .Fbytes each% under the
segmented memory.
+he :85:; can be supported by :85:7 for mathematical data processing
Intro*)ction to ,-7,/6
+he 54-bit :8.:; is the next e"olutionary step up from the :85:;. )ne of the most
ob"ious feature included in :8.:; is a built in math co processor. +his coprocessor is
essentially the same as the :85:; but being integrated on the chip allows it to execute math
instruction about three times as fast as a :85:;/5:7 combination. :8.:; is an :kbyte code
and cache. +o make room for the additional signal% the :8.:; is packed in 2;: pin% pin grid
array package instead of 254 pin 'KA used for the :85:;. +he 54-bit $'& :8.:; from 3ntel
is the first processor with an inbuilt floating point unit.
+he .:; is "ery similar to its predecessor% the 5:;. Main differences are an
optimised instruction set% an on-chip unified instruction and data cache% an optional on-chip
floating-point unit ='&!% and an enhanced bus interface unit. +hese impro"ements yield a
rough doubling in performance o"er an 5:; at the same clock rate.

+he .:; processor has been licensed or re"erse engineered by other companies such
as 3BM% AM1 and $yrix. Some manufacturers made hybrid 5:;/.:; $'&s $xrix
$x.:;1E$% +exas 3nstruments +?.:;1E$!% ha"ing a .:; instruction set and a 5:;-
compatible pinout. +he *apid$A1 is a .:; 1? with 5:; pinout and dummy ='& chip for
upgrading 5:; systems to .:; technology.
)ne of the most ob"ious feature included in a :8.:; is a built in math coprocessor.
+his coprocessor is essentially the same as the :85:7 processor used with a :85:;% but
being integrated on the chip allows it to execute math instructions about three times as fast
as a:85:;/5:7 combination.:8.:; is an :Fbyte code and data cache. +o make room for the
additional signals% the :8.:; is packaged in a 2;: pin% pin grid array package instead of the
254 pin 'KA used for the :85:;.
28
Fig. Basic architecture of 80486 microprocessor
A 52- A4C Address outputs A52-A4 pro"ide the memory and 3/) with the address during
normal operation. 1uring a cache line in"alidation A52-A. are used to dri"e the
microprocessor
A**ressin1 #o*es
89 Scale* in*e:e* #o*e
-$ontent of an index register are multiply by scale factor that may be added further to get
the operand offset.
.9 ;ase* scale* in*e:e* #o*e
-$ontent of an index register are multiply by scale factor that may be then added to base
register to get the operand offset.
29;ase* scale* in*e:e* #o*e 4ith *is!lace#ent
-$ontent of an index register are multiply by scale factor and the result is added to a base
register and a displacement to get operand offeset.
$'& :8.:; 1? from 3ntel is the first 54-bit microprocessor to ha"e an inbuilt floating point
unit. 3t retained the complex instruction set of :85:; but introduced more pipelining for
speed enhancement. :8.:; has fi"e stages of pipelining. +wo out of fi"e stages are used for
decoding complex instructions of :8.:; architecture. +he :8.:; is also the first amongst
the xxx:; processors to ha"e an on-chip cache. +his : Fbytes of cache is a unified data and
code cache and acts on the physical addresses.
(oteC :8.:; S? does not ha"e floating point unit
54-bit address linesC A 4 - A 52 % BD 8 - BD 5 !
54-bit data linesC 1 8 - 1 52 !
Di%%erences 'et4een i2,/ an* i7,/
22
An : FB on-chip le"el 2! S*AM cache stores the most recently used instructions
and data 2; FB and/or write-back on some later models!. +he 5:; had no such
internal cache but like the i.:; supported a slower off-chip cache le"el 4 cache!.
+ightly coupled pipelining allows the .:; to complete a simple instruction like AE&
reg%reg or AE& reg%im e"ery clock cycle. +he 5:; needed two clock cycles for this.
3ntegrated ='& disabled or absent in S? models! with a dedicated local bus0
together with faster algorithms on more extensi"e hardware than in the i5:7% this
gi"es faster floating point calculations compared to the i5:;>i5:7 combination.
3mpro"ed MM& performance.
+he .:; has a 54-bit data bus and a 54-bit address bus. +his required either four
matched 58-pin :-bit! S3MMs or one 74-pin 54-bit! S3MM on a typical '$ motherboard.
Qust like the :85:;% the 54-bit address bus of the :8.:; enabled up to . gigabytes of
memory to be directly addressed using a flat memory model with 54-bit linear addresses in
protected mode. Qust as with the :85:;% the ability to use memory directly without
segmentation helped performance in compliant operating systems and applications.
S)##ar+
2! +hus in sort :8.:; is updated "ersion of :85:;.
4! 3t has :Byte code and cache.
5! 3t is the processor with inbuilt floating point unit
.! 3t has tightly coupled pipelining which allows :8.:; to complete an instruction like a
simple AE&.
<! 3t has the same memory system as :85:; ha"e. Bhich contains the memory addresses
from 88888888/ to ========/.
;! 3t also has in built parity checker and parity generator circuit which is used to check that
a data read from memory is correct or not.
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