Jon Turner

Setup and hold time constraints

Input timing constraints

Clock period analysis

Metastability and synchronizer reliability

Timing Issues in
Digital Circuits
2
Edge-Triggered D Flip Flop

D lip lop stores !alue at D input

"hen clock rises

Most "idely used storage element

or se#uential circuits

Propagation time is time rom rising

clock to output change

I input changes "hen clock rises$

ne" !alue is uncertain

output may oscillate or may remain at

intermediate !oltage %metastability)
D Q
Q >C
&
Timing rules to a!oid metastability
' D input must be stable or setup time beore rising clock edge
' must remain stable or hold time ollo"ing rising clock edge
C
D
Q
setup
hold
min, max propagation delay
(
Implications o Setup Time Constraints
D Q
Q >C
D Q
Q >C
clock
source
combinational
circuit path
x
y
clk
y
x
period
flip flop prop delay
comb circuit delay
setup time
! clock ske"

To a!oid setup time !iolations$ re#uire

period ) %ma* FF prop+ delay, - %ma* comb+ circuit delay,
- %FF setup time, - %ma* clock ske",

C.D tools can check all FF-to-FF paths to !eriy

both component delays and "iring delays matter

accurate estimate re#uires component locations and

inormation about routing o "ires
/
Clock 0eriod .nalysis rom Synthesis
=======================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 4.227ns (frequency: 2!."!#$%&'
Total num(er of pat)s * destination ports: 4" * "
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Delay: 4.227ns (,e-els of ,ogic = '
.ource: state/00d1 (00'
Destination: cnt/2 (00'
.ource Clock: clk rising
Destination Clock: clk rising
Data 2at): state/00d1 to cnt/2
3ate 4et
Cell:in+5out fanout Delay Delay ,ogical 4ame (4et 4ame'
++++++++++++++++++++++++++++++++++++++++ ++++++++++++
0D6:C+57 8 #.!2! 1.12" state/00d1 (state/00d1'
,9T2::1+5; 1 #.478 #.74# /mu<###1=252#/.># (412'
,9T4/,::2+5,; 1 #.478 #.12 /mu<###1=2524/.># (4118'
,9T4::+5; 1 #.478 #.### /mu<###1=254 (/mu<###1=25'
0D.:D #.17! cnt/2
++++++++++++++++++++++++++++++++++++++++
Total 4.227ns (2.28ns logic? 1.8@@ns route'
(".#A logic? 47.#A route'
=======================================================================
synthesis estimates only1
placement and routing
inormation needed or
accurate analysis
FF setup
time
2
Implications o 3old Time Constraints
D Q
Q >C
D Q
Q >C
clock
source
combinational
circuit path
x
y

To a!oid hold time !iolations$ re#uire

hold time 4 %min FF prop+ delay,
- %min comb+ circuit delay, 5 %ma* clock ske",

C.D tools can check all FF-to-FF paths to !eriy

In F60.s$ it is oten the case that

hold time 7 %min FF prop+ delay, 5 %ma* clock ske",
so$ hold time !iolations cannot occur
clk
y
x
hold time
ff delay
cc delay
8
Input Timing

Setup and hold times constrain "hen inputs to a

circuit can change

stable period starts at clock 5 %setup - ma* delay,

and lasts until clock - hold 5 %min delay,

Common simpliication is to hold input stable rom

clock 5 %setup - ma* delay, until clock
D Q
>C
D Q
>C
clock
max
delay path
x
y
min
delay path
#
clk
y,# stable
max delay
x stable
min delay
setup hold
9
Input Delay .nalysis rom Synthesis
=========================================================================
Timing constraint: Default ;00.BT :4 CB0;6B for Clock 'clk'
Total num(er of pat)s * destination ports: 17 * 12
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;ffset: 4."!ns (,e-els of ,ogic = 4'
.ource: d:n (2DD'
Destination: cnt/2 (00'
Destination Clock: clk rising
Data 2at): d:n to cnt/2
3ate 4et
Cell:in+5out fanout Delay Delay ,ogical 4ame (4et 4ame'
++++++++++++++++++++++++++++++++++++++++ ++++++++++++
:C90::+5; 7 #.71" 1.2#1 d:n/:C90 (d:n/:C90'
,9T4::#+5; 1 #.478 #.7#4 /mu<###1=25 (/mu<###1=25/map1
,9T4/,::+5,; 1 #.478 #.12 /mu<###1=2524/.># (4118'
,9T4::+5; 1 #.478 #.### /mu<###1=254 (/mu<###1=25'
0D.:D #.17! cnt/2
++++++++++++++++++++++++++++++++++++++++
Total 4."!ns (2.2@ns logic? 2.#2@ns route'
(".4A logic? 4!.!A route'
=========================================================================
d$n input should be stable$
rom /+(28 ns beore clock
edge$ until clock edge
:
;e!ie" <uestions
=+ Consider a lip lop "ith a setup time o ( ns and a hold time o =
ns+ I the clock input rises at time t$ is it ok or the data input to
change at time t52> ?hat about t5/> ?hat about t-=@2> ?hat
about t-2> E*plain "hy it is not acceptable or the data input to
change at certain times+
2+ Consider the clock period analysis on page /+ 3o" "ould the clock
period change i the lip lop propagation delay "as = ns instead o
+828 and the gate delay or the ABTs "as C+8 ns$ instead o C+/9D>
%Eou may assume that the net delays donFt change+,
(+ Consider a circuit in "hich there is a path rom an input x to a lip
lop that has a ma*imum possible delay o 9 ns$ and there is also a
path rom x to another lip lop "ith a minimum delay o ( ns+ I
the setup and hold times are 2 ns and = ns respecti!ely and the
clock input rises at time t$ is it ok or x to change at time t52> ?hat
about t5=> ?hat about t> ?hat about t5=C>
D
Timing .nalysis 0rocedure
=+ Check or internal hold time !iolations

or e!ery -to- path$ check

%minimum prop+ delay, - %minimum comb+ circuit delay,
) %hold time, - %clock ske",

i* !iolations by adding delay

no !iolations possible i hold-time7%min--prop-delay,5ske"

2+ Determine minimum clock period

ind -to- path "ith largest !alue o

%maximum prop+ delay, - %maximum comb+ circuit delay,
- %setup time, - %clock ske",
(+ Input timing analysis

each input must be stable rom

%clockGedge, %%maximum input-to- delay, - %setup time,,
to %%clockGedge, - %hold time,, %minimum input-to- delay,
/+ Timing analysis or synchronous outputs

synchronous outputs ha!e potential to change any time rom

%clockGedge, - %minimum clock-to-output delay,
to %clockGedge, - %maximum clock-to-output delay,
omit ske" or paths rom
output to input o same
omit ske" or paths rom
output to input o same
=C
Timing .nalysis o Se#uential Comparator
&
Minimum clock period - 2 - 8= - 2 - = H == ns or DC M3z

Input timing re#uirements

'
% and & must be stable rom %clock'edge 5 2, 5 /= until
%clock'edge -=, 5 ( +22$ so rom -8 ns to -+22

Iutput timing - outputs can change +2 to 2 ns ater clock

&
Timing parameters
' gate delayJ C+22 to = ns
' setup timeJ 2 ns
'
hold timeJ = ns
' prop+ delayJ C+2-2 ns
' clock ske"J = ns

Internal hold time !iolation>

' yes - +2 - /%+22, 7 = - =
' add in!erter pair to eedback
paths rom s
==
Combining Circuits

?hen combining t"o components$ check setup

constraints manually
clock period ) %ma* output delay, - %ma* input delay,
- %ma* inter-connect delay, - ske"

Kote$ ske" much larger across dierent

components than "ithin a single component

3old time !iolations unlikely across components

inter-chip delays much larger than %hold time,-ske"

Circuit =

Circuit 2
clk
interconnect
delay
D Q
>C
D Q
>C
ma* input
delay
ma* output
delay
=2
Dealing "ith Timing Failures

To i* hold time errors$ add delay

rarely issue in F06.s$ but can be in .SIC designs

To correct setup time ailures

i you canFt increase clock period$ must reduce delay

ind long delay paths and modiy circuit to reduce

adLust synthesis@implementation properties

ocus on speed optimization$ increase eort le!el

study synthesis report to identiy "orst-case paths

re"rite M3DA to produce aster circuit

e+g+ replace ripple-carry circuits "ith carry lookahead

i need be %and easible,$ insert pipeline registers to di!ide

long combinational paths into smaller parts
=(
Metastability

Most digital systems ha!e asynchronous inputs

keyboard input on a computer$

sensor on a traic light controller$

card insertion on an .TM$ etc+

.synchronous inputs change at unpredictable times

so$ can change during clock transition$ causing

metastability

Iutput o a metastable lip lop can oscillate or remain

at intermediate !alue

leads to unpredictable beha!ior in other lip lops

metastability usually ends #uickly$ but no definite time

limit

so$ circuit ailures due to metastability are una(oidable

ho"e!er$ systems can be designed to make ailures rare

=/
Synchronizers

)ynchroni#ers are used to isolate metastable signals until

they are Nprobably saeO
D Q
>C
D Q
>C
clk
asynchronous
input
potentially
metastable
signal
*probably
safe+ signal
&
I the clock period is long enough$ ailure probability is small
and e*pected time bet"een ailures is large
MTPF H Mean Time Pet"een Failures %T@TC,eT@
"here T is the clock period$ is the a!erage time bet"een
asynchronous input changes$ and TC are parameters o the
lip lop being used

I T H 2C ns$ , = ms$ H = ns$ TC H = ns$ MTPF : trillion

years$ i T H =C ns$ MTPF becomes 22C secondsQ
=2
MTPF Chart
=+E-C2
=+E-C8
=+E-C9
=+E-C:
=+E-CD
=+E-=C
=+E-==
=+E-=2
=C =2 2C 22 (C (2 /C /2 2C 22 8C
T@

M
T
P
F

%
s
e
c
o
n
d
s
,

H= s
= year
= ns = ms =

HT
C
HTC
T@TC
=C years
=8
E*ercises
=+Consider the generic state machine
sho"n belo" "ith the indicated
propagation delays+ I the setup time or
the lip lops is =+2 ns and the ma*imum
clock ske" is +2 ns$ "hat is the smallest
clock period or "hich the circuit is
guaranteed to "ork correctly>
2+ For the state machine sho"n belo"$
assume that the lip lop setup time is 2
ns$ the hold time is C+2 ns and the lip lop
propagation delay is bet"een = and ( ns+
.lso$ that the clock ske" is C+( ns+
Is this circuit subLect to internal hold
time !iolations> Rustiy your ans"er+ ?hat
is the smallest clock period or "hich the
circuit is not subLect to setup time
!iolations> Pe sure to take into account
any modiications rom the pre!ious step+
?hat is the latest time relati!e to the
clock$ "hen it is sae or input & to
change> ?hat is the latest time ater the
clock "hen output - can be changing>
=9
(+Consider a synchronizer used to
synchronize an asynchronous input
signal+ Aet the a!erage time bet"een
changes o the input signal be 2C
microseconds+ Aet the lip lop
parameters be TC H ( ns and H 2 ns+ I
the clock period or the synchronizer is
=C ns$ "hat is the mean time bet"een
synchronizer ailures> ?hat is the
smallest clock period %to the nearest ns,
or "hich the mean time bet"een ailures
is =C years> ?hat is the smallest clock
period or "hich the mean time bet"een
ailures is =C$CCC years>

=:
Solutions
=+ The minimum clock period is
=+2-(-=+2-C+2H8+2 ns+
2+ There are no hold time !iolations
because the minimum lip lop
propagation delay is larger than the hold
time plus the ske"+
The ma*imum delay or the ne*t state
logic is 2 ns+ This gi!es a minimum clock
period o (-2-2-C+(H=C+( ns+
Input & has a ma*imum delay path o 2
ns$ so it must be stable by (-2H2 ns
beore the clock rises+
The latest time ater the clock "hen
output - can be change is (-/H9 ns+

(+ H 2C*=C
-8
$ TC H (*=C
-D
and H
2*=C
-D
$ so or TH=C*=C
-D
$ MTPF H
=89*=C
-8
e
2
H 2/$9(2*=C
-8
seconds or
about 22 milliseconds+ Py trial and
error$ one inds that or TH2( ns the
MTPF is about D+2 years and or TH2/
ns$ it is about =2 years$ so "e need a
target clock period o about 2/ ns to
get a =C year MTPF+ .lso$ by trial and
error$ one inds that or TH88 ns the
MTPF is about 9$8CC years and or
TH89 ns$ it is about =2$:CC years$ so
"e need a target clock period o
about 89 ns to get a =C$CCC year
MTPF+ So$ adding =( ns has impro!ed
the reliability by a actor o =$CCC+