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G.V.Hari Prasad Dr.P.Rajesh kumar V.srinivasa Rao K.Leela Bhavani

Email:leelaklb@gamil.com,gvh.prasad2k@gmail.com

Department Of Electronics & Communication Engineering

Shri Vishnu Engineering College For Women,JNTU Kakinada University

has two separate junctions for the entrance and exit of single

A tunneling transistor is considered to be an element of a future electrons.

low power, high-density integrated circuit because of a possible

ultra-low power operation with a few electrons. In this context,

the performance of SET is compared qualitatively and

quantitatively with CMOS logic gates. Therefore, although a

complete replacement of CMOS by single-electronics is

unlikely in the near future, it is also true that combining SET

and CMOS one can bring out new functionalities, which are un-

mirrored in pure CMOS technology. As the hybridization of

CMOS and SET is gaining popularity, silicon SETs are

appearing to be more promising than metallic SETs for their

possible integration with CMOS Simulation of SET and CMOS

circuits are required for efficient circuit design and analysis.

The macro-modeling technique of SET has been applied to the

SPICE simulation of single-electron/CMOS hybrid circuits.

Transistor,CMOS, Hybrid circuits, SPICE

Fig 1: A Single-electron transistor diagram

Introduction For an electron to hop onto the island, its energy must equal

the Coulomb energy e2/2C. When both the gate and bias

Recently, there has been great progress in the fabrication of voltages are zero, electrons do not have enough energy to enter

various nano-devices utilizing silicon ULSI processing the island and current does not flow. As the bias voltage

techniques. Reliable room temperature operations have been between the source and drain is increased, an electron can pass

demonstrated in a silicon single-electron quantum-dot transistor, through the island when the energy in the system reaches the

a silicon self assembled quantum-dot transistor, and various Coulomb energy. This effect is known as the Coulomb

types of single-electron memory cells. SETs have been widely blockade, and the critical voltage needed to transfer an electron

studied and demonstrated due to the maturity and variety of onto the island, equal to e/C, is called the Coulomb gap voltage.

their process technologies. These devices based on the single- If the bias voltage is kept below the Coulomb gap voltage the

electron charging effect, i.e., the Coulomb blockade in Si increase of gate voltage gradually increases the energy of the

nanostructures, are promising because their operation principle initial system while the energy of the system with one excess

becomes more robust as the device size is scaled down unlike electron on the island gradually decreases. At the gate voltage

MOSFET, which will be further explained in the following corresponding to the point of maximum slope on the Coulomb

section. Moreover, their power consumption is quite low. staircase, both of these configurations equally qualify as the

However, SETs are not expected to replace the conventional lowest energy states of the system. This lifts the Coulomb

CMOS logic devices because of their inherent limitations such blockade, allowing electrons to tunnel into and out of the island.

as a low voltage gain and current drivability. In contrast, new There are three fundamentally different approaches to the

functionalities of SETs, such as quantum cellular automata simulation of single electron circuits: SPICE macro-modeling,

(QCA), binary decision diagram (BDD) devices, and the multi Monte Carlo based and Master Equation based .In this paper,

valued logic, have been explored extensively. the Simulation of SET and CMOS based logic circuits are done

Single-electron tunneling transistor is a device that exploits by Micro-Cap Simulator. The commonly used simulators are

the quatum effect of tunneling to control and measure the MOSES, SIMON, and KOSEC. These simulators are based on

moment of single electrons.Unlike field-effect transistors, a Monte Carlo method. Micro-Cap is a SPICE compatible

single-electron devices are based on an intrinsically quantum method. The SPICE macro-modeling of SET has been

phenomenon: the tunnel effect. This is observed when to successfully applied to the simulation of single-electron/hybrid

metallic electrodes are separated by an insulating barrier about circuits. Several hybrid circuits such as an SET-NMOS pair and

1nm thick. Electrons at the Fermi energy can “tunnel” through a single electron NOR-gate with CMOS buﬀers have been

the insulator, even though in classical terms their energy would

be low to overcome the potential barrier.

simulated and efficient interface characteristics are

demonstrated.

OF SETS

modeling of SETs. The macro modeling scheme is compatible

with the standard method of SPICE simulation, consisting of the

device modeling using an equivalent circuit, parameter

extraction and subsequent circuit simulation. Figure 2 shows the

schematic diagram of an SET and its equivalent circuit. The

macro-model representation of the equivalent circuit is

summarized in Fig.2

In Fig. 2, R1 , R2 , and R3 is expressed with a cosine

function to describe the Coulomb oscillation

And D2, D3, Vp, and −Vp are expressed to describe the

Coulomb staircase. The parameter values, CF 1 = 60,CV p =

0.015, CI2 = 0.2 × 10−9 , CR1 = 300 × 106 , and CR2 = 100 ×

106 , give the best ﬁt of the current-voltage characteristics when

C = 1.6 aF, Cg = 4.8 aF, Rt =100 M Ω, and T = 30 K.

circuit, as depicted in Fig.2. logic ‘0’=Vd=0mv, logic

Fig 2 a. Macro –modeling of an SET (equivalent circuit of an ‘1’=Vd=Vs~qe/C1.The inverting buffer is composed of 2 SET

SET) transistors, where the upper transistor T1 consists of the circuit

elements J1,J2,Cg1,Cb1 and the lower transistor T2 consists of

SIMULATION OF SET & CMOS BASED the circuit elements J3,J4,Cg2,Cb2.

LOGIC GATES When the buffer’s output values changes, a charge

transport of 1qe occurs through one of these two transistors.the

We can construct single-electron logic circuits in which SETs initial tunnel event occurs in either junction J1 (followed by a

can operate analogously to MOSFETs of CMOS logic circuits. tunnel event in junction J2), or in junction J4 (followed by a

The Simulation of SET and CMOS based logic circuits are done tunnel event in junction J3).In each of these two cases, the delay

by Micro-Cap and SPICE software respectively.Since most of associated with the initial tunnel event is approximately one

the readers are very familiar with CMOS logic order of magnitude larger than the delay of the second tunnel

circuits,Schematic of SET logic circuits only are presented event. The total capacitive load attached to a transistor island

here.. (nodes n1 and n3) is assumed to be approximately ½[C1].As a

result, the critical voltage Vc of each tunnel junction is

Inverter approximately Vs, Focusing on T1,and assuming that the input

Complementary single-electron inverter,a Vin is logic ‘0’ and that the charges on nodes n1 and n2 are

fundamental circuit element for single-electron CMOS-type both 0, the initial tunnel event occurs through J1. Afterwards,

logic can be constructed by using twp similar SETs. An the charge on node n1 is qe while the charge on node n2

equivalent circuit is shown in Fig.3 Each SET has two gates. remains 0.Consequently, the voltage across junction J2 resulting

One of them acts as an input gate, and other acts as a control from the initial tunnel event is approximately Vs. In contrast the

gate by which we can use the same SET as a p-switch or an n- initial tunnel event in J1 is triggered when the input Vin

switch. switches between logic ‘0’ and ‘1’.The Fig.4. Shows the Screen

shot of SET inverter using Micro-cap.

Fig. 6. SET- NAND input & output waveforms

CIRCUITS

Figure 8(a) shows an inverter consisting of an SET with an

NMOS load. The bias voltage (Vdd) is 0.015 V and the gate

bias of the NMOS load (Vgg) is 0.5 V so that the NMOS load

operates in the sub threshold region. The output of the inverter

is connected to the 3-stage CMOS buﬀers. Figure 8(b) shows a

Fig .5.Inverter input & output waveforms

hybrid circuit consisting of a single electron NOR-gate

connected with 4-stage CMOS buﬀers. The parameters of MOS

transistors are notiﬁed in the ﬁgure where Wn , Wp , L, tox , VT

N , and VT P denote the NMOS channel width, the PMOS

Fig.5.shows the CMOS based inverter input & output

channel width, the channel length, the gate oxide thickness, the

waveforms. From these waveforms it’s very clear that the SET

NMOS threshold voltage, and the PMOS threshold voltage,

based inverter switches very fast without much delay and

respectively. The channel widths of the ﬁrst CMOS inverter are

voltage swing.Fig.6 & Fig.7 shows the waveforms of NAND

narrower than those of the others to reduce the load capacitance

and NOR.

seen by the SEC. Multi-stage CMOS buﬀers are used for the

ampliﬁcation of the output signal (Vout ) up to the full swing

(±1 V).

Fig. 8. Schematic diagrams of hybrid circuits. (a) An

inverter, consisting of an SET with an NMOS load, connected

with 3-stage CMOS buffers. (b) A single electron NOR-gate

connected with 4-stage CMOS buﬀers.

the hybrid circuit shown in Fig. 8(a). Figure 9(a) shows the

current (Ids) of the SET and the voltage (Vt) at the SET/NMOS Fig. 9. SPICE macro-model simulation results of the hybrid

node as a function of the input bias (Vin). Figure 9(b) shows circuit shown in Fig. 8(a). (a) Ids of the SET and Vt at the

the Vt , Vi (output of the ﬁrst CMOS buffer), and Vout (output SET/NMOS node as a function of Vin. b) Transient

of the third CMOS buffer) when the square pulse is applied to characteristics of Vt , Vi , and Vout when the square pulse is

Vin .The ﬁnal output Vout exhibits a pulse with the amplitude applied to Vin .

of 2 V. Figure 6 shows the SPICE macro-model simulation

results of the hybrid circuit shown in Fig. 8(b). The input buffer stage where the logic levels are settled at the full swing

voltage (Vg1 and Vg2 ) range is ±8 mV and the output of the of ±1 V. However, the above CMOS buffer circuits consisting

single electron NOR-gate (VNOR) is with in the range of ±4 mV. of CMOS inverters have some problem from a practical view-

Especially, the low level of VN OR shows level splitting of ±1 point because of the noise margin or MOS device parameter

mV and ±4 mV . However, the ﬁnal output (Vout) exhibits full variation. In the future, we will be able to simulate hybrid

swing of ±1 V and does not show any level splitting. The range circuits consisting of SEC circuits and new circuits such as the

of VN OR signal is completely in the transition region of the ﬁrst comparators over 10 bits with SPICE macro-model of SETs

stage CMOS inverter. The high and the low signal gradually because the comparators over 10 bits can be designed

diverge from each other as they go through the CMOS buﬀer independently enough to the noise margin or MOS device

stages. The level splitting disappears at the ﬁnal parameter variation.

AND2 4 One SEB

NAND2 4 One SEB+2

SET

NOR2 2 One SEB+2

SET

DELAY ESTIMATION

using(1)

R- Circuit resistance, C- circuit capacitance,

S- VDD- Supply Voltage,Vout-output Voltage.

Fig. 10. SPICE macro-model simulation results of the Propagation Delay Time(PDT) can be estimated from the time

hybrid circuit shown in Fig. 8(b). constant of the circuit RC.The sum of the rise time, fall time &

propagation delay gives the total delay time(2).

All the simulation results reported above clearly show that TABLE 3

SET based logic gates take approximately zero delay time in COMPARISON BASED ON DELAY

propagating the input signal to output side. A number of SET

circuits are discussed and simulated using the macro model for Tr(or) tf PDT TD

single electron transistor. The possibility of simulating hybrid CMOS(ns) 16.95 36.95 70.85

circuits was one of the motivations for developing a macro SET(ps) 116.5 316.5 549.5

model for a single electron transistor. Also a comparison

between the power consumption of single electron transistor POWER LOSS ESTIMATION

and CMOS circuits are made.

TABLE l The power loss estimation of logic system is described in the

The theoretical comparisons between SET and CMOS are: following section. Dynamic Power Loss is calculated using (3)

circuit

Maximal switching speed 10-10s 10-15s CPD - Power Dissipation Capacitor

Supply voltage range 100m 100µV CL - Load Capacitance

Current range nA afew electrons VDD – Supply Voltage

RBC sensitivity none γ f – Switching frequency

Maximum voltage gain high high

Maximum operation >3000C[1 difficult at 300K Static power loss can be estimated from the equivalent circuit

temperature 6] diagram an the parameter mentioned

It’s very clear from (3) that the power dissipation increases

with increase in frequency and decreases with decrease in

voltage level.

The logic circuit diagrams show that the no of transistor Table 4 summarizes the power estimation results,which provide

require to relize different logic gates is less in case of SET the qualitative comparison of CMOS and SET logic circuits.It

based logic system.The number of transistors require for shows that the SET based logic circuit Consume very low

realizing different logic gates using both CMOS & SET power (pico-watt range) where as CMOS circuits consume

technology are given in the Table 2 more power (milli-watt range).

TABLE 2

COMPARISON BASED ON NUMBER OF

TRANSISTOR TABLE 4

CMOS SET COMPARISON BASED ON POWER CONSUMPTION &

NOT 6 2 SET SPEED POWER PRODUCT

OR2 6 One SEB

[4] K.K. Likharev, “Single-electron devices and their

Freq CMOS SET applications,” Proc. IEEE, vol. 87, pp. 606-632, April 1999.

(Mhz) [5] L. Guo, E. Leobandung and S. Y. Chou, Science 275, 649

PT(mw) SPP PT SPP

(1997).

5V 2.5V 1.8V (pJ) (pw) (aJ)

[6] K. Uchida, J. Koga, A. Ohath and A. Toriumi, Tech.

Sys. Sys. Sys. Dig. Of Silicon Nanoelectronics Workshop, 59 (1998).

1 9.43 4.35 1.20 1.886 25.00 2.56 [7]C.Wasshuber and H.Kosina,”A single-electron device and

circuit simulator,” Superlattices and

10 11.05 4.76 1.43 2.21 25.62 2.56 Microstructures,vol.21,no.1,1997.

100 27.25 8.81 3.5 5.55 25.89 2.56 [8] K.Uchida,K.Matsuzawa,J.Koga,R.Ohba,S.Takagi,and

A.Toriumi,”Analytical single-electron transistor(SET) model

1000 189.2 49.3 24.2 37.85 28.54 2.854

for design and analysis of realistic SET

5

circuits,”Jpn.J.Appl.Phys.,vol.39,pp.2321-2324,2000.

10000 1809 454 231 361.8 55 5.5 [9] Y.S. Yu, H.S. Lee, and S.W. Hwang, “SPICE macro-

100000 18009 450 2301 3601 319.6 31.96 modeling for the compact simulation of single electron

4 circuits,” Journal of Korean Physical Society, vol. 33, pp. S269-

S272, Nov. 1998

[10] Y. S. Yu, H. S. Lee and S. W. Hwang, SSDM 98’, 196

As mentioned before the higher integration density is due to (1998).

the fact that these single electron quantum devices are few [11]Y. S. Yu, S. W. Hwang and D. Ahn, IEEE Tran. Electron

nanometers in dimension, this enables more number of devices Devices. 46, 1667 (1996).

to be accommodated in a smaller area. Again these devices are [12] M. Kirihara, N. Kuwamura, K. Taniguchi, and C.

also very power economic in the sense the voltage level at Hamaguchi, “Monte Carlo study of single-electronic devices,”

which these devices work is very less say a few milli-volts in Ext. Abstr. 1994 Int. Conf. Solid State Devices and

when compared to a CMOS device which needs a few volts for Materials, Tokyo, 1994, pp. 328–330

its working. Also the voltage drop across these devices is also

very low resulting in very low power dissipation and also low

temperature rise again enabling more integration density.

CONCLUSION

gates quantitatively as well as qualitatively and compared its

performamce with conventional CMOS technology based logic

gates.The comparison result shows that the SET based gates

consume ultra low power, and switches with very high speed.

The number of transistors require for realizing different logic

gates using SET are also less.These facts indicate that the future

ULSI technology, which requires higher integration, fast

switching and ultra low power consumption can be realized

with SET based logic system. The macro-modeling technique of

SET has been applied to the SPICE simulation of single-

electron/CMOS hybrid circuits. This technique is simple to

perform and does notrequire any modiﬁcation of the SPICE

internal source code.

REFERENCES

electrons in ultra small tunnel junctions,” IBMJ.Res.Develop.,

vol.32,pp.144-158,Jan.1988

[2] R. H. Chen, A. N. Korotkov, and K. K. Likharev, “Single-

electron transistor logic,” Appl. Phys. Lett., vol. 68, pp. 1954–

1956, Apr. 1996

[3] Y. S. Yu, S.W. Hwang, and D. D. Ahn, “Macro modeling of

single-electron transistors for efficient circuit simulation,” IEEE

Trans. Electron Devices, vol. 46, pp. 1667–1671, Aug. 1996.

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