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DELAY ESTIMATION
Fig. 10. SPICE macro-model simulation results of the Propagation Delay Time(PDT) can be estimated from the time
hybrid circuit shown in Fig. 8(b). constant of the circuit RC.The sum of the rise time, fall time &
propagation delay gives the total delay time(2).
All the simulation results reported above clearly show that TABLE 3
SET based logic gates take approximately zero delay time in COMPARISON BASED ON DELAY
propagating the input signal to output side. A number of SET
circuits are discussed and simulated using the macro model for Tr(or) tf PDT TD
single electron transistor. The possibility of simulating hybrid CMOS(ns) 16.95 36.95 70.85
circuits was one of the motivations for developing a macro SET(ps) 116.5 316.5 549.5
model for a single electron transistor. Also a comparison
between the power consumption of single electron transistor POWER LOSS ESTIMATION
and CMOS circuits are made.
TABLE l The power loss estimation of logic system is described in the
The theoretical comparisons between SET and CMOS are: following section. Dynamic Power Loss is calculated using (3)
It’s very clear from (3) that the power dissipation increases
with increase in frequency and decreases with decrease in
voltage level.
The logic circuit diagrams show that the no of transistor Table 4 summarizes the power estimation results,which provide
require to relize different logic gates is less in case of SET the qualitative comparison of CMOS and SET logic circuits.It
based logic system.The number of transistors require for shows that the SET based logic circuit Consume very low
realizing different logic gates using both CMOS & SET power (pico-watt range) where as CMOS circuits consume
technology are given in the Table 2 more power (milli-watt range).
TABLE 2
COMPARISON BASED ON NUMBER OF
TRANSISTOR TABLE 4
CMOS SET COMPARISON BASED ON POWER CONSUMPTION &
NOT 6 2 SET SPEED POWER PRODUCT
OR2 6 One SEB
[4] K.K. Likharev, “Single-electron devices and their
Freq CMOS SET applications,” Proc. IEEE, vol. 87, pp. 606-632, April 1999.
(Mhz) [5] L. Guo, E. Leobandung and S. Y. Chou, Science 275, 649
PT(mw) SPP PT SPP
(1997).
5V 2.5V 1.8V (pJ) (pw) (aJ)
[6] K. Uchida, J. Koga, A. Ohath and A. Toriumi, Tech.
Sys. Sys. Sys. Dig. Of Silicon Nanoelectronics Workshop, 59 (1998).
1 9.43 4.35 1.20 1.886 25.00 2.56 [7]C.Wasshuber and H.Kosina,”A single-electron device and
circuit simulator,” Superlattices and
10 11.05 4.76 1.43 2.21 25.62 2.56 Microstructures,vol.21,no.1,1997.
100 27.25 8.81 3.5 5.55 25.89 2.56 [8] K.Uchida,K.Matsuzawa,J.Koga,R.Ohba,S.Takagi,and
A.Toriumi,”Analytical single-electron transistor(SET) model
1000 189.2 49.3 24.2 37.85 28.54 2.854
for design and analysis of realistic SET
5
circuits,”Jpn.J.Appl.Phys.,vol.39,pp.2321-2324,2000.
10000 1809 454 231 361.8 55 5.5 [9] Y.S. Yu, H.S. Lee, and S.W. Hwang, “SPICE macro-
100000 18009 450 2301 3601 319.6 31.96 modeling for the compact simulation of single electron
4 circuits,” Journal of Korean Physical Society, vol. 33, pp. S269-
S272, Nov. 1998
[10] Y. S. Yu, H. S. Lee and S. W. Hwang, SSDM 98’, 196
As mentioned before the higher integration density is due to (1998).
the fact that these single electron quantum devices are few [11]Y. S. Yu, S. W. Hwang and D. Ahn, IEEE Tran. Electron
nanometers in dimension, this enables more number of devices Devices. 46, 1667 (1996).
to be accommodated in a smaller area. Again these devices are [12] M. Kirihara, N. Kuwamura, K. Taniguchi, and C.
also very power economic in the sense the voltage level at Hamaguchi, “Monte Carlo study of single-electronic devices,”
which these devices work is very less say a few milli-volts in Ext. Abstr. 1994 Int. Conf. Solid State Devices and
when compared to a CMOS device which needs a few volts for Materials, Tokyo, 1994, pp. 328–330
its working. Also the voltage drop across these devices is also
very low resulting in very low power dissipation and also low
temperature rise again enabling more integration density.
CONCLUSION
REFERENCES