EETimes.com - Antenna effect: Do the design rules really protect us? http://www.eetimes.com/news/design/silicon/showArticle.jhtml;jsessi...

1 of 4 22/02/2007 15:39

EE Times: eeDesign News: Silicon Engineering
Antenna effect: Do the design rules really protect us?
Tuvia Liran
(05/23/2003 11:07 AM EST)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=17408334

The "antenna effect" is a common name for the effects of charge accumulation in isolated nodes of an integrated circuit during its
processing. This effect is also sometimes called "Plasma Induced Damage", "Process Induced Damage" (PID) or "charging
effect". In those cases that the discharging of the isolated nodes is done through the thin gate oxide of the transistor, it might cause
damage to the transistors and degrade their performance.
This article will describe the degradation effects, the process steps that might cause it, the existing design rules that should limit
these effects, their limitations and propose improvement solution for these design rules.
PID degradation effects
If charge accumulates on an electrically isolated node of an IC during processing, it can cause any number of problems, ranging
from easily-detected outright failure to more subtle and less detectable problems. The PID may cause "hard" failure if the energy
of the accumulated charge is dissipated on a single spot of the gate oxide. This will cause permanent failure of the transistor.. This
is the extreme case, but most times the damage will appear not as a hard failure, but as degraded performance. This degradation
can be due to any of the following effects:
Increase of gate oxide leakage current.
Increase of the threshold voltage of the transistors, and its variance.
Degradation of the gate oxide life time.
Degradation of the transconductance of transistors.
Increase of the noise generated by the devices.
Increase of hot-electron effects.
While none of these effects would be welcome in digital circuits, the major impact of PID is on the analog circuits that might
suffer from additional mis-match between devices, increase of intrinsic noise, and lower amplification and bandwidth. In these
cases the effects of PID will appear not as a minor variation but as a failure to meet specifications.
The causes of PID
There are several process steps during which charge can accumulate on isolated nodes. Reasonably, these steps all involve
flooding the surface of the wafer with ions in one way or another. The step which dominates the process in terms of potential
damage is the etching of metal and polysilicon, and especially the etch process used with aluminum metallization. This is the step
we will study in more detail in the rest of the article. But it should be noted that damage can also occur during photoresist ashing
by plasma after metal or polysilicon etch, during ion implantation while forming the MOS devices, and during plasma-enhanced
deposition of dielectric on top of the conductors.
Prior to the etch process, the whole wafer is covered by a conductive layer of metal that is shorting all the devices, and hence no
charge can accumulate in any one node. That is also the case during the process of etching by ionized particles (Figure 1a), until
the etching has proceeded far enough into the metal so that patterns have become isolated, enabling the accumulation of charge on
each node separately (Figure 1b). At this stage in the etching process, the wide spaces are disconnected, while the narrow spaces
are not yet completely etched away. At this stage, named the "latent stage", the residual metal at the bottom of the narrow spaces
absorbs the majority of the ion current, and consequently the charge accumulation rate is high.
EETimes.com - Antenna effect: Do the design rules really protect us? http://www.eetimes.com/news/design/silicon/showArticle.jhtml;jsessi...
2 of 4 22/02/2007 15:39
Figure 1: Metal etching steps -- intermediate stage (a); 'latent
stage' (b); over-etching stage (c).
As the etch progresses, the etching of the narrow spaces is completed. Now charge is accumulated at the sidewalls of the metal
patterns (Figure 1c). At this stage the charge accumulation rate is much lower than during the latent stage. Figure 2 illustrates the
rate of charge accumulation versus time for a simplified etch process.
Figure 2: Charge accumulation rate during the metal etch
process.
Actually, the etching process is more complicated, and includes the flooding of the surface of the wafer by electrons during the
etch process. The electron flooding should neutralize the positively-charged ions used in the etching, and hence reduce the total
accumulation of charges. However, during the latent stage, there is a "shadowing" effect in the narrow spaces that reduces the
effectiveness of the electron flooding. Hence there is still charge accumulation in these narrow spaces.
Design rules related to PID
In order to prevent this residual accumulation from damaging circuits, IC manufacturers have defined several types of design
rules. The most common rule is called "antenna ratio". This rule applies to any metal pattern connected to a gate of a transistor. It
defines a limit for the ratio between the area (or the peripheral length) of the metal and the area of the gate oxide of the gate to
which the metal is attached. If there is a diode connected to that node, the restrictions on antenna ratio are relaxed. This rule tends
to limit the amount of charge that might stress the victim gate oxide. Most of the EDA tools that are currently used to check
topological design rules can check antenna ratio rules as well.
There has been considerable question, however, about the effectiveness of these rules. Several leading manufacturers have
EETimes.com - Antenna effect: Do the design rules really protect us? http://www.eetimes.com/news/design/silicon/showArticle.jhtml;jsessi...
3 of 4 22/02/2007 15:39
performed and published experiments on PID, measured on structures similar to those described in Figure 3. The most remarkable
of these experiments has been published by Srikanth Krishnan et al. from Texas Instruments.
Figure 3: Three topologies used for monitoring PID that presented
similar sensitivities.
Pattern 3a has the shape of a comb with narrow spaces between its fingers--generating a large area and peripheral length for
antenna effects. It is connected to a small gate structure of an MOS transistor. In pattern 3b the fingers of the comb are separated,
causing the "antenna ratio" to be much smaller. In pattern 3c the comb structure is separated completely from the victim transistor
with narrow metal gaps with minimum space. Again, the calculated antenna ratio would be very small, as hardly anything is
directly connected to the gate.
But actual measurements showed very little difference in PID between these structures, although there is difference of orders of
magnitude in the "antenna ratio" between the structures.
The reason for this phenomenon is probably related to the "shadowing" effect during the "latent stage" of the metal etches. During
the later stages of the etch, the narrow spaces between the metal islands in patterns 3b and 3c act like fuses. That is, they remain
conducting bridges that accumulate charge, and they are disconnected only at the end of the latent stage, after the majority of the
charge has already been accumulated.
Hence even though these metal structures are, by the end of the etch process, isolated from each other and from the gate, it is
incorrect to treat them as isolated during antenna rule analysis. The experiments demonstrate that the existing design rules do not
consider those cases where a cluster of adjacent patterns are separated from the other patterns by wide spaces.
Implications for design
Figure 4 presents a common pattern that can be generated by any automatic routing S/W, where metal conductors are randomly
placed in the same routing direction. The gray lines are the metal patterns, and the green lines are the narrow spaces that are
shadowed during the latent stage of the metal etch. Such clusters of shadowed areas can be selected by a dedicated set of DRC
(Design Rule Checking) commands. The effective area of such structures for antenna analysis is the sum of all the shadowed
areas for each cluster, and the effective gate area is the sum of all the gates connected to that cluster. If there are diodes connected
to any of these clusters, they should be considered as well. The new "latent antenna ratio", is the ratio between the shadowed
spaces and the sum of gate areas for each cluster. This ratio represents the real situation better than the common antenna ratio.
EETimes.com - Antenna effect: Do the design rules really protect us? http://www.eetimes.com/news/design/silicon/showArticle.jhtml;jsessi...
4 of 4 22/02/2007 15:39
Figure 4: Description of clusters of shadowed spaces that should be
used for calculating the 'latent antenna ratio'.
Is it really important to include this level of estimation in antenna effect rule checking? Unfortunately, not just experiments such
as the one cited here, but also actual design experience indicate that it is. Antenna effect has already caused several failures in
development of new products, including designs by some of the leading IC vendors. Some of these failures affected products that
passed all the checks of the existing design rules. Indeed the probability of failure due to latent effects is low, but the bigger the
die the higher the risk. Beside, why should we take a risk that can be avoided?
In fact there is reason to believe that as we move to denser and higher-frequency circuits, the problem will get worse. One of the
specific implementations that might aggravate the latent effect is the addition of shielding traces parallel to noise-sensitive signals.
Such topology may reduce the noise, but it creates exactly the sorts of structures that are vulnerable to this latent-stage effect.
Hence, using shielding traces without augmenting the design rules might enhance the PID effects, leading for instance to an
increase in offset voltage of amplifiers on the very signals that the designer set out to protect in the first place.
Summary
The PID is one of the process factors that can degrade the performance, reliability and yield of ICs. There are several topological
design rules that tend to limit these effects. However, the existing design rules does not address one of the key issues, and thus do
not provide complete elimination of PID. The key issue is the shadowing effects during the latent stage of the metal etch.
Additional design rules, such as proposed here, are necessary to eliminate this effect completely.
Tuvia Liran is an industry consultant for DFM in Kiriat Tivon, Israel.
All material on this site Copyright 2007 CMP Media LLC. All rights reserved.
Privacy Statement | Your California Privacy Rights | Terms of Service | About