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10, OCTOBER 2011 3587

High-Gain Fully Printed Organic Complementary
Circuits on Flexible Plastic Foils
M. Guerin, A. Daami, S. Jacob, E. Bergeret, E. Bnevent, P. Pannier, and R. Coppard
AbstractWe present several fully printed organic complemen-
tary circuits using n- and p-type organic thin-lm transistors.
n-Type and p-type devices are developed on a exible poly-
ethylene-naphthalate substrate. All organic layers are deposited
using a low-cost screen-printing technique. The inverters show a
high gain and a switching point at exactly V DD/2. Aseven-stage
voltage-controlled oscillator (VCO) is designed with an organic
output buffer, using the n- and p-type organic transistors. This
VCO oscillates at a frequency of 186 Hz. Finally, two complemen-
tary differential ampliers with high gain and large bandwidth are
presented. The ampliers only draw a 1-A current from a 40-V
power supply.
Index TermsAmplier, foil, inverter, organic, thin lm.
URING the last years, strong efforts have been done to-
ward the development of organic electronics, aiming at re-
placing the classic silicon electronics in certain elds such as
chemical sensors, photovoltaic cells, or some radio-frequency
identication applications. The main advantages of organic
electronics, compared with silicon electronics, are its low man-
ufacturing cost and its low-temperature fabrication process [1].
This enables the use of exible plastic substrates, such as
polyethylene naphthalate (PEN) or polyethylene terephthalate
(PET) [2]. Moreover, important work has been carried out in
order to improve the reliability and the performances of organic
thin-lm transistors (OTFT), mainly consisting of improving
the carriers mobility in polymers and stabilizing the fabrication
process to increase the yield. Moreover, as only p-type OTFTs
were available a few years ago, much work was done to obtain
stable and high-performance n-type OTFTs. We present in this
paper n- and p-type OTFTs, which are used to design fully
printed complementary organic circuits on a plastic exible
substrate, where organic polymers are used for the gate dielec-
tric and the channel of the transistors. Only a few fully printed
organic circuits using fast mass-printing technologies have been
reported in [3][7]. Moreover, the manufacture of mass-printed
stable and high-performance n-type transistors is a process that
Manuscript received May 5, 2011; revised June 17, 2011 and July 7, 2011;
accepted July 7, 2011. Date of publication August 18, 2011; date of current
version September 21, 2011. The review of this paper was arranged by Editor
A. C. Arias.
M. Guerin, E. Bergeret, E. Bnevent, and P. Pannier are with Aix-Marseille
University, 13397 Marseille, France (e-mail: Mathieu.guerin@im2np.fr).
A. Daami, S. Jacob, and R. Coppard are with the Laboratoire des Com-
posants Imprims, 38 054 Grenoble, France.
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TED.2011.2162071
is difcult to carry out. Usually, fully printed transistors show
lower performances compared with transistors using vacuum
deposition or photolithography [16]. Nevertheless, fully printed
technology is one of the best ways to develop a very-low-cost
means of production, compared with classic silicon technol-
ogy. Some circuits are designed and measured in this paper.
First, a simple complementary organic inverter is designed,
using an n-type and a p-type transistor. This rail-to-rail inverter
shows a high gain and a switching point at exactly V DD/2. It
also presents a low time delay of 0.43 ms and a cutoff frequency
of 850 Hz. Moreover, repetitive measurements show very good
stability of the inverter. Then, a voltage-controlled oscillator
(VCO) is designed by using a chain of seven fully printed
inverters. This VCO oscillates at a frequency of 183 Hz under
40-V supply. Finally, two differential complementary organic
ampliers are presented in this paper, i.e., using an n-type dif-
ferential pair with a p-type load and using a p-type differential
pair with an n-type load. Both differential ampliers show su-
perior gains and gain bandwidth (GBW) product, compared to
the circuits reported up to now. The n-type differential amplier
works up to frequencies above 1 kHz for symmetric 20-V
supply and has good resistance to repetitive sweeps. The n-type
amplier switches at half of V dd, whereas the p-type amplier
suffers an input offset. Some ways such as a bootstrapped
gain enhancement structure are proposed to solve this problem.
In Section VI, conclusions are drawn, and future works are
Complementary metaloxidesemiconductor devices are
fabricated on a 125-m-thick PEN substrate. A 30-nm gold
(Au) source/drain layer also serving as a rst-level connec-
tion is formed by laser ablation. An organic semiconductor
(polytriarylamine (PTAA) derivative for p-type and acene-
based-diimide for n-type transistors) of about 100-nm thickness
and then an 800-nm-thick dielectric uoropolymer are screen-
printed and annealed, respectively.
Finally, the gate layer, which also serves as a second con-
nection layer, is also screen-printed using a silver (Ag) paste,
giving a thickness of 5 m. A nal annealing at 100

C is then
performed. The process alignment of all printed materials is
about +/ 25 m.
Fig. 1 presents a schematic cross section of the whole
The whole process fabrication and electrical measurements
have been done in air without any sample conservation.
0018-9383/$26.00 2011 IEEE
Fig. 1. Schematic cross section of the fully screen-printed OTFT.
Fig. 2. Transfer characteristic of fully printed organic N-TFT (W = 2000 m
and L = 20 m).
Fig. 3. Transfer characteristics of fully printed organic P-TFT (W =
2000 m and L = 20 m).
Fig. 4. Output characteristics of fully printed organic N-TFT.
DC measurements are performed on the n- and p-type tran-
sistors in order to extract their main features to be able to
simulate them in analog and digital circuits. The width and
length of the transistors are W = 2000 m and L = 20 m,
respectively. The minimal width and length are 140 and 5 m,
First, curves are displayed in Figs. 2 and 3, representing
the transfer characteristics for the n- and p-type transistors,
Fig. 5. Output characteristics of fully printed organic P-TFT.
Fig. 6. (a) Schematic of an inverter using n- and p-type organic TFTs.
(b) Microscopic image of an inverter using n- and p-type organic TFTs.
We show in Figs. 4 and 5 the output characteristics of the
same transistors.
We summarize in Table I the most important parameters
extracted from the measured transistors.
The extracted mobility values are higher than other fully
printed technologies such as [5], and the threshold voltage
variation is about 1 V among the transistors of the same type.
This V
shift may come from the charge trapping. For example,
the trapped holes can decrease the value of the N-OTFT V
A. Circuit Design
Most of the organic inverters reported are only made with
p-type transistors, with the pull-down being made by using a
diode-connected organic p-type transistor or by a zero-VGS
load [9].
The availability of an n-type organic transistor allows us to
get a classic CMOS inverter schematic, meaning a lower
current consumption. The schematic of the organic inverter is
shown in Fig. 6.
Both n- and p-type transistors are multinger devices having
four parallel channels each and of the same sizes. The unitary
Fig. 7. Voltage transfer characteristics of organic inverters for different VDDs.
Fig. 8. GAIN versus VIN characteristics of the inverters for different VDDs.
channel has a length of 20 m and a width of 250 m.
Therefore, the total width of one transistor is actually 1 mm.
B. DC Measurements
Measurements have been carried out on the organic inverter
in order to characterize its performances. The voltages and
the current are applied and measured, respectively, with an
Agilent HP 4156 device analyzer. First, dc measurements were
performed in order to determine the supply voltage range of the
inverter. In Fig. 7, the output characteristic of the inverter versus
the input voltage is displayed. To obtain this curve, a 0 VVDD
sweep with a 50-mV step is applied to the input of the inverter
for supply voltages of 5, 10, 20, 30, and 40 V.
For each curve, it is important to notice that the switching
from high to low output level happens exactly at half of the sup-
ply voltage [5]. This results from the good balancing between
the pull-down and pull-up transistors of the inverter. It is also
interesting to note that the inverter is a rail-to-rail device since
the output voltage swings from 0 V to VDD for each supply
voltage. Another comment can be done about the important
value of the slope, which indicates a high gain.
Fig. 8 shows the gain of the inverter as a function of the
input voltage for different supply voltages. One can see that
the gain is increasing with the supply voltage. The gain reaches
a value of 29 for a supply voltage of 40 V, which is four
times as much as [10][13]. Some inverters with equivalent or
superior gain have been demonstrated ([14] and [15]), but they
are not based on a full printer process, using vacuum deposi-
tion for the conductive polymer layer. This approach does not
permit to carry out low-cost devices since the deposition rate is
0.02 nm/mn. Another study demonstrated higher gain inverters
Fig. 9. Noise margin calculation characteristic.
Fig. 10. Current consumption of the inverters versus VIN.
[16], but the gate insulator is made of atomic-layer-deposited
, which is also a vacuum deposition technique.
To calculate the noise margins of the inverters, the output
characteristic displayed in Fig. 9 is used. The values of VIH
(the high input voltage) and VIL (the input low voltage) are
extracted at the points where the curves slope is equal to
1, and the VOH (output high voltage) and VOL (output low
voltage) values are the output voltages for VIN = 0 V and
VDD, respectively. Then, (1) and (2) are used to determine the
noise margins NMH (high noise margin) and NML (low noise
We obtain high values of noise margins as NMH = 17 V
and NML = 15 V for a supply voltage of 40 V. The noise
margins values are not far from the ideal noise margin value
of VDD/2 = 20 V.
The current consumed by the inverter is also displayed as a
function of the input voltage in Fig. 10. A logarithmic scale is
used to be able to represent, on the sale graph, both a strong
switching current for a 40-V supply and a weak switching
current for the 5-V supply.
The current consumption is almost only present during the
switch and rapidly decreases for voltages before and beyond
VDD/2. This feature, combined with the high noise margin of
the inverters, would allow us to carry out organic circuits with
a high number of transistors and very low static and dynamic
power consumption.
As it is an important request to obtain reliable and stable
devices, the inverters curve needs to have good reproducibility.
Fig. 11. V
versus V
characteristics after 1 and 1000 sweeps at VDD =
40 V.
Fig. 12. Block diagram of the output buffer circuit.
The device was subject to a thousand sweeps of the input
voltage from 0 to 40 V in order to observe the shift of the curve.
The output voltage versus the input voltage after 1 and 1000
measurements is displayed on Fig. 11.
One can observe a 1-V shift of the curve to the right and a
decrease of the gain from 29.2 to 26 dB during the switching.
This shift is very little and shows the good behavior of the
inverters after repeated measurements.
C. AC Measurements
In order to performac measurements on the organic inverters,
it is necessary to present a measurement device with high
impedance. Therefore, an exterior buffer was needed (Fig. 12).
A small-signal sinusoidal input, centered on VDD/2, is ap-
plied on the input of the inverter, and the output is measured
due to an oscilloscope. These measurements are then used
to plot the following frequency response: The low-frequency
0-dB gain corresponds to the maximum gain of the inverter (29)
for a 20-V supply.
In Fig. 13, the graph of the gain as a function of the input
signal frequency is displayed. This curve permits to determine
a 3-dB cutoff frequency of 850 Hz.
A seven-stage VCO is designed, using the inverters previ-
ously described. Fig. 14 shows the schematic of the seven-
stage VCO and the output buffers; due to this organic buffer
designed on the plastic wafer, an exterior buffer was not needed
to connect the VCO to the measurement devices.
It is possible to have an idea of the VCO frequency value by
calculating the time delay of one inverter
Fosc =
2 N Td
Fig. 13. Frequency response of the inverters for VDD = +/ 20 V.
Fig. 14. (a) Schematic of the seven-stage ring voltage VCO. (b) Microscopic
image of the seven-stage ring VCO.
where Fosc is the frequency of the VCO output oscillations,
N is the number of stages (which is seven here) in the VCO,
and Td is the time delay of one inverter. In order to determinate
Td, a relatively high frequency sinusoidal signal (500 Hz) is
applied to the inverter, and the output signal is measured on an
oscilloscope. Due to this method, the delay between the input
and the output is measured, and we obtained a value of Td =
0, 43 ms.
By using (3), the frequency of the VCO can be calcu-
lated with N = 7 and Td = 0, 43 ms. An output frequency of
166 Hz is obtained. From the measurements, an output
frequency of 186 Hz is obtained for a 40-V supply. An output
frequency of 186 Hz is a high value for a fully printed organic
ring oscillator. Indeed, this value is higher than that reported in
[3], [4], [17], or [18], even though our supply voltage is much
higher (40 V, compared with 2 V). Some ring oscillators exist,
with a much higher frequency, such as [19], which demonstrate
a VCO reaching a frequency of 1.1 kHz, but this work uses
photolithography to pattern the organic layers and does not
precise the way the layers were deposited. Moreover, a SiO2
layer is used to make the gate dielectric, which is not the case
in this paper, which relies on fully printed techniques.
A. Circuit Design
Using the same n- and p-type organic fully printed transistors
as in the inverters, two differential ampliers are designed.
Fig. 15(a) shows the amplier based on an n-type differential
Fig. 15. (a) Schematic of the n-type differential amplier. (b) Schematic of
the p-type differential amplier.
Fig. 16. Voltage transfer characteristics of organic n-type differential ampli-
er for different VDDs.
pair, and Fig. 15(b) shows the schematic of the amplier based
on the p-type differential pair.
The sizes of the n- and p-type organic transistors are the
same in both cases, i.e., each transistor has four channels of
L = 20 m and W = 500 m. The supply voltage is either
positive for the n-type amplier or negative for the p-type one.
The differential ampliers are working for supply voltages of
20 V and more. The bias current is set to 1 A for the n-type
differential pair and 1 A for the p-type one. This current can
be supplied by n- or p-type organic transistors, as displayed in
Fig. 4.
B. DC Measurements
DC measurements are rst performed on the differential
ampliers by making a sweep from 40 to +40 V on V
different supply voltages going from 10 to 40 V for the n-type
differential pair and from 40 to 10 for the p-type one. The
obtained curves are displayed in Figs. 16 and 17.
In Fig. 17, one can see that the p-type differential amplier
has an important input offset (14 V) due to V
shift or a
mismatch between the differential pairs transistors. A boot-
strapped gain enhancement topology used in [9] or [20] could
decrease the sensitivity of the ampliers output characteristic
to V
This important offset does not appear on the n-type differen-
tial pairs graph, which has an input offset voltage lower than
1 V, as one can notice in Fig. 18.
From the previous graphs, the gain of the differential ampli-
ers are deduced and plotted in Fig. 18.
Fig. 17. Voltage transfer characteristics of organic p-type differential ampli-
er for different VDDs.
Fig. 18. GAIN versus VIN characteristics of the inverters for VDD = 40 V.
Fig. 19. Voltage transfer characteristics of an organic n-type differential
amplier after 1 and 2000 measures.
The n-type differential pair reaches a gain of 22.4 dB and
has a very low offset, whereas the p-type differential pair has a
gain of 27 dB, which is higher than the n-type pair. Beyond the
switching point, the amplier presents no gain at all.
In order to determine the robustness of the amplier to
repetitive sweeps, a series of 2000 sweeps is applied to the input
of the amplier, and the rst and 2001th output characteristics
are plotted in Fig. 19.
After 2000 sweeps, the dc output characteristic shows a slight
shift from the left to the right, introducing a little input positive
offset of 3 V while the gain decreases from 22.3 to 21.6 dB.
These differences are nevertheless quite insignicant and show
the good behavior of the differential amplier after a certain
number of measurements.
Fig. 20. Bode diagram of the n- and p-type organic differential ampliers.
C. AC Measurements
In order to perform ac analysis, the buffer used for the
inverter characterization is used once again. The following
curves showing the evolution of the gain of the differential
amplier as a function of the frequency are plotted in Fig. 20.
The GBW product of the ampliers can be calculated due to
the equation
GBW= BWG (4)
where BW is the 3-dB cutoff frequency, and G is the gain
during the switch, both measured for a supply of +/20 V.
The p- and n-type differential pairs present a 3-dB cutoff
frequency of 600 and 1025 Hz, meaning a gain band-width
product of 13.2 and 13.36 kHz, respectively.
After the cutoff frequency, both ampliers gains suffer a
20-dB loss per decade.
The p-type differential pair has a GBW superior to [20] and
[21], which show a GBW of 10 and 3.6 kHz, respectively. The
n-type differential pair is the fastest stable n-type differential
amplier reported today to our knowledge. The sensitivity
of the circuit to V
shift involves a decrease in the cutoff
frequency and the dc gain. In order to correct this problem, a
bootstrapped gain enhancement topology will be discussed
in future work in order to raise the dc gain and to make the
circuits insensitive to the V
dispersion [20].
A fully printed organic complementary inverter has been
presented here. Its main features are a rail-to-rail output voltage,
a very high gain of 29 (compared to the published fully printed
inverters) [22], a high speed with a time delay of 0.43 ms, and
good reliability and reproducibility. The total size of the inverter
is only 10 mm
. The main characteristics of the inverters are
summarized in Table II.
A VCO is created using a chain of seven of these inverters.
The VCO oscillates at a frequency of 186 Hz for a 40-V supply,
which is one of the fastest speeds reported. The whole VCO
with an output buffer and the connection pads represents a size
of 225 mm
Finally, two fully printed organic differential ampliers have
been presented. These ampliers are based either on n or
p differential pairs and show a gain band-width product of
13 kHz, which is a reference compared to the differential ampli-
ers presented up to now. The size of the complete fully printed
organic differential amplier is 32 mm
. The main features
of the presented organic differential ampliers are listed and
compared with a reference in Table III. The most important
parameters are the high gain bandwidth product, as well as the
low current consumption of the amplier.
Future work will consist in rectifying the V
sensitivity of the organic fully printed circuits by using some
topologies such as the one presented in [9] or [20].
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M. Guerin, photograph and biography not available at the time of publication.
A. Daami, photograph and biography not available at the time of publication.
S. Jacob, photograph and biography not available at the time of publication.
E. Bergeret, photograph and biography not available at the time of publication.
E. Bnevent, photograph and biography not available at the time of
P. Pannier, photograph and biography not available at the time of publication.
R. Coppard, photograph and biography not available at the time of