I EEE TRANSACTI ONS ON ELECTRON DEVICES, VOL. ED-15, NO.

12, DECEMBER 1968 1009

Low-Temperature Hysteresis Effects in Metal-Oxide-
Silicon Capacitors Caused by
Surface-State Trapping
Abslracf-At low temperatures, charge exchange in all surface
states except those close to the band edges can occur only by capture
of free carriers because emission rates become very slow. If means
are provided to supply minority carriers (either from an extended in-
version layer or in a gate-controlled diode), pronounced charge-trap-
ping effects can be observed.
A ledge in the C-V characteristic is identified as being due to the
charging of almost all surface states within the forbidden gap at a
surface potential dependent on surface-state density, capture cross
section and voltage sweep rate. Capture cross sections at low tem-
peratures can be estimated from the onset of the ledge.
When the C-V curves are traced from accumulation t o inversion
the capacitance drops below the equilibrium minimum value into
depletion and increases rapidly when inversion is reached. This
hook is caused by a barrier against minority carrier flow at the
boundary of the MQS capacitor. The barrier disappears when suffi-
cient voltage is applied to charge the surface states in the boundary
region.
I d
I. INTRODUCTION
OW-TEMPERATURE measurements of metal-
oxide-silicon capacitors are important for a
variety of reasons. The surface-state distribution
close to the band edges can be investigated by the
method described in [l]. The question as to whether a
MOS characteristic is dominated by surface states or
surface charge can often only be answered by perform-
ing a measurement at low temperature. Minority car-
rier generation rates become exceedingly small when
temperature is lowered, an effect which makes MOS
diodes very light sensitive [ 2 J , [ 3] . During the course of
such measurements it was found that a number of
hitherto unexplained features occur in capacitance-
voltage characteristics. Because a complete understand-
ing of all low-temperature MOS phenomena is necessary
before firm conclusions can be drawn from such low-
temperature characteristics, an investigation of the
anomalous characteristics was undertaken.
I n this paper a number of effects will be described
and explained which occur when there is a noticeable
density of surface states combined with an external
source of minority carriers. External sources of minority
carriers are either extended surface inversion or a p-n
Manuscript received May 31, 1968; revised J une 11, 1968.
Murray Hill, N. J . He is now with the Institute for Electronic Ma-
A. Goetzberger was with the Bell Telephone Laboratories, Inc.,
terials Research, Fraunhofer Society, Freiburg, West Germany.
Hill, N. J .
J . C. Irvin is with the Bell Telephone Laboratories, Inc., Murray
-7 I I I
700
I 6o0
i 500
\\ I C
\ I I I DEPLETION
I
I
LL
u
a
-
400
300
200
1 1 1 1 1 1 1 1 1 1 1
-9 -8 -7 -6 - 5 - 4 - 3 -2 - I 0 I 2 3 4 5
Ad
v
Fig. 1. Capacitance-voltage characteristic of p-t:ype 140s capacitor,
oxide thickness 1000 A, measured at liquid Nz temperature with a
1-MHz signal. Note absence of saturation in inversion.
junction within the MOS structure that can supply
minority carriers when properly biased. A structure in-
corporating the p-n junction feature and very suitable
for h40S capacitance measurements is the gate-con-
trolled diode [ 4] , [SI . The results reported here will
be equally applicable to MOS capacitors on inverted
surfaces and to the gate capacitance of gate-controlled
diodes. As will be explained in more detail below, most
of the observed phenomena result from the fact that
surface states are not i n equilibrium with the applied
dc voltage because emission time constants are large
compared to the sweep time.
At room temperature, devices of the kind investi-
gated here exhibit high capacitance in both accumula-
tion and depletion with a minimum in between. The
inversion response occurs by means of charge flow into
and from regions external to the MOS capacitor [ 6 ] , [7].
If there is no external source of charge, the low-tempera-
ture curves are very similar to the room-temperature
pulse [SI , [9] bias curves. I n both cases the minority
carrier concentration is unable to follow the applied
voltage. Therefore the width of the depletion layer is
not limited to the equilibrium value but can increase
until a nonthermal process like avalanche or tunneling
[ 9] supplies minority carriers. An example of such a
curve which is dominated by majority carriers only is
shown in Fig. 1,
45 r I
I I . RESULTS AND INTERPRETATION
A . Relative Importance of Capture and Inversion liy
Surjace States
$35L
I n order to explain the observed low-temperature
characteristics it is necessary to show that charge ex-
change by surface states is much more likely by capture
rate can be changed by change of surface potential
while emission rate cannot. I t can be shown that all
V surface states more than a temperature-dependent
30 than by emission processes. This is so because capture
1
25 I , 2 ( I I 1 I
-15 -10 - 5 0 5 IO 15 20
40 r
30
10
40
-
30
-
U
-
a20
-
0
10
-
0' 4 5 -10 - 5 0 5 IO -15
V
( c >
Fig. 2. MOS characteristics of different capacitors measured at
liquid Nt temperature and 1 MHz. All samples are p-type and
have inverted surfaces. (a) Substrate doping 4.8X10l7 cm-a in-
sulator 880 A of Si8X4. (b) Substrate doping 3X1014, 1000 A of
SiOz.
thermal SOz. (c) Substrate doping 3X 1014, 940 A of thermal
If minority carriers are available, curves like those
shown in Fig. 2(a), (b), and (c) are observed. Although
they are from different samples, they display a number
of common features, the origins of which will be ex-
plored in this paper. The hysteresis effect labeled 3 in
Fig. 2(a) on the inversion side of the curves was found
to be caused by the well-known surface-charge migration
phenomenon which has previously been identified at
room temperature [ 6 ] , [7]. This hysteresis was found to
depend on surface treatment and preceding biasing con-
ditions. I t will not be considered further in this paper
because i t does not seem to be related to the semicon-
ductor-insulator interface.
energy Elirn away from either band edge can be charged
and discharged by capture of free carriers only. The
analysis is carried out for single-level states but the
pertinent results apply also to the more realistic case
of a surface-state continuum.
Using recombination-generation statistics [lo], [ll ]
it can be shown that the time constant for capture of
electrons by surface states is
1
r c =~ (1)
w s
and the emission time constant is
1 e - ( E ~ i k T )
r e = - = - (2)
e, C&i
where C, =capture constant cmz. s-l, n, =free electron
density at the surface ~m- ~, e, =emission constant per
second, ni =intrinsic carrier density, and ET =energy of
surface-state level. Comparison between (1) and (2)
shows that the capture rate can be changed by change
of surface potential (because r c depends on n,) while r e
cannot. Therefore the emission rate determines whether
a surface state at level ET can stay in equilibrium with
a given rate of change of surface potential. The emission
rate of electrons from surface states can be expressed
G, =fATssc,K( T ) exp - -- - -
[ k : e ( 3)
where f =Fermi factor, N, , =surface-state density cmW2,
and K( T) =3.97 X 1016T3/2 ~m- ~. T he activation energy
of (3) is the energy between the trap level and the con-
duction band. An equivalent expression holds for emis-
sion of holes.
A qualitative description of surface-state behavior at
low temperature is as follows. I n an n-type sample all
the surface states are charged with electrons in accumu-
lation. On changing the bias towards depletion, capture
time constants of all surface states decrease because
carrier densities decrease. States very close to the con-
duction band edge are able to emit electrons and thus
follow the changing bias, but most surface states stay
charged negatively until strong inversion with high hole
density p , is reached. Then capture of holes (which have
to be supplied from outside the T\/IOS capacitor) occurs,
GOETZBERGER AND IRVIN: HYSTERESIS EFFECTS IN METAL-OXIDE-SILICON CAPACITORS 1011
charging surface states positively. Thus surface-state
charging and discharging takes place only in a relatively
narrow range of surface potential close to the conduc-
tion or valence band.
At every temperature there is a limiting surface-state
energy Elirn (Fig. 3) beyond which surface states will be
unable to follow the dc bias because their emission rate
is too slow. This level which depends on temperature,
voltage sweep rate and surface-state density will now
be estimated.
The condition used as an approximate criterion is
that, for surface states to follow a given rate of voltage
change =d V/ d t , the emission current G, has to be
equal or greater than the current charging the oxide
capacitance. For electron emission this means
where the equal sign applies to the limiting energy level.
Replacing G, from ( 3) and using the definition of
Elirn =(E,/2) -ET as given in Fig. 3,
qNsscnK(T)e-(Eli,kT) =CoxV. ( 5)
Equation ( 5 ) has been derived under the assumption
that initially all traps are full, i.e., f= 1. Taking the
logarithm of ( 5 ) ,
Elirn is therefore approximately a linear function of
temperature. An analogous expression holds for the
limiting energy level for hole emission:
The low-temperature phenomenon described here can
only be observed when the two critical energy ranges
are not overlapping or
When condition (8) is fulfilled, charge trapped in surface
states in the nonoverlapping range is discharged by
capture, not by emission. This conclusion is not limited
to silicon at low temperature. I t applies also to wide
bandgap semiconductors at room temperature.
B. Experi ment al Resul t s on Gate-Controlled Diodes
Measurements on gate-controlled diodes reveal the
effects just discussed very clearly. Fig. 4 shows a typical
gate capacitance versus substrate bias curve at liquid
nitrogen temperature. The device shown here has been
X-ray irradiated [14] to increase the surface-state
clusions. We want to thank them for a preprint of their work.
Brown and Gray [13] have independently come to similar con-
E,
E STATES
IN EQUILIBRIUM
Elim, n
t
SURFACE STATES
El - - - - -
NOT IN EQUILIBRIUM
WITH D C VOLTAGE
Ellrn, p
IN EQUILIBRIUM
EV
Fig. 3. Schematic band diagram showing three different regions of
surface-state response. E, =conduction band edge, Ey= valence
band edge. Surface states above Eli,,,,,, can :stay in equilibrium
by electron emission, those below E I ~ ~ , ~ by hole emission. Those
in between can only change charge by capture.
Fig. 4. Gate capacitance versus substrate bias curve of gate-con-
trolled diode. Substrate resistivity was 1 hl.cm. This diode was
irradiated to create high surface-state density. Dashed line gives
location of points to which capacitance drifts within one minute
if bias is kept constant.
density.2 The p+ region is shorted during the measure-
ment to the n-substrate. This curve was obtained at 1
MHz with a sweep rate of 0.05 Hz/s. In some portions
of the characteristic there are pronounced drift effects.
The dashed curve gives the location of points to which
the capacitance drifts during one minute at constant
bias.
The curve does not exhibit the hysteresis effect in
inversion labeled 3 in Fig. 2(a). This is another indica-
tion that this effect is caused by surface migration of
charges. In a gate-controlled diode the injecting junc-
tion is under the metal contact and can therefore not be
influenced by surface-charge motion.
The remaining hysteresis effect results from charge
trapping in surface states. Referring to the results of the
preceding sections the top part of the characteristic
(A-+B+C+D+E) can now be understood in the fol-
lowing. Point A is in inversion, all surface states are
child Semiconductor for this device.
a We are indebted to A. S. Grove and D. Fitzgerald from Fair-
1012 I EEE TRAKSACTIONS Oh- ELECTRO?: DEVICES, DECEMBER 1968
filled with holes. I n going towards depletion, point B is
reached where the electrical connection with the p+
region is pinched off. The surface states lying closer to
the valence band than Elim,p in Fig. 3 are able to lose
holes by emission, but all other states are still in their
more positively charged state at point B. At this point,
which is at an applied voltage of about - 15 volts cor-
responding to the positive charge in surface states, the
capacitance increases toward flat-band capacitance. At
point C, where the Fermi level is already close to the
conduction band, the surface electron concentration
becomes high enough so that surface states can dis-
charge by electron capture. Within a rather narrow
range of surface potential between C and D most of
the surface states are discharged by electron capture.
Between D and E they are again in equilibrium with the
applied bias and a normal C-V curve is observed in the
accumulation range.
The shape of the ledge between C and D depends
on the sweep rate V . The downward drift of capacitance
at constant bias in this region is a result of the limited
supply of electrons at constant bias. The time constant
of electron capture depends on electron density accord-
ing to (1). If bias is kept constant electrons are slowly
captured by surface states, which leads to electron
depletion and a concomitant change of surface poten-
tial. The capture process comes to a halt when the
electron concentration n, has become sufficiently low.
The lower part of the characteristic F+B in Fig. 4
is also a consequence of the presence of surface states.
I t will be interpreted in Section 11-E.
C. Calculation of Capture from Onset of Surface-State
Charging
In the ledge region the characteristic is determined
by the equilibrium between filling rate of surface states
and voltage sweep rate. The applied voltage divides
between the oxide and the semiconductor space-charge
region :
v=+,+--+--
Qw Qsc
c o x cox
where Q,, is the charge in surface states and QOe is the
semiconductor space charge. The time derivative of (9)
is
dV . a+, 1 dQS8 1 dQSo
-- - v =-+-- __ +--.
(10)
at at cox at cox at
I n the ledge region of Fig. 4 from C to D most of the
charge goes into surface states. Therefore,
The oxide capacity is charged by a current I :
This current is equated to the surface-state capture
current of (1) ,
a
at
CoxV =qR, =q - ilV,8fct)) =qI~7ss~7L(1 - f)n, (13)
where Rn is the electron capture rate. Equation (13) is
integrated with the condition that the charging starts
at t =Q:
qN,,f =c,,vt. (14)
Equation (14) is now inserted back into (13) :
coxv
cn = (1 5)
%( q N , s - Coxlit)
At the onset of charging, t =0 (point C in Fig. 4) and
(15) reduces to
coxv
% q N , s
Cn5z------.
(1 6 )
N, , is the total number of surface states being filled and
is given by qN,, =CozA V where A V is the width of the
ledge. With this relation the capture rate c, results
from the very simple expression
V
c n=- .
(1 7)
n,AV
If N,, and c, depend on energy, then (17) gives an aver-
age of c, over all surface states between El - Elimjp and
EZ Elirn,n:
JBy A? , , ( E) cn ( E) dE
c, =(6,) = (18)
~EEz ATs s ( E. ) dE
A number of samples were evaluated in this manner.
The values for the capture cross sections C , , ~ = C , , ~ / V ,
(where $ =5 X l o6 cm/s average thermal velocity) were
found to range between and cm2 at 100K
for p and n type. The accuracy of these values was
found to be limited by the precision with which surface
potential could be determined from the C-V curves.
D. Simultaneous Observation of Minority Carrier Injec-
tion and Surface-State Charging
I t had been pointed out previously [ 3] that in sam-
ples not containing an external source (or sink) of
minority carriers, such carriers which were for instance
injected by light can be removed only if a forward bias
is developed across the surface space-charge layer. This
effect results in a ledge region very similar to that ob-
served while surface states are being charged. Under
the appropriate conditions both effects can be seen in
the same characteristic.
Fig. 5 depicts a characteristic obtained in the same
gate-controlled diode shown in Fig. 4 but with the p+
GOETZBERGER AND I RVI N: HYSTERESI S EFFECTS I N METAL-OXIDE-SILICON CAPACITORS
1013
1 I I I I I 1 I S
-25 -20 -15 -10 -5 0 5 IO
Fig. 5. Trace of gate-controlled diode with pt diode disconnected.
At point A light was admitted at constant bias, at point B light
was turned off and return trace started. First ledge is due to mi-
nority carrier injection, second is due to surface-state filling.
region disconnected. The downward trace is typical of
deep depletion (compare Fig. 1). At point A light was
admitted to supply minority carriers and turned off
when point B was reached, and then the return trace
was started. I t can be seen that hole injection dominated
the flat portions from B to C and that the capacitance
then rises to point D where the previously described
charging of surface states starts. The latter part of the
characteristic has a finite slope due to the fact that the
space-charge capacity is a very strong function of sur-
face potential in this range. The minority carrier injec-
tion and the surface-state charging portion of the char-
acteristic are separated only by a relatively small dif-
ferential in surface potential. This results from the
fact that minority carrier injection requires (as deter-
mined from V-I characteristic of a p-n junction) a for-
ward potential of about 0.7 volt. A statement made in
[3] that this voltage is 0.25 volt is in error.
E. ExpEanation of Depletion Book in C-V Characteristics
The hook in the characteristic (feature F-B in Fig. 4)
is a direct consequence of the presence of surface states.
I ts magnitude depends on surface-state density, and it
is always present when there are surface states and an
external source of minority carriers. The explanation of
the effect is based on the fact that a barrier against
minority carrier flow exists at the edge of the external
source.
Fig. 6(a) shows a cross section of a gate-controlled
diode with the edge regior, emphasized. The p+ region
can also represent an external channel. Fig. 6(b) shows
two C-V curves, the measured one and a hypothetical
one which is thought to be taken infinitely slowly such
that the surface states are always in equilibrium. This
characteristic cannot be measured, but it illustrates the
behavior of a very narrow region close to the p-n junc-
tions. This edge region, seen in Fig, 6(a), can come to
Fig. 6. (a) Cross section of gate-controlled diode showing edge re-
gion where barrier against minority carrier flow develops. (b)
Solid curve is experimentally measured characteristic going from
accumulation toward inversion. Dashed curve is equilibrium
curve which is expected to describe edge region where availability
of minority carriers assures thermal equilibrium.
equilibrium because of the availability {of minority car-
riers across the p- n junction. Suppose that the applied
voltage is V, in Fig. 6(b), then the surface potential
around the edge is in equilibrium corresponding to
point 1 while the rest of the MOS capacitor is in deep
depletion corresponding to point 2. This situation is
stable because the edge region is in depletion, having no
conductivity for holes. Thus, no minority carriers can
flow across this region until an equilibrium inversion
layer is established there. That means that all the sur-
face states have to be charged before carriers can flow
into the depleted part of the surface. Once an equi-
librium inversion layer is established in the edge region,
more minority carriers can flow across it, inverting the
center region of the capacitor and simultaneously
charging all the surface states there. This relatively fast
process gives rise to the sharp increase of capacitance.
Based on this model the dependence of the magnitude
of the hook on surface-state density can be calculated.
The measured capacitance C in Fig. 6(b) at any poi nt
between the flat-band and the minimum capacitance
C, z is described by [ 8 ] , [9]:
- V F B
where V p B is the flat-band voltage,
1014 IEEE TRANSACTIONS ON ELECTRON DEVICES, DECEMBER 1968
I
0
0 4 8 12 16 20 24 28 32 36
AV
Fig. 7. Plot of (Cml/Cm# vs. AV for a set of samples where only the
density by AV=qNeY, , /C, , . Solid line is best fit to the data.
surface-state density is changed. A V is related to surface-state
ND =bulk donor density, and e8 =dielectric permittivity
of the semiconductor.
The voltage Vmz at which the curve reaches its mini-
mum Cm2is given by Vmz =Vml+AV where V,I is the
voltage at which the surface-state free MOS capacitor
would have its minimum Cml, and AI is the voltage
offset due to charge in surface states. Thus
(z)2 =1 +
Vm1 f AV - VFB
a2
(20)
and
From (20) and (21) we have
From (22) we conclude that a plot of (C,I/C,Z)~ is
linearly related to the surface-state density N, , =COB V
/ q. Fig. 7 shows such a plot.
111. CONCLUSIONS
Low-temperature silicon MOS curves were shown to
differ in some important aspects from room-temperature
behavior. The presence of an external supply of minor-
ity carriers permits observation of effects caused by
those carriers. The major results of this paper are as
follows.
1) The maj ori ty of deep-lying surface states get
charged and discharged by capture of holes when the
Fermi level is close to the valence band and by capture
of electrons when the Fermi level is close to the conduc-
tion band. This leads to pronounced hysteresis effects
dependent on the surface-state density and temperature
in MOS characteristics.
2 ) In going from inversion towards accumulation the
discharge of surface states is indicated by a ledge in the
characteristic. From the onset of the charging the aver-
age capture cross section of surface states can be found.
3) Going from accumulation to inversion the capaci-
tance drops below the equilibrium minimum value and
increases rapidly when inversion condition is reached.
This hook in the characteristic is caused by the neces-
sity of charging all the surface states in the edge region
bordering the source of minority carriers until a stable
inversion layer exists in this region. Only after this is
accomplished can minority carriers traverse this region
and charge the rest of the capacitor. The magnitude of
the jump of capacitance depends on surface-state den-
sity.
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