designfeature By Ken Holladay, Fujitsu Microelectronics

USING A SIMPLE PROCEDURE AND SET OF EQUATIONS,

YOU CAN EASILY DESIGN A FREQUENCY SYNTHESIZER
TO MEET SPECIFICATIONS BASED ON THE LOOP BAND-
WIDTH INSTEAD OF THE HOP TIME. HOP TIME DEPENDS
ON THE LOOP BANDWIDTH, SO YOU MAY HAVE TO MAKE
COMPROMISES IN THESE TWO SPECIFICATIONS TO MEET
DESIGN REQUIREMENTS.

Design a PLL for a specific

loop bandwidth
oday’s PLL ICs make designing a high-quali- signal. The PLL’s loop bandwidth sets the corner fre-

T ty, versatile frequency synthesizer easier than quency of this response. There are some systems that
ever. These devices have many built-in func- insert the modulation both before and after the loop
tions, such as serial interfaces, phase detectors, and filter to get a flat response.
swallow counters. Typically, the only external parts If you plan to phase- or frequency-modulate the
are the reference oscillator, VCO, loop filter, and dc PLL, the desired loop bandwidth will influence the
decoupling components. Some ICs, such as the MB- choice of the loop-filter component values. There-
15E03SL from Fujitsu (www.fujitsumicro.com ), also fore, you must base the initial design on the desired
have built-in circuitry for a crystal or an LC refer- loop bandwidth. Unfortunately, trade-offs are nec-
ence oscillator. Most of the synthesizer applications essary. A direct relationship exists between loop
are for wireless designs, for which the system speci- bandwidth and hop time: The narrower the band-
fications require the synthesizer to operate over a width, the longer it takes the synthesizer to step from
bandwidth of 10% or less.
Most of the written design information
about calculating the loop filter for these PLL Figure 1
R2
synthesizers is based on how long it takes to “hop” FROM PLL TO VCO
from one frequency to another. This design infor- R1
C1 C3
mation is sufficient if you plan to use the synthesiz- C2
er only as a local oscillator, to convert one frequen-
(a)
cy to another, or as a continuous-wave source at
various frequencies. However, many applications use R2
a synthesizer to modulate a transmitter. In this case, 510
the loop bandwidth may be the controlling factor for R1
the loop-filter design. C1 510 C3
0.12 mF 0.15 mF
You can apply modulation to a synthesizer by C2
1.39 mF
changing the VCO tuning voltage either before or af-
(b)
ter the loop filter. The frequency response of the
modulation at the output of the transmitter will have
either a lowpass or highpass characteristic, depend- For the typical loop-filter configuration (a), you can use a design method
ing on where in the loop you apply the modulating based on loop bandwidth to arrive at standard component values (b).

www.ednmag.com October 12, 2000 | edn 173

designfeature PLL design

one frequency to another. If hop time

is also important, you have to work out
a balance between loop bandwidth and
hop time.
DEFINE THE BASIC REQUIREMENTS
To design a loop filter based on band-
width, instead of the frequency hop or
switching time, consider the following
example. You first define the basic syn-
thesizer requirements:
● Frequency range: 770.01 to 800.01
MHz;
● Channel spacing: 30 kHz;
● Maximum frequency hop: 30
MHz; and
● Loop bandwidth: 1000 Hz.
Then, you identify the active compo-
nent specifications:
● VCO sensitivity: 22 MHz/V and
● PLL IC charge-pump current:
6 mA.
Now, you perform the PLL calcula-
tions for the typical loop-filter config-
uration in Figure 1a. Table 1 lists the
definitions of terms. The basic steps The phase noise at 100 Hz (marker 0) is 172.0 dBc/Hz, and the phase
and calculations for a given loop band- Figure 2
noise at 1000 Hz (marker 1) is 175.5 dBc/Hz.
width are as follows:
1. Calculate FSTEP:
4. Calculate C2: 7. Choose values of R2 and C3:
FSTEP = MAXIMUM VCO FREQUENCY R2 and C3 reduce any spurs that the ref-
1MINIMUM VCO FREQUENCY. ICP × K VCO erence frequency introduces. The prod-
C2 = . uct of R2 and C3 should be at least one-
N × (2 π × FN )2
2. Calculate N: tenth times the product of C2 and R1.
8. Calculate TS:
MAXIMUM VCO FREQUENCY 5. Calculate R1:
N= . 
CHANNEL SPACING F 
11 ×  ln A 
N  FSTEP 
3. Calculate FN: R1 = 2 × ξ × . TS = .
ICP × K VCO × C2 FN × 2 π × 2ξ

2 × LOOP BANDWIDTH STEP-BY-STEP EXAMPLE

FN = . 6. Calculate C1:
 1  FSTEP = 800.01 MHz1
2π ×  ξ +  C2
 4 × ξ C1 = . (1)
10 770.01 MHz = 30 MHz.

800.01e6
(2) N= = 26,667.
TABLE 1—DEFINITION OF TERMS 30e3
Term Description
2 × 1000
FA The frequency of the carrier within the desired time (TS) after a step or hop; FN = =
 1 
normally, 1000 Hz (3) 6.28 ×  0.707 + 
FN Natural frequency  2.828 
FSTEP Maximum frequency change during a step, or hop, from one frequency to another 300.27 Hz.
ICP Charge-pump current
0.006 × 22e6
(4) C2 =
KVCO VCO sensitivity
TS The desired time for the carrier to step to a new frequency 26,667 × (6.28 × 300.27)2
j Damping factor; typically, 0.707 = 1.39 µF.

174 edn | October 12, 2000 www.ednmag.com

designfeature PLL design

TABLE 2—HOP TIMES FOR VARIOUS

LOOP BANDWIDTHS
Loop bandwidth (Hz) Hop time (msec)
500 15.5
1000 7.7 (design example)
2000 3.9
3000 2.6

R1 = 2 × 0.707 ×
(5) 26,667
= 539Ω.
0.006 × 22e6 × 1.39e16

1.39 µF
(6) C1 = = 0.139 µF.
10
7. Let R25539V. Then, C351.39 mF/
1050.139 mF.

 1000 
11 ×  ln 
(8)  30e6 
TS = =
300.27 × 6.28 × 0.707
Figure 3
7.73 msec. The spurs are greater than 296.7 dBc at 30 kHz from the carrier.

Figure 1b shows the completed design

using the closest standard component
values. The measured results of this de-
sign working with an MB15E03SL-based
synthesizer show a close relationship be-
tween the design goals and the actual
performance. Figure 2 displays the phase
noise between 100 Hz and 100 kHz. The
phase noise at 100 Hz (marker 0) is
272.0 dBc/Hz, and the phase noise at
1000 Hz (marker 1) is 275.5 dBc/Hz.
Figure 2 also shows that the loop band-
width is very close to the desired 1000
Hz.
Figure 3 shows that the spurs are
greater than 296.7 dBc at 30 kHz from
the carrier. Figure 4 shows that the hop
time from 770.01 to 800.01 MHz is 7.65
msec. The loop bandwidth mainly deter-
mines this hop time. Table 2 shows the
approximate hop times that result when
you use other loop bandwidths in the de-
sign example.k

Author’s bio graphy

Ken Holladay is applications manager for
the wireless group at Fujitsu Microelec- Figure 4
tronics. He has been with FMI for five years The hop time from 770.01 to 800.01 MHz is 7.65 msec.
and has more than 20 years of industry ex-
perience.

176 edn | October 12, 2000 www.ednmag.com