Operating Systems Lecture Notes

Lecture 11
MIPS TLB Structure
Martin C. Rinard
Case Study: A simple VM and paging system for the MIPS R3000.
Start with arhiteture. !ere is the memory hierarhy of the mahine at hand:
o "irst #e$el Cahe. %&' (ytes) diret mapped. *rite alloate) write through.
Physially addressed.
o *rite +uffer. & ,ntries.
o Seond #e$el Cahe. -.%' (ytes) diret mapped. *rite (a/.
o Physial Memory. %&M (ytes. &' page frames.
o +a/ing Store 0is/. -.%M (ytes of swap spae.
Address format. Are two modes: user mode and /ernel mode. 1op -0 (its are Virtual Page
2um(er) (ottom 3- (its are page offset. Mahine has a % (it urrent proess id4 proess id
is part of 35 (it $irtual address. All user mode addresses ha$e a top address (it of 0. !ow
(ig is potential user address spae6 !ow (ig are pages6
'ernel mode addresses.
o If address starts with 0) is mapped 7ust li/e urrent user proess. So) user proess
address spae is su(set of 8S address spae. Called /useg.
o If address starts with 300) translates to (ottom .3- M(ytes of physial memory
and does not go through 1#+. 9ahed and unmapped:. Called /seg0. ;sed for
/ernel instrutions and data.
o If starts with 303) translates to (ottom .3- M(ytes of physial memory. Is not
ahed 9unahed) unmapped:. Called /seg3. ;sed for dis/ (uffers) I<8 registers)
R8M ode.
o If starts with 33) is mapped and ahea(le. Maps differently for eah proess.
Called /seg-. ;sed for /ernel data strutures in whih there is one per address
spae = user page ta(les) et.
Speifiation of mapping proess: must map 33 (it $irtual address 9top (it is always 0:
plus % (it proess id to 3- (it physial address. 0o mapping (y first mapping upper 3>
(its of $irtual address plus % (it proess id to a physial page frame) then using lower 3-
(its of $irtual address as offset within the physial page frame.
!ow do we map upper 3> (its of $irtual address6 ;se a linear page ta(le stored in /seg-.
!ow (ig an this page ta(le (e6
2ote that we will also (e paging /seg- using a linear page ta(le. *here do we hold the
page ta(le for /seg-6 1here is one for eah proess) and it is stored in /seg0. If the page
ta(le for the user proess stored in /seg- ta/es up most of the used address spae) how
(ig an the page ta(le for /seg- stored in /seg0 (e6
In effet) we ha$e a two le$el approah. ?i$en a 3- (it $irtual address from /useg) we get
the physial address as follows:
o ,@trat top > (its of address. ;se this as an inde@ into that proessAs /seg- page
ta(le stored in /seg0. 1he memory in /seg0 is always there and the referene goes
unmapped) so there will (e no pro(lem will this loo/up. *e get the physial page
frame that holds the rele$ant part of the page ta(le in /seg-. If the page is not
resident) read it (a/ in from dis/.
o ,@trat middle 30 (its of address. 1his is the amount you need to inde@ one page
of & (yte physial addresses. ;se the middle 30 (its to inde@ the page ta(le in
/seg-. 1his loo/up yields a physial page frame in /useg. If the page is not
resident) read it (a/ in from dis/. Must ma/e sure that we are aessing the
orret memory for the urrent proess id sine /seg- maps differently for eah
proess id.
o ,@trat lower 3- (its of address. ;se this as an offset into the physial page frame
holding the page from /useg. Read the memory loation.
*hy di$ide the loo/up into two stages6 So we an page the $irtual address spae A20
page the page ta(le. 1he page ta(le for $irtual address spae is stored in the part of /ernel
address spae that is mapped differently for different proesses. 1he page ta(le page ta(le
is stored in unmapped (ut ahed /ernel memory.
Seems ineffiient = 3 memory aesses for one user memory aess. So) speed it up with
a 1#+. %& entry fully assoiati$e 1#+. ,ah entry maps one $irtual address to one
physial page frame.
1#+ entry format. ,ah 1#+ entry is %& (its long.
o 1op -0 (its: VP2.
o 2e@t % (its: PI0.
o 2e@t % (its: unused.
o 2e@t -0 (its: Physial page frame.
o 2e@t (it: 2 (it. If set) memory aess (ypasses the ahe. If not set) memory
aess goes through the ahe.
o 2e@t (it: 0 (it. If set) memory is writea(le. If not set) memory is not writea(le.
o 2e@t (it: V (it. If set) entry is $alid.
o 2e@t (it: ? (it. If set) 1#+ does not he/ PI0 for translation.
!ow does loo/up wor/6 +asi idea: math on upper half of 1#+ entry) use lower half of
1#+ entry. Can generate three different /inds of 1#+ misses) eah with its own e@eption
handler.
o ;1#+ miss = generated when the aess is to /useg and there is no mathing
mapping loaded into the 1#+.
o 1#+ miss = generated when the aess is to /seg0) /seg3) or /seg- and there is no
mapping loaded into 1#+. Also generated when the mapping is loaded into 1#+)
(ut $alid (it is not set.
o 1#+ mod = generated when the mapping is loaded) (ut aess is a write and the 0
(it is not set.
!ere is the 1#+ loo/up algorithm:
o If MS+ is 3 and in user mode) generate an address error e@eption.
o Is there a VP2 math6 If no) generate a 1#+ miss e@eption if MS+ is 3)
otherwise generate a ;1#+ miss.
o 0oes the PI0 math or is the glo(al (it set6 If no) generate a 1#+ miss 9if MS+ is
3: or ;1#+ miss 9if MS+ is 0:.
o Is $alid (it set6 If no) generate a 1#+ miss.
o If 0 (it is not set and the aess is a write) generate a 1#+ mod e@eption.
o If 2 (it is set) aess memory) otherwise aess ahe 9whih may refer aess to
memory:.
1he PI0 field allows multiple proesses to share the 1#+. *hat if there was no PI0
field6 1he PI0 field is only % (its long. *hat if reate more than %& user proesses6
Manipulating 1#+ entries. Proessor must (e a(le to load new entries into 1#+. +asi
Mehanism: 1wo 3- (it 1#+ registers: 1#+ ,ntry!i) 1#+ ,ntry#ow. +its are the same
as for %& (it 1#+ entry. ,ntry!i register holds urrent PI0 that is part of all $irtual
addresses. Also ha$e an Inde@ register: % (its that an (e set (y software) and a Random
register: % (it register deremented e$ery lo/ yle. Constrained not to point to first 5
entries.
Can load into 1#+ entry registers under program ontrol) then store ontents of ,ntry
registers either to 1#+ entry to whih inde@ register points) or to whih random register
points.
1#+ instrutions:
o mt0 = loads one of 1#+ registers with ontents of a general register.
o mf0 = reads one of 1#+ registers into a general register.
o tl(p = pro(es the 1#+ to see if an entry mathes ,ntry!i. If so) loads inde@
register with inde@ of 1#+ entry that mathed. If no math) sets upper (it of inde@
register.
o tl(r = loads ,ntry!i and ,ntry#ow with ontents of 1#+ entry that inde@ register
points to.
o tl(wi = writes 1#+ entry that inde@ points to with ontents of ,ntry!i and
,ntry#o registers.
o tl(wr = writes 1#+ entry that random register points to with ontents of ,ntry!i
and ,ntry#o registers.
*hat happens when there is a ;1#+ or 1#+ miss6 8S must reload 1#+ and restart the
faulting proess. 2ote = the ;1#+ and 1#+ miss e@eptions (ranh to different handlers.
Mahine state for e@eptions:
o ,PC register: points to instrution that aused fault) unless faulting instrution
was in (ranh delay slot. If so) points to (ranh (efore (ranh delay slot
instrution. +asi idea: when fi@ up e@eption and return to user ode) will (ranh
to ,PC.
o Cause register. 1ells what aused e@eption) and maintains some state a(out
interrupts.
o Status register. Contains information a(out status of mahine. Important (its:
'ernel<;ser mode (it) Interrupt ,na(le (it. 8S maintains a 3 deep sta/ of these
(its) shifting them o$er on an e@eption. So) an ta/e two e@eptions without
ha$ing to e@trat and store the (its.
o +adVaddr register = stores $irtual address that aused last e@eption.
o Conte@t register. ;pper 33 (its = set under program ontrol. 2e@t 3> (its = set to
VP2 of address that aused e@eption 9omits top (it:. #ast - (its = always 0.
*hat does mahine do on a ;1#+ miss6
o Sets ,PC register.
o Sets Cause register.
o Sets Status register. Shifts '<; and I, (its o$er one) and lears urrent
'ernel<;ser and Interrupt ,na(le (its. So = proessor is in /ernel mode with
interrupts turned off.
o Sets +adVaddr register = stores $irtual address that aused e@eption.
o Sets Conte@t register. ;pper 33 (its = left alone. 2e@t 3> (its = set to VP2 of
address that aused e@eption 9omits top (it:.
o Sets 1#+ ,ntry!i register to ontain VP2 of faulting address.
*hat does 8S do in ;1#+ handler6
o Store ,PC register to /t3 register 9software on$ention) 8S has two registers
reser$ed for its use:.
o #oad onte@t register into /t0 register.
o #oad ontents of memory address that /t0 points to into /t0. Into what part of
address spae does /t0 point6
o #oad /t0 into entry low 1#+ register.
o #oad 1#+ entry registers into 1#+ entry that random register points to.
o BR /t34 rfe instrution in (ranh delay slot. rfe instrution pops (its in Status
Register.
*hat is going on6 8S uses a linear page ta(le for eah proess) starting at address stored
in upper 33 (its of onte@t register. ,ah page ta(le entry is the 3- lower (its of a 1#+
entry. So) 8S 7ust fethed the 1#+ entry and stored it into a random loation in 1#+) then
started up the program again.
*hat are upper two (its of onte@t register6 33 = so) this is /ernel memory that is mapped
separately for eah proess. 2e@t > (its are (ase of page ta(le in mapped) proess=speifi
/ernel spae. So) eah proess has its own page ta(le.
,rror ases:
o *hat if page is not in memory6 1hen 8S will store a Cero in the $alid (it of page
ta(le entry. Program will ree@eute faulting instrution) generating a 1#+ miss
e@eption. 9281 a ;1#+ miss e@eption:.
o *hat if address is out of (ounds6 8S stores nothing a(o$e the page ta(le in
address spae) so will get a 1#+ miss 9281 a ;1#+ miss:. 1his generates a
dou(le fault that 8S will handle in general e@eption handler.
o *hat if page ta(le page is not mapped or it is not in memory6 Another dou(le
fault.
o *hat if faulting instrution was in a (ranh delay slot6 ,PC points to (ranh) so
will ree@eute (ranh instrution. 2o pro(lem = in R3000) all (ranh instrutions
are ree@euta(le with same effet.
o *hat if are inside /ernel when ta/e a ;1#+ miss6 !ow does miss handler /now
whih state to return to6 Is stored automatially in Status register) and
manipulated (y e@eptions and rfe instrution.
R3000 arefully designed to support this effiient ;1#+ reload mehanism.
o Some /ernel addresses are mapped differently for different proesses. So) an
store per=proess page ta(les there.
o 1#+ entry format laid out so that it mathes possi(le page ta(le entries.
o All (ranhes are restarta(le = they do not depend on mahine state.
o ;1#+ miss handler is in a different loation than normal e@eption handler =
supports fast ode. 0onAt ha$e to deode ause of e@eption.
o Sets onte@t register appropriately.
o Supports three le$els of 'ernel<;ser mode and interrupt ena(le<disa(le (its) so
an ta/e two faults in a row without needing to sa$e state. Supports dou(le fault
mehanism for fast handling of unommon ases.
*hat must 8S do when it swithes onte@ts6 Must set ,ntry!i of 1#+ to ontain urrent
proess id. Must also load top 33 (its of onte@t register with page ta(le (ase.
*hat happens on a 1#+ miss 9as opposed to a ;1#+ miss:.
o Sets ause register = an (e 1#+ mod miss) or 1#+ miss. 1#+ mod miss is when
1#+ entry mathes (ut operation was a store and 0 (it was not set.
o Sets +adVaddr register.
o Sets ,PC.
o Shifts (its in Status register.
o Sets onte@t register.
o Sets 1#+ ,ntry!i register.
o +ranhes to general e@eption handler 9different from ;1#+ miss handler:.
*hat 8S does on 1#+ miss:
o "irst determine what aused miss.
o If 1#+ mod miss) he/ to see if proess has right to write page. ;sually stored in
page ta(le entry in one of unused (its. If has an write it) mar/ physial page as
dirty in 8S data strutures) set 0 (it in 1#+ entry and restart proess. 2ote: anAt
use random register to write 1#+ entry (a/ in. 1here is already a 1#+ entry with
the mathing VP2 and PI0. Must use tl(p to load inde@ register with the inde@ of
the mathing entry) then store new page ta(le entry into ,ntry #ow register) then
tl(wi to store new 1#+ entry (a/ into the 1#+.
o If 1#+ aused (y dou(le miss from ;1#+ miss handler) 9find this out (y seeing
of ,PC points inside ;1#+ miss handler:) first determine if gi$en address is
$alid. 0etermine this (y he/ing if it is within range of proess $irtual address
spae. 1hen determine if page ta(le page is resident. If so) onstrut mapping for
page ta(le page and put it into 1#+. ;se this mapping to get 1#+ entry for page.
Insert this entry into 1#+ and return to user program.
o If page ta(le page not resident 9this is for a normal /ernel 1#+ miss in per=
proess /ernel spae:) read it in from dis/. *hen page arri$es) set up page ta(le
entry. Set $alid (it) ma/e P"2 point to page frame where it was read in. Clear 0
(it. Map page ta(le page into 1#+ and proeed as a(o$e.
o If 1#+ aused (y /ernel mode referene not mapped) find the P1, for the /ernel
address and put it into 1#+) using entry hi and lo registers and random register.
Return to ode that aused miss.
o If miss aused (y referene to in$alid page in user address spae) read page in
from dis/) set $alid (it and P"2 in page ta(le. Also) (e sure to lear 0 (it so that
any write referene will ause a trap. 1he 8S will use this trap to mar/ the P"2
dirty.
Alternati$es:
o 1he 8S may run ompletely unmapped. Pro(lem: anAt page 8S data strutures.
o 1he 8S may ha$e a separate address spae from user. Pro(lem: anAt as easily
aess user spae.
o Cahe may (e $irtually addressed. Pro(lem: anAt map same memory in different
addresses in same proess. !ow do implement ;ni@ mmap faility) whih
demands that different $irtual addresses map to same physial address6 Also) if
ahe does not ha$e PI0 field) must flush ahe on onte@t swith 9D:.
o 1#+ may not ha$e PI0 field. Pro(lem: must flush 1#+ on onte@t swith.
o 1#+ reload may (e done automatially in hardware. ,ah page ta(le entry is 3-
(its 9lower 3- (its of 1#+ entry a(o$e:) and hardware will automatially reload
1#+. Conte@t swith must load page ta(le (ase and (ounds registers. Pro(lem:
lo/s 8S into using a speifi data struture for page ta(le.