Académique Documents
Professionnel Documents
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NI Build Your Own Embedded System Workshop
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Extend Your Current LabVIEW Skills
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Project Explorer
Manage and organize all
system resources, including
I/O and deployment targets
Front Panel
Create event-driven user
interfaces to control systems
and display measurements
Block Diagram
Define and customize the
behavior of your system
using graphical programming
Instant Compilation
See the state of
your application at
all times, instantly
Parallel Programming
Create independent loops
that automatically execute
in parallel
Analysis Libraries
Use high-performance
analysis libraries designed
for engineering and science
Hardware Connectivity
Bring real-world signals into
LabVIEW from any I/O on
any instrument
Timing
Define explicit execution
order and timing with
sequential data flow
Deployment Targets
Deploy LabVIEW code to the
leading desktop, real-time,
and FPGA hardware targets
Models of Computation
Combine and reuse .m files,
C code, and HDL with
graphical code
LabVIEW System Design Software
Accelerates Your Success
By abstracting low-level complexity and integrating all of the tools you need to build any measurement or control system
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Complete
System IDE
Windows + Desktop PC Application
Real-Time OS + Processor Application
FPGA Configuration/Application
System Design Tool
LabVIEW System Development Environment
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Complete
System IDE
Math and
Analysis
LabVIEW System Development Environment
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.m File Scripts
Graphical Graphical
.m File Scripts
Complete
System IDE
Math and
Analysis
Reuse of
Existing Code
LabVIEW System Development Environment
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Complete
System IDE
Math and
Analysis
Reuse of
Existing Code
Graphical Syntax
VHDL
LabVIEW System Development Environment
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Graphical Syntax
Text
Code
Complete
System IDE
Math and
Analysis
Reuse of
Existing Code
LabVIEW System Development Environment
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Complete
System IDE
Math and
Analysis
Reuse of
Existing Code
Graphical
Debugging
LabVIEW System Development Environment
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Complete
System IDE
User
Interface
Math and
Analysis
Reuse of
Existing Code
Graphical
Debugging
LabVIEW System Development Environment
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The NI Approach to Flexible Hardware
NI LabVIEW RIO Architecture
Processor
Real-time OS
Application software
Networking and
peripheral I/O drivers
DMA, interrupt, and
bus control drivers
FPGA
Application IP
Control IP
DSP IP
Specialized I/O drivers
and interface
DMA controller
Highly Productive LabVIEW Graphical Programming Environment
for Programming Host, FPGA, I/O, and Bus Interfaces
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~4000 lines of VHDL
Acquire analog data point-by-point
Transfer analog data to host
CPU via DMA FIFO for data
logging, display, etc.
Abstraction of Hardware Complexities
LabVIEW FPGA vs. VHDL
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Fire Suppression System
Fire Suppression System
We were able to rapidly prototype our system for FedEx with LabVIEW and CompactRIO and
create a final deployed solution with NI Single-Board RIOall in under a year.
Jeremy Snow, Ventura Aerospace
Ventura Aerospace
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With National Instruments LabVIEW and NI CompactRIO, we were able to reduce our
development cost by $250,000. In addition, we were able to reduce our development time
from four months to four weeks, and avoid the necessity of developing
custom control software and drivers.
Daryl Farr, KCBioMedix Inc.
Biomedical Device KCBioMedix
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NI-RIO Evaluation hardware
Xilinx Spartan-6 LX45 FPGA
400 MHz Real-Time Controller
AI, AO, DIO, LCD Screen
90-day extended evaluation
version of NI LabVIEW, Real-Time and
FPGA Modules
Step-by-Step Tutorials
All necessary cables and accessories
Online Community Support
NI LabVIEW RIO Evaluation Kit
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[ The Challenge]
Create an Electric Vehicle Battery
Management System
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Battery Management System
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Battery Management System
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Data Communication Diagram
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Simulating Signal I/O
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BYOES Workshop Agenda
Networking and Hardware Configuration
LabVIEW FPGA/Real-Time Environment Tour
Introduction to LabVIEW FPGA
Introduction to LabVIEW Real-Time
Communicating between Targets
System Deployment and Replication
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Build Your Own Embedded System:
NI reconfigurable I/O (RIO) Hardware Configuration
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Networking Concepts
Ways to obtain an IP address?
1. Dynamic Assignment
DHCP
DHCP Server
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Networking Concepts
Ways to obtain an IP address?
1. Dynamic Assignment
DHCP
Link Local
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Networking Concepts
Ways to obtain an IP address?
1. Dynamic Assignment
DHCP
Link Local
2. Static Assignment
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Networking Concepts
Subnet Mask
XXX.XXX.XXX.XXX each between 0-255
Designates who is in the local network in relation to your target
Think of it as a neighborhood
Subnet: 255.255.0.0
Means: 10.0.x.x must match
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Our Network Setup
By default the LabVIEW RIO Evaluation Kit comes set as
dynamic assigned IP address
For this workshop set both the evaluation target and your
laptop to a statically assigned IP address
NI Recommends Using a Dynamic DHCP Enabled Network
Before Leaving Today, Set the Assignment Back to Dynamic
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Hardware Configuration
NI MAX
Set PC & Target IP Address
Install Software/Firmware
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[Exercise 0]
Configure Your Target
Setup and install software on your embedded system
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[Demo]
Explore the LabVIEW Project
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[Exercise 1]
Open and Run Application
Explore a simple RIO-based embedded system
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Build Your Own Embedded System:
Introduction to LabVIEW FPGA
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Field-Programmable Gate Array (FPGA)
Configurable Logic Blocks (CLBs)
Implement logic using flip-flops and LUTs
Multipliers and DSPs
Implement signal processing using
multiplier and multiplier-accumulate circuitry
Memory Blocks
Store data sets or values in user defined RAM
Programmable Interconnects
Route signals through the FPGA matrix
I/O Blocks
Directly access digital and analog I/O
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FPGAs Are Dataflow Systems
A
B
C
D
F
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Parallel Processing
A
B
C
D
F
W
X
Y Z
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VI = Program or Function
Block Diagram = Code
Project = System Configuration
LabVIEW Environment Basics
Front Panel = User Interface
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VI = Application
Block Diagram= Code
Project = System Configuration
LabVIEW FPGA
Front Panel= Interface Elements I/O Node
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begin
LED <= LED_local;
process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if ToggleLED then
LED_local <= not LED_local;
end if;
end if;
end process;
CounterProc: process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if CounterValue = kCounterTC then
CounterValue <= (others => '0');
ToggleLED <= true;
else
CounterValue <= CounterValue + 1;
ToggleLED <= false;
end if;
end if;
end process CounterProc;
end rtl;
LabVIEW FPGA vs. VHDL: Blink an LED
VHDL Implementation
Physical wire connection to LED
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begin
LED <= LED_local;
process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if ToggleLED then
LED_local <= not LED_local;
end if;
end if;
end process;
CounterProc: process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if CounterValue = kCounterTC then
CounterValue <= (others => '0');
ToggleLED <= true;
else
CounterValue <= CounterValue + 1;
ToggleLED <= false;
end if;
end if;
end process CounterProc;
end rtl;
Physical wire connection to LED
Toggle the physical LED when
internal timing signal ToggleLED
is true. Executes every tick of the
50Mhz clock.
LabVIEW FPGA vs. VHDL: Blink an LED
VHDL Implementation
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begin
LED <= LED_local;
process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if ToggleLED then
LED_local <= not LED_local;
end if;
end if;
end process;
CounterProc: process (CLK_50MHZ)
begin
if rising_edge(CLK_50MHZ) then
if CounterValue = kCounterTC then
CounterValue <= (others => '0');
ToggleLED <= true;
else
CounterValue <= CounterValue + 1;
ToggleLED <= false;
end if;
end if;
end process CounterProc;
end rtl;
Physical wire connection to LED
Toggle the physical LED when
internal timing signal ToggleLED
is true. Executes every tick of the
50Mhz clock.
LabVIEW FPGA vs. VHDL: Blink an LED
VHDL Implementation
Counter establishes the timing of
the ToggleLED signal. Goes
true when the counter reaches
50,000,000 (1 second) and resets
counter.
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LabVIEW FPGA vs. VHDL: Blink an LED
LabVIEW Implementation
LED I/O Resource
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NOT (Toggle)
LabVIEW FPGA vs. VHDL: Blink an LED
LabVIEW Implementation
LED I/O Resource
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Loop Timing (1000ms)
NOT (Toggle)
LED I/O Resource
LabVIEW FPGA vs. VHDL: Blink an LED
LabVIEW Implementation
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Why Are FPGAs Useful?
True Parallelism Provides parallel tasks and pipelining
High Reliability Designs become a custom circuit
High Determinism Runs algorithms at deterministic
rates down to 25 ns (faster in many cases)
Reconfigurable Create new and alter existing task-
specific personalities
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Parallel Processing
A
B
C
D
F
W
X
Y Z
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High Reliability and Determinism
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Decision Making in Software
~25 ms
Response
Outputs
System
or Device
Multiple Software Layers
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High Reliability and Determinism
H
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t
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o
n
~25 ns
Response
Outputs
UUT
Decision Making in Hardware
Highest Reliability
Highest
Determinism
System
or Device
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Enables rapid development iterations
Decreases long-term maintenance
Reduces overall design cost
Reconfigurable
FPGAs Custom Circuits ASICs
vs.
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Common Applications
High-speed control
Custom data acquisition
Digital communication protocols
Inline signal processing
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High-Speed Control
This design can achieve loop rates up to the 100-500 kHz range
on CompactRIO
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Custom Triggered Analog Input
Custom timing & synchronization
Multi-rate sampling
Custom counters
Flexible PWM
Flexible encoder interface
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Digital Communication Protocol APIs
SPI:
I2C:
Serial:
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Inline Signal Processing and Data Reduction
Inputs
Analog voltages
Digital communications
Sensor signals
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Inline Signal Processing and Data Reduction
Inputs
FPGA Processing
Encoding/decoding
Filtering/averaging
Modulation/demod
Decimation
Stream processing
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Inline Signal Processing and Data Reduction
Outputs
DMA preprocessed data
Save to file
Transfer over network
Further actions
Streaming from input
to output without host
involvement
Analog voltages
Digital communications
Motor/actuator drives
Data
Transfer
FPGA Processing
Encoding/decoding
Filtering/averaging
Modulation/demod
Decimation
Stream processing
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Application Architecture
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Exercise 2: Control/Indicator Names
The control/indicator names must have the exact same spelling,
capitalization, and spacing as shown above
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[Exercise 2]
Create an FPGA Application to
Acquire & Analyze Data
Program a LabVIEW FPGA VI to acquire data and control I/O on the
Battery Management System
Challenge Exercise: Implement Data Logging by pressing the
center Push Button (PB3). A few customer solutions are provided
with the exercises.
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Exercise 2 Recap
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Simplified FPGA Design Flow
Design
Entry
Simulation
Compilation
Deployment
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Design
Entry
Simulation
Compilation
Deployment
Interface Abstraction
HDL/IP Integration
Configuration-Based
Simplified FPGA Design Flow
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Interface Abstraction
I/O Interfaces to NI and 3
rd
party I/O modules
Built-in DMA FIFO interfaces
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Configuration-Based Design
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Reuse of Existing HDL Algorithms
Increase application development efficiency and leverage
existing team expertise
Similar to calling a DLL in LabVIEW for the desktop
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity DemoClipAdder is
port (
clk : in std_logic;
aReset : in std_logic;
cPortA : in std_logic_vector(15 downto 0);
cPortB : in std_logic_vector(15 downto 0);
cAddOut : out std_logic_vector(15 downto 0)];
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Design
Entry
Simulation
Compilation
Deployment
Simulation Tools
Interactive Window Debugging
Interface Abstraction
HDL/IP Integration
Configuration-Based
Simplified FPGA Design Flow
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Be More Productive with LabVIEW FPGA
Verify Faster
Verify Code using Simulated I/O
Use the Desktop Execution Node to
verify code by developing test benches
using simulated or file generated I/O
Verify Signal Timing with Waveform
Probe
Use the Digital Waveform Probe to probe
your signals relative to one another and
view history
Debug with Standard LabVIEW Features
in Simulation
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LabVIEW FPGA Desktop Execution Node
Test Harness
Unit Test
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Interactive Front Panel Window
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Design
Entry
Simulation
Compilation
Deployment
Simulation Tools
Interactive Window Debugging
Interface Abstraction
HDL/IP Integration
Configuration-Based
Simplified FPGA Design Flow
One-click automation
of the Xilinx Tools
Local Computer,
Server, or Cloud
Compilation
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Compilation Process
LabVIEW FPGA Code FPGA Logic Implementation Compile VHDL through Xilinx
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Compilation Process
LabVIEW FPGA Code FPGA Logic Implementation Compile VHDL through Xilinx
Translation
VHDL
Generation
Optimization
Analysis &
Logic
Reduction
Synthesis
Place & Route
Timing
Verification
Bit Stream
Generation
Download &
Run
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One-Click Deployment and Compilation
Development
PC
Compile
Server and
Workers
High-
Performance
Cloud
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Design
Entry
Simulation
Compilation
Deployment
Simplified FPGA Design Flow
Simulation Tools
Interactive Window Debugging
Interface Abstraction
HDL/IP Integration
Configuration-Based
One-click automation
of the Xilinx Tools
Local Computer,
Server, or Cloud
Compilation
Packaged and Board-level
Hardware Options
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LabVIEW RIO Hardware
CompactRIO and NI Single-Board RIO
Value
PXI, PC RIO (R Series, NI FlexRIO)
High Performance
Expansion I/O
MXI-Express RIO Ethernet RIO Wireless EtherCAT RIO
Performance
Value
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Discussion: LabVIEW FPGA
When is an FPGA useful?
How would an FPGA improve your
application?
What programming resources are available?
ni.com
Identify Your Training Path
Walk through the exercise in Appendix A to map your application needs
to the appropriate LabVIEW RIO training path.
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LabVIEW for CompactRIO Training Courses
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The Fastest Route to Proficiency
Online Training included with your software service subscription
Available Courses
LabVIEW FPGA
LabVIEW Real-Time
LabVIEW Real-Time 2:
Architecting Embedded Systems
LabVIEW Core 1
LabVIEW Core 2
LabVIEW Core 3
Advanced Architectures in
LabVIEW
Object Oriented Design and
Programming in LabVIEW
And more
ni.com/self-paced-training
ni.com
Build Your Own Embedded System:
Introduction to LabVIEW Real-Time
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What is Real-Time?
Real-time does not always mean really fast
Real-time means absolute reliability
Real-time systems have timing constraints that
must be met to avoid failure
Determinism is the ability to complete a task
within a fixed amount of time
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Critical Applications to Consider
Event Response Closed-Loop Control Critical Tests
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When General Purpose OSs Fall Short
Design for fairness and user responsiveness vs.
strictly prioritizing tasks
Focus on multitasking instead of maximum reliability
and uptime
Different design goals, not the result of bad products
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Key Careabouts for Critical Applications
Jitter: execution time variability of a given operation or
application
Execution
Time (ms)
Iterations
2
1.9
2.1
1.3
2.8
2.1
Mean = 2.03 ms
Jitter
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Key Careabouts for Critical Applications
Determinism: a condition that is met if an operation or
application has bounded jitter
Execution
Time (ms)
Iterations
2
1.9
2.1
1.3
2.8
2.1
Mean = 2.03 ms
Jitter
Bound
(for hard
real-time
systems)
n
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[Demo]
General Purpose OS vs.
Real-Time OS Jitter
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Operating System Characteristics
General Purpose OS
High-priority tasks can be
preempted by lower-priority
tasks
Extraneous background
programs
- Screen savers, disk utilities,
virus software
Peripheral Interrupts
- Mouse, keyboard, etc.
Real-Time OS
Scheduler ensures high-priority
tasks execute first
Direct control over all tasks
Stand-alone (no peripherals)
Loop Rate Software
Jitter
10100 Hz Unbounded
Up to
50kHz
Bounded
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Real-Time System Design
Real-Time Operating System (RTOS)
Editor, Compiler, and
Linker
Debugging and
Analysis Tools
Board Support Additional I/O Drivers
Development
Tools
System
Components
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LabVIEW Real-Time
LabVIEW Real-Time
Target
Linker
System Analysis Tools
RTOS
Microprocessor
I/O Connectivity
Compiler
Debugger
Real-Time Development Tools
Development
Software
Real-Time
Hardware
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Flexible Software Integration with NI Linux Real-Time
Code Reuse
Integrate existing applications and libraries
Develop, debug and deploy C/C++ code
Use Eclipse or IDE of choice
Leverage the Linux ecosystem
Interoperate with LabVIEW-programmed
FPGA
Programmable Hardware
Offload critical, decision-making code to
the FPGA
Reliable, precision timing for control or
processing
Achieve high-speed, high-accuracy I/O
Use graphical programming to leverage
FPGA technology without HDL expertise
FPGA
Modular I/O
Real-Time
Processor
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LabVIEW MathScript RT Module
Text-based controls, signal
processing, analysis, and math
900 built-in functions / user-defined
functions
Reuse many of your .m file scripts
created with The MathWorks, Inc.
MATLAB