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School of Computer Sciences

Universiti Sains Malaysia

CST131 Computer Organisation
Academic Session 2014/2015 Semester 1

TUTORIAL 3 (Answer)
Computer Arithmetic


1. Briefly explain the following representations: sign magnitude and twos
complement.

SignMagnitude Representation: In an N-bit word, the left-most bit is the
sign (0 = positive, 1 = negative) and the remaining N 1 bits comprise the
magnitude of the number.
Twos Complement Representation: A positive integer is represented as in
sign magnitude. A negative number is represented by taking the Boolean
complement of each bit of the corresponding positive number, then adding 1
to the resulting bit pattern viewed as an unsigned integer.

2. What is the difference between the twos complement representation of a number
and the twos complement of a number?

The twos complement representation of a number is the bit pattern used to
represent an integer. The twos complement of a number is the operation that
computes the negation of a number in twos complement representation.

3. If we treat 2 twos complement numbers as unsigned integers for purposes of
addition, the result is correct if interpreted as a twos complement number. This is
not true for multiplication. Why?

The algorithm for performing twos complement addition involves simply
adding the two numbers in the same way as for ordinary addition for
unsigned numbers, with a test for overflow. For multiplication, if we treat the
bit patterns as unsigned numbers, their magnitude is different from the twos
complement versions and so the magnitude of the result will be different.












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4. Explain Booths algorithm for twos complement multiplication.

































The multiplier and multiplicand are placed in the Q and M registers,
respectively. There is also a 1-bit register placed logically to the right of the least
significant bit (Q
0
) of the Q register and designated Q
-1
; its use is explained
shortly. The results of the multiplication will appear in the A and Q registers. A
and Q
-1
are initialized to 0. As before, control logic scans the bits of the multiplier
one at a time. Now, as each bit is examined, the bit to its right is also examined. If
the two bits are the same (11 or 00), then all of the bits of the A, Q, and Q
-1

registers are shifted to the right 1 bit. If the two bits differ, then the multiplicand
is added to or subtracted from the A register, depending on whether the two bits
are 01 or 10. Following the addition or subtraction, the right shift occurs. In
either case, the right shift is such that the leftmost bit of A, namely A
n-1
not only
is shifted into A
n-2
, but also remains in A
n-1
. This is required to preserve the sign
of the number in A and Q. It is known as an arithmetic shift, because it preserves
the sign bit.


Q
0
, Q
-1

Arithmetic Shift
Right: A Q, Q
-1

count =count -1
A=A-M
A=A+M
=10 =01

count=0?
NO
YES
END
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5. Is the following a valid alternative definition of overflow in twos complement
arithmetic?
If the exclusive-OR of the carry bits into and out of the leftmost column is 1,
then there is an overflow condition. Otherwise, there is not.

The overflow rule was stated as follows: If two numbers are added, and
they are either both positive or both negative, then overflow occurs if and
only if the result has the opposite sign. There are four cases:
Both numbers positive (sign bit = 0) and no carry into the leftmost
bit position: There is no carry out of the leftmost bit position, so
the XOR is 0. The result has a sign bit = 0, so there is no overflow.
Both numbers positive and a carry into the leftmost bit position:
There is no carry out of the leftmost position, so the XOR is 1. The
result has a sign bit = 1, so there is overflow.
Both numbers negative and no carry into the leftmost position:
There is a carry out of the leftmost position, so the XOR is 1. The
result has a sign bit of 0, so there is overflow.
Both numbers negative and a carry into the leftmost position.
There is a carry out of the leftmost position, so the XOR is 0. The
result has a sign bit of 1, so there is no overflow.
Therefore, the XOR result always agrees with the presence or absence of
overflow.



























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6. Multiply -13

by -5

using Booths algorithm for twos complement multiplication.
Each number is represented using 5 bits.

M = -13 = 10011; +13 = 01101
Q = -5 = 11011; +5 = 00101

A Q Q
-1
M Remarks
00000 11011 (-5) 0 10011 (-13) Initial values
00000 CYCLE 1
01101 -(-13) = +13 A = A M (10 @ Q
0
, Q
-1
)
01101 11011
00110 11101 1 Shift A, Q, Q
-1
to the right
CYCLE 2
00011 01110 1 Shift (11 @ Q
0
, Q
-1
)
00011 CYCLE 3
10011 +(-13) A = A + M (01 @ Q
0
, Q
-1
)
10110 01110
11011 00111 0 Shift
11011 CYCLE 4
01101 -(-13) = +13 A = A M (10 @ Q
0
, Q
-1
)
01000 00111
00100 00011 1 Shift A, Q, Q
-1
to the right
CYCLE 5
00010 00001 1 Shift (11 @ Q
0
, Q
-1
)

A, Q = 00010 00001 = 65























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7. Use the Booth algorithm to multiply 25 by 30, where each number is represented
using 6 bits.

M = 25 = 011001; -25 = 100111
Q = 30 = 011110

A Q Q-1 M Remarks
000000 011110 0 011001 Initial Values
000000 Cycle 1
000000 001111 0 Shift (00 @ Q
0
, Q
-1
)
000000 Cycle 2
100111 (25) = -25 A = A M (10 @ Q
0
, Q
-1

100111 001111
110011 100111 1 Shift A, Q, Q
-1
to the right
Cycle 3
111001 110011 1 Shift (11 @ Q
0
, Q
-1
)
Cycle 4
111100 111001 1 Shift (11 @ Q
0
, Q
-1
)
Cycle 5
111110 011100 1 Shift (11 @ Q
0
, Q
-1
)
111110 Cycle 6
011001 +25 A = A + M (01 @ Q
0
, Q
-1
)
010111 011100
001011 101110 0 Shift A, Q, Q
-1
to the right

A, Q = 001011 101110 = 750























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